On Tue, Oct 24, 2023 at 11:30 AM Akihiko Odaki wrote:
>
> On 2023/10/24 0:45, Cédric Le Goater wrote:
> > From: Cédric Le Goater
> >
> > Hello,
> >
> > Here is a little series adding FLR to the new IGB models.
> >
> > Thanks,
> >
> > C.
> >
> > Changes in v2:
> >
> > - add a "x-pcie-flr-init"
On 26.10.23 22:56, Stefano Stabellini wrote:
On Thu, 26 Oct 2023, David Woodhouse wrote:
On Thu, 2023-10-26 at 13:36 -0700, Stefano Stabellini wrote:
This seems like a lot of code to replace that simpler option... is
there a massive performance win from doing it this way? Would we want
to
On Thu, 2023-10-26 at 10:27 -0500, Ninad Palsule wrote:
> Hello Cedric,
>
>
> On 10/24/23 10:21, Cédric Le Goater wrote:
> > On 10/24/23 17:00, Ninad Palsule wrote:
> > > Hello Cedric,
> > >
> > > On 10/24/23 02:46, Cédric Le Goater wrote:
> > > > and the fsi_opb_* routines are useless to me.
>
On 25/10/23 08:56, Cédric Le Goater wrote:
On 10/24/23 23:29, Glenn Miles wrote:
Power9 is supposed to have 4 PIB-connected I2C engines with the
following number of ports on each engine:
0: 2
1: 13
2: 2
3: 2
Power10 also has 4 engines but has the following number of ports
On 26/10/23 16:00, Cédric Le Goater wrote:
On 10/26/23 09:06, Cédric Le Goater wrote:
Hello,
This series fixes a buffer overrun in VFIO. The buffer used in
vfio_realize() by qemu_uuid_unparse() is too small, UUID_FMT_LEN lacks
one byte for the trailing NUL.
Instead of adding + 1, as done
I'm trying to fill in QMP documentation holes, and found one in commit
415442a1b4a (this patch). Details inline.
Jonathan Cameron writes:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
>
On 10/26/23 02:13, Richard Henderson wrote:
+case TCG_COND_TSTEQ:
+case TCG_COND_TSTNE:
+if (b_const && is_power_of_2(b)) {
+tbit = ctz64(b);
+need_cmp = false;
+}
I think another value that can be handled efficiently is 0x
which becomes
Stefan Hajnoczi writes:
> On Thu, 26 Oct 2023 at 14:32, Markus Armbruster wrote:
>>
>> Requires Brian's pull request and two patches from Thomas to compile:
>>
>> [PULL 0/2] hex queue - GETPC() fixes, shadowing fixes
>> [PATCH v2] block/snapshot: Fix compiler warning with -Wshadow=local
On 10/25/23 23:35, Michael Tokarev wrote:
24.05.2023 08:46, Richard Henderson:
The beginning of the structure, with pretaddr, should be just below
16-byte alignment. Disconnect fpstate from sigframe, just like the
kernel does.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1648
On 10/25/23 23:20, Zhao Liu wrote:
On Mon, Sep 25, 2023 at 03:14:53AM -0400, EwanHai wrote:
Date: Mon, 25 Sep 2023 03:14:53 -0400
From: EwanHai
Subject: [PATCH] target/i386/kvm: Refine VMX controls setting for backward
compatibility
X-Mailer: git-send-email 2.34.1
Commit 4a910e1
On Thu, Oct 26, 2023 at 10:20:41AM -0400, Peter Xu wrote:
> Could you elaborate why is that important? In what use case?
I was not involved in the formulation of the IOPMP specification, but I'll try
to explain my perspective. IOPMP use the same the idea as PMP. "The matching
PMP entry must
Console logs from the VM can be useful for debugging when things go wrong.
Other avocado tests enables them. This change enables console logging with the
following changes:
- point to the newer bios bits image that actually enabled VM console.
- change the bits test to drain the console logs
QEMU defaults to 64-bit entry point since the following commit
bf376f3020 ("hw/i386/pc: Default to use SMBIOS 3.0 for newer machine models")
The above change is applicable for all newer machine versions from version 8.1
and newer. i440fx and q35 machine versions 8.0 and older still use 32-bit
Included are couple of bios bits test fixes.
32-bit SMBIOS entry point is enforced.
Console logging is enabled.
I have tested these changes in the CI pipeline here and the test seems
to pass:
https://gitlab.com/anisinha/qemu/-/jobs/5380627517
Log:
> -Original Message-
> From: Stefan Hajnoczi
> Sent: Thursday, October 26, 2023 7:52 PM
> To: Markus Armbruster
> Cc: qemu-devel@nongnu.org; pbonz...@redhat.com;
> marcandre.lur...@redhat.com; berra...@redhat.com; th...@redhat.com;
> phi...@linaro.org; Brian Cain ; i...@bsdimp.com;
>
On 10/26/23 02:14, Richard Henderson wrote:
+} else if ((i & ~0xff00) == 0 && r < 4) {
+tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, r);
Should be "r + 4".
Paolo
+tcg_out8(s, i >> 8);
} else {
On 10/26/23 02:13, Richard Henderson wrote:
+
+sh = ctz64(val);
+ret = op->args[0];
+src1 = op->args[1];
+inv = cond == TCG_COND_TSTEQ;
+
+if (neg && !inv && sext_opc) {
+op->opc = sext_opc;
+op->args[1] = src1;
+op->args[2] = sh;
+op->args[3]
>From 4af1fca6e5c99578a5b80b834c22b70f6419639f Mon Sep 17 00:00:00 2001
From: Brendan Sweeney
Date: Thu, 26 Oct 2023 17:01:29 -0500
Subject: [PATCH] Support for the RISCV Zalasr extension
Signed-off-by: Brendan Sweeney
---
target/riscv/cpu.c | 2 +
target/riscv/cpu_cfg.h | 1 +
On Thu, 26 Oct 2023 at 14:32, Markus Armbruster wrote:
>
> Requires Brian's pull request and two patches from Thomas to compile:
>
> [PULL 0/2] hex queue - GETPC() fixes, shadowing fixes
> [PATCH v2] block/snapshot: Fix compiler warning with -Wshadow=local
> [PATCH v2] migration/ram:
On Fri, 27 Oct 2023 at 00:25, Juan Quintela wrote:
>
> Stefan Hajnoczi wrote:
> > On Tue, 24 Oct 2023 at 23:45, Juan Quintela wrote:
> >>
> >> The following changes since commit
> >> a95260486aa7e78d7c7194eba65cf03311ad94ad:
> >>
> >> Merge tag 'pull-tcg-20231023' of
Hi David,
Thank you very much for the Reviewed-by in another thread.
I have re-based the patch and sent again.
https://lore.kernel.org/all/20231026211938.162815-1-dongli.zh...@oracle.com/
Dongli Zhang
On 10/26/23 09:39, Dongli Zhang wrote:
> Hi David,
>
> On 10/26/23 08:39, David Woodhouse
While the default "info lapic" always synchronizes cpu state ...
mon_get_cpu()
-> mon_get_cpu_sync(mon, true)
-> cpu_synchronize_state(cpu)
-> ioctl KVM_GET_LAPIC (taking KVM as example)
... the cpu state is not synchronized when the apic-id is available as
argument.
The cpu state
On Thu, 26 Oct 2023, David Woodhouse wrote:
> On Thu, 2023-10-26 at 13:36 -0700, Stefano Stabellini wrote:
> >
> > > This seems like a lot of code to replace that simpler option... is
> > > there a massive performance win from doing it this way? Would we want
> > > to use this trick for the Xen
Hi everybody,
the mechanism for a (Linux) guest to signal a regular shutdown event to
QEMU seems fairly architecture specific and dependent on kernel
configuration.
The existing pvpanic protocol [0] could be extended fairly easily to
also cover these events.
Any thoughts?
Thanks,
Thomas
[0]
On Thu, 2023-10-26 at 13:36 -0700, Stefano Stabellini wrote:
>
> > This seems like a lot of code to replace that simpler option... is
> > there a massive performance win from doing it this way? Would we want
> > to use this trick for the Xen PV backends (qdisk, qnic) *too*? Might it
> > make
On Thu, 26 Oct 2023, David Woodhouse wrote:
> On Thu, 2023-10-26 at 11:07 -0700, Stefano Stabellini wrote:
> > On Thu, 26 Oct 2023, David Woodhouse wrote:
> > > On Wed, 2023-10-25 at 14:24 -0700, Vikram Garhwal wrote:
> > > > Hi,
> > > > This patch series add support for grant mappings as a pseudo
On Thu, 2023-10-26 at 11:07 -0700, Stefano Stabellini wrote:
> On Thu, 26 Oct 2023, David Woodhouse wrote:
> > On Wed, 2023-10-25 at 14:24 -0700, Vikram Garhwal wrote:
> > > Hi,
> > > This patch series add support for grant mappings as a pseudo RAM region
> > > for Xen.
> > >
> > > Enabling
On Thu, Oct 26, 2023 at 04:08:20PM -0400, Peter Xu wrote:
> On Thu, Oct 26, 2023 at 08:43:59PM +0100, Joao Martins wrote:
> > Considering we aren't including any downtime timestamps in the tracing, is
> > this
> > a way to say that the tracing tool printing timestamps is what we use to
> >
SORRY for the noise, I type the wrong send-mail command, please ignore this
resend of V2 - steve
On 10/26/2023 4:08 PM, Steve Sistare wrote:
> Add a mode migration parameter that can be used to select alternate
> migration algorithms. The default mode is normal, representing the
> current
Create a mode migration parameter that can be used to select alternate
migration algorithms. The default mode is normal, representing the
current migration algorithm, and does not need to be explicitly set.
No functional change until a new mode is added, except that the mode is
shown by the
Extend the blocker interface so that a blocker can be registered for
one or more migration modes. The existing interfaces register a
blocker for all modes, and the new interfaces take a varargs list
of modes.
Internally, maintain a separate blocker list per mode. The same Error
object may be
Some blockdevs block migration because they do not support sharing across
hosts and/or do not support dirty bitmaps. These prohibitions do not apply
if the old and new qemu processes do not run concurrently, and if new qemu
starts on the same host as old, which is the case for cpr. Narrow the
vhost blocks migration if logging is not supported to track dirty
memory, and vhost-user blocks it if the log cannot be saved to a shm fd.
vhost-vdpa blocks migration if both hosts do not support all the device's
features using a shadow VQ, for tracking requests and dirty memory.
vhost-scsi
On Thu, Oct 26, 2023 at 08:43:59PM +0100, Joao Martins wrote:
> Considering we aren't including any downtime timestamps in the tracing, is
> this
> a way to say that the tracing tool printing timestamps is what we use to
> extract
> downtime contribution?
>
> It might be obvious, but perhaps
Add the cpr-reboot migration mode. Usage:
$ qemu-system-$arch -monitor stdio ...
QEMU 8.1.50 monitor - type 'help' for more information
(qemu) migrate_set_capability x-ignore-shared on
(qemu) migrate_set_parameter mode cpr-reboot
(qemu) migrate -d file:vm.state
(qemu) info status
VM status:
Add a mode migration parameter that can be used to select alternate
migration algorithms. The default mode is normal, representing the
current migration algorithm, and does not need to be explicitly set.
Provide the cpr-reboot (CheckPoint and Restart) migration mode for live
update, which saves
Signed-off-by: Steve Sistare
---
tests/qtest/migration-test.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index e1c1105..de29fc5 100644
--- a/tests/qtest/migration-test.c
+++
On Thu, Oct 26, 2023 at 08:33:13PM +0100, Joao Martins wrote:
> Sure. For the fourth patch, feel free to add Suggested-by and/or a Link,
> considering it started on the other patches (if you also agree it is right).
> The
> patches ofc are enterily different, but at least I like to believe the
On 26/10/2023 20:01, Peter Xu wrote:
> Add tracepoints for major downtime checkpoints on both src and dst. They
> share the same tracepoint with a string showing its stage.
>
> On src, we have these checkpoints added:
>
> - downtime-start: right before vm stops on src
> - vm-stopped: after
On 26/10/2023 19:18, Peter Xu wrote:
> On Thu, Oct 26, 2023 at 01:03:57PM -0400, Peter Xu wrote:
>> On Thu, Oct 26, 2023 at 05:06:37PM +0100, Joao Martins wrote:
>>> On 26/10/2023 16:53, Peter Xu wrote:
This small series (actually only the last patch; first two are cleanups)
wants to
On Thu, 26 Oct 2023 09:10:43 +0200
Cédric Le Goater wrote:
> and drop warning when ENOTTY is returned. Only useful for the mdev-mtty
> driver today, which has partial support for INTx: the AUTOMASK
> behavior is not implemented.
FWIW, I prefer not to carry a sentence through from subject to
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Friday, October 13, 2023 9:01 AM
> To: qemu-devel@nongnu.org
> Cc: Eduardo Habkost ; Xiaojuan Yang
> ; Michael S. Tsirkin ; qemu-
> p...@nongnu.org; Aleksandar Rikalo ; David
> Hildenbrand ; qemu-s3...@nongnu.org; Edgar E.
Add tracepoints for major downtime checkpoints on both src and dst. They
share the same tracepoint with a string showing its stage.
On src, we have these checkpoints added:
- downtime-start: right before vm stops on src
- vm-stopped: after vm is fully stopped
- iterable-saved: after all
Yeah, I felt that it may not be a cakewalk as it might sound.
You're right, trying to understand the whole code is overwhelming. I'll
start with a small section instead.
I have interest in working on x86_64 and Aarch64 architectures within qemu.
Please let me know if there are any specific tasks
On Thu, Oct 26, 2023 at 01:03:57PM -0400, Peter Xu wrote:
> On Thu, Oct 26, 2023 at 05:06:37PM +0100, Joao Martins wrote:
> > On 26/10/2023 16:53, Peter Xu wrote:
> > > This small series (actually only the last patch; first two are cleanups)
> > > wants to improve ability of QEMU downtime analysis
On Thu, 26 Oct 2023, David Woodhouse wrote:
> On Wed, 2023-10-25 at 14:24 -0700, Vikram Garhwal wrote:
> > Hi,
> > This patch series add support for grant mappings as a pseudo RAM region for
> > Xen.
> >
> > Enabling grant mappings patches(first 6) are written by Juergen in 2021.
> >
> > QEMU
On Thu, Oct 26, 2023 at 05:14:49PM +0200, Andrew Jones wrote:
> On Thu, Oct 26, 2023 at 07:36:21AM -0700, Andrea Bolognani wrote:
> > On Mon, Oct 23, 2023 at 07:35:16PM +0200, Andrew Jones wrote:
> > > On Mon, Oct 23, 2023 at 02:00:00PM -0300, Daniel Henrique Barboza wrote:
> > > > On 10/23/23
On Thu, Oct 26, 2023 at 04:45:21PM +0100, David Woodhouse wrote:
> On Wed, 2023-10-25 at 18:23 -0700, Stefano Stabellini wrote:
> > On Thu, 26 Oct 2023, David Woodhouse wrote:
> > > On Wed, 2023-10-25 at 14:24 -0700, Vikram Garhwal wrote:
> > > > From: Juergen Gross
> > > >
> > > > Virtio
Peter Xu writes:
> Unify the three users on recording downtimes with the same pair of helpers.
>
> Signed-off-by: Peter Xu
Reviewed-by: Fabiano Rosas
On 10/25/23 20:44, Daniel Henrique Barboza wrote:
zic64b is defined in the RVA22U64 profile [1] as a named feature for
"Cache blocks must be 64 bytes in size, naturally aligned in the address
space". It's a fantasy name for 64 bytes cache blocks. RVA22U64
mandates this feature, meaning that
Peter Xu writes:
> Postcopy calculates its downtime separately. It always sets
> MigrationState.downtime properly, but not MigrationState.downtime_start.
>
> Make postcopy do the same as other modes on properly recording the
> timestamp when the VM is going to be stopped. Drop the temporary
On Thu, Oct 26, 2023 at 05:06:37PM +0100, Joao Martins wrote:
> On 26/10/2023 16:53, Peter Xu wrote:
> > This small series (actually only the last patch; first two are cleanups)
> > wants to improve ability of QEMU downtime analysis similarly to what Joao
> > used to propose here:
> >
> >
On 10/20/23 14:31, Philippe Mathieu-Daudé wrote:
diff --git a/target/hppa/machine.c b/target/hppa/machine.c
index 0c0bba68c0..ab34b72910 100644
--- a/target/hppa/machine.c
+++ b/target/hppa/machine.c
@@ -21,21 +21,12 @@
#include "cpu.h"
#include "migration/cpu.h"
-#if TARGET_REGISTER_BITS ==
> From: Dongli Zhang
>
> While the default "info lapic" always synchronizes cpu state ...
>
> mon_get_cpu()
> -> mon_get_cpu_sync(mon, true)
>-> cpu_synchronize_state(cpu)
> -> ioctl KVM_GET_LAPIC (taking KVM as example)
>
> ... the cpu state is not synchronized when the apic-id is
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence
This patchset introduces IBM's Flexible Service Interface(FSI).
Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.
FSI has long existed in POWER processes and so comes with
Added basic qtests for FSI model.
Signed-off-by: Ninad Palsule
Acked-by: Thomas Huth
---
v3:
- Added new qtest as per Cedric's comment.
V4:
- Remove MAINTAINER and documentation changes from this commit
v6:
- Incorporated review comments by Thomas Huth.
v7:
- Incorporated review comments by
This is a part of patchset where scratchpad is introduced.
The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not support any special management
support. The scratchpad registers can be read or written from LBUS
slave.
In this model, The
Added maintainer for IBM FSI model
Signed-off-by: Ninad Palsule
---
V4:
- Added separate commit for MAINTAINER change.
V5:
- Use * instead of listing all files in dir
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
Hello,
Please review the patch-set version 7.
I have incorporated review comments from Cedric, Philippe and Thomas.
Ninad Palsule (10):
hw/fsi: Introduce IBM's Local bus
hw/fsi: Introduce IBM's scratchpad
hw/fsi: Introduce IBM's cfam,fsi-slave
hw/fsi: Introduce IBM's FSI
hw/fsi: IBM's
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule
---
v4:
- Added separate commit for documentation
v7:
- Incorporated review comments by Cedric.
---
docs/specs/fsi.rst | 138 +++
docs/specs/index.rst | 1 +
2 files changed, 139
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration block presents engines in the
order they are
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a way that it is embedded inside the FSI master which is a
bus controller.
The FSI master: A controller in the platform service
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang
On Thu, 26 Oct 2023 at 13:48, Tanmay wrote:
> I'm really interested in contributing to qemu. I wanted to
> work on the renaming API calls cpu_physical_memory_* to
> address_space_*. I couldn't find any related issues on the
> GItlab tracker. Can I work on this issue?
You're welcome to, but be
Hi David,
On 10/26/23 08:39, David Woodhouse wrote:
> From: David Woodhouse
>
> Where the local APIC is emulated by KVM, we need kvm_get_apic() to pull
> the current state into userspace before it's printed. Otherwise we get
> stale values.
>
> Signed-off-by: David Woodhouse
> ---
>
On Thu, 2023-10-26 at 10:25 +0100, David Woodhouse wrote:
>
> > So it would have been entirely possible to use -initrd 'bzImage
> > console=hvc0 root=/dev/xvda1' if Xen worked like that.
>
> Xen does allow that too. I didn't realise our multiboot loader did though.
>
> So yes, you *can* use
Hi,
The above refactoring of functions was mentioned under API conversion at
https://wiki.qemu.org/Contribute/BiteSizedTasks .
Thanks,
Tanmay Patil
On Thu, 26 Oct 2023 at 15:54, Tanmay wrote:
> Hi,
>
> I'm really interested in contributing to qemu. I wanted to work on the
> renaming API calls
On Wed, 2023-10-25 at 14:24 -0700, Vikram Garhwal wrote:
> Hi,
> This patch series add support for grant mappings as a pseudo RAM region for
> Xen.
>
> Enabling grant mappings patches(first 6) are written by Juergen in 2021.
>
> QEMU Virtio device provides an emulated backends for Virtio
On 10/26/23 04:29, Paolo Bonzini wrote:
On 10/26/23 02:14, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
Also, a TST{EQ,NE} with a one-bit immediate argument can be changed to:
- a TEST reg, reg + js/jns (or sets/setns, or cmovs/cmovns) when testing bits
7, 15 or 31
- a BT
On 26/10/2023 16:53, Peter Xu wrote:
> This small series (actually only the last patch; first two are cleanups)
> wants to improve ability of QEMU downtime analysis similarly to what Joao
> used to propose here:
>
> https://lore.kernel.org/r/20230926161841.98464-1-joao.m.mart...@oracle.com
>
Postcopy calculates its downtime separately. It always sets
MigrationState.downtime properly, but not MigrationState.downtime_start.
Make postcopy do the same as other modes on properly recording the
timestamp when the VM is going to be stopped. Drop the temporary variable
in postcopy_start()
This small series (actually only the last patch; first two are cleanups)
wants to improve ability of QEMU downtime analysis similarly to what Joao
used to propose here:
https://lore.kernel.org/r/20230926161841.98464-1-joao.m.mart...@oracle.com
But with a few differences:
- Nothing exported
We have a bunch of savevm_section* tracepoints, they're good to analyze
migration stream, but not always suitable if someone would like to analyze
the migration downtime. Two major problems:
- savevm_section* tracepoints are dumping all sections, we only care
about the sections that
Unify the three users on recording downtimes with the same pair of helpers.
Signed-off-by: Peter Xu
---
migration/migration.c | 37 -
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index
On Wed, 2023-10-25 at 18:23 -0700, Stefano Stabellini wrote:
> On Thu, 26 Oct 2023, David Woodhouse wrote:
> > On Wed, 2023-10-25 at 14:24 -0700, Vikram Garhwal wrote:
> > > From: Juergen Gross
> > >
> > > Virtio devices should never be unplugged at boot time, as they are
> > > similar to pci
From: David Woodhouse
Where the local APIC is emulated by KVM, we need kvm_get_apic() to pull
the current state into userspace before it's printed. Otherwise we get
stale values.
Signed-off-by: David Woodhouse
---
target/i386/monitor.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 24/10/2023 15.12, Juan Quintela wrote:
From: Thomas Huth
There's no need for dedicated handlers here if they don't do anything
special.
Acked-by: David Hildenbrand
Reviewed-by: Eric Farman
Acked-by: Juan Quintela
Signed-off-by: Thomas Huth
Signed-off-by: Juan Quintela
Message-ID:
On Thu, 26 Oct 2023 at 16:06, Konstantin Ryabitsev
wrote:
>
> October 26, 2023 at 5:58 AM, "Cédric Le Goater" wrote:
> > > Reviwed-by: Denis V. Lunev
> > >
> >
> > I changed that to "Reviewed-by".
> >
> > Interesting to see that b4 was ok with this new tag.
>
> When we see an email address in
On 24/10/2023 15.12, Juan Quintela wrote:
From: Thomas Huth
Since the instance_init() function immediately tries to set the
property to "true", the s390_skeys_set_migration_enabled() tries
to register a savevm handler during instance_init(). However,
instance_init() functions can be called
Hello Cedric,
On 10/24/23 02:34, Cédric Le Goater wrote:
On 10/21/23 23:17, Ninad Palsule wrote:
Added basic qtests for FSI model.
Signed-off-by: Ninad Palsule
---
v3:
- Added new qtest as per Cedric's comment.
V4:
- Remove MAINTAINER and documentation changes from this commit
v6:
-
Hello Cedric,
On 10/24/23 02:37, Cédric Le Goater wrote:
On 10/21/23 23:17, Ninad Palsule wrote:
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule
---
v4:
- Added separate commit for documentation
---
docs/specs/fsi.rst | 141 +
Hello Cedric,
On 10/24/23 10:21, Cédric Le Goater wrote:
On 10/24/23 17:00, Ninad Palsule wrote:
Hello Cedric,
On 10/24/23 02:46, Cédric Le Goater wrote:
On 10/21/23 23:17, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB
Stefan Hajnoczi wrote:
> On Tue, 24 Oct 2023 at 23:45, Juan Quintela wrote:
>>
>> The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:
>>
>> Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into
>> staging (2023-10-23 14:45:46 -0700)
>>
>> are available
On 10/24/23 02:08, Philippe Mathieu-Daudé wrote:
On 23/10/23 19:08, Ninad Palsule wrote:
Hello Philippe,
On 10/23/23 10:00, Philippe Mathieu-Daudé wrote:
On 21/10/23 23:17, Ninad Palsule wrote:
This is a part of patchset where scratchpad is introduced.
The scratchpad provides a set of
Vector crypto spec defines the NIST algorithm suite related extensions
(Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 20
2 files changed, 23 insertions(+)
Because the vector crypto specification is ratified, so move theses
extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
Expose the properties of ShangMi Algorithm Suite related extensions
(Zvks, Zvksc, Zvksg).
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8eae8d3e59c..1709df76a9b 100644
---
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh
Signed-off-by: Max Chou
---
disas/riscv.c | 137 ++
1 file changed, 137
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou
---
disas/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7ea6ea050e9..e9458e574b9 100644
---
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou
---
disas/riscv.c | 14 +-
disas/riscv.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git
Expose the properties of NIST Algorithm Suite related extensions (Zvkn,
Zvknc, Zvkng).
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 992f8e0f7b0..8eae8d3e59c 100644
--- a/target/riscv/cpu.c
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions.
Signed-off-by: Max Chou
---
disas/riscv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/disas/riscv.h b/disas/riscv.h
index 8abb578b515..b242d73b25e 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -274,6 +274,7 @@ enum {
Vector crypto spec defines the ShangMi algorithm suite related
extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto
extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 17 +
2 files changed, 20 insertions(+)
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 1 +
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5099c786415..992f8e0f7b0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
The Zvkb extension is a proper subset of the Zvbb extension and includes
following instructions:
* vandn.[vv,vx]
* vbrev8.v
* vrev8.v
* vrol.[vv,vx]
* vror.[vv,vx,vi]
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++-
1 file changed, 24
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a2881bfa383..5099c786415 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
Vector crypto spec defines the Zvkt extension that included all of the
instructions of Zvbb & Zvbc extensions and some vector instructions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 5 +
2 files changed, 6 insertions(+)
diff --git
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