Re: [PATCH v13 00/11] Add VIRTIO sound card

On Mon, Oct 23, 2023 at 03:03:17PM +0300, Manos Pitsidianakis wrote: > This patch series adds an audio device implementing the recent virtio > sound spec (1.2) and a corresponding PCI wrapper device. > > v13 can be found online at: > > https://gitlab.com/epilys/qemu/-/tree/virtio-snd-v13 > >

Re: [PATCH v6 11/21] virtio-net: Return an error when vhost cannot enable RSS

On 2023/11/01 13:19, Jason Wang wrote: On Mon, Oct 30, 2023 at 9:15 PM Akihiko Odaki wrote: On 2023/10/30 21:51, Yuri Benditovich wrote: On Mon, Oct 30, 2023 at 2:21 PM Akihiko Odaki mailto:akihiko.od...@daynix.com>> wrote: On 2023/10/30 21:14, Yuri Benditovich wrote: > >

Re: [PATCH v6 11/21] virtio-net: Return an error when vhost cannot enable RSS

On Mon, Oct 30, 2023 at 9:15 PM Akihiko Odaki wrote: > > On 2023/10/30 21:51, Yuri Benditovich wrote: > > > > > > On Mon, Oct 30, 2023 at 2:21 PM Akihiko Odaki > > wrote: > > > > On 2023/10/30 21:14, Yuri Benditovich wrote: > > > > > > > > > On

[PATCH v2 11/21] target/sparc: Always copy conditions into a new temporary

This will allow the condition to live across changes to the global cc variables. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a405512e6c..dd6d43d1f1

[PATCH v2 16/21] target/sparc: Merge gen_op_next_insn into only caller

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1233911b69..0bbe4cff3b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@

[PATCH v2 17/21] target/sparc: Record entire jump condition in DisasContext

Use the original condition instead of consuming cpu_cond, which will now only be live along exception paths. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/sparc/translate.c

[PATCH v2 09/21] target/sparc: Remove DisasCompare.is_bool

Since we're going to feed cpu_cond to another comparison, we don't reqire a boolean value -- anything non-zero is sufficient. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 22 +++--- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git

[PATCH v2 15/21] target/sparc: Pass displacement to advance_jump_cond

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cbee5435a3..1233911b69 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@

[PATCH v2 04/21] target/sparc: Remove CC_OP_DIV

Return both result and overflow from helper_[us]div. Compute all flags explicitly in gen_op_[us]divcc. Marginally improve the INT64_MIN special case in do_sdiv. Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 - target/sparc/helper.h| 6 +-- target/sparc/cc_helper.c |

[PATCH v2 02/21] target/sparc: Split psr and xcc into components

Step in removing CC_OP: change the representation of CC_OP_FLAGS. The 8 bits are distributed between 6 variables, which should make it easy to keep up to date. The code within cc_helper.c is quite ugly but is only temporary. Signed-off-by: Richard Henderson --- linux-user/sparc/target_cpu.h |

[PATCH v2 06/21] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB

These are all related and implementable with common code. Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 3 - target/sparc/cc_helper.c | 103 target/sparc/translate.c | 203 +-- 3 files changed, 45 insertions(+), 264

[PATCH v2 14/21] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond

Handle these via TCG_COND_{ALWAYS,NEVER}. Allow dc->npc to be variable, using gen_mov_pc_npc. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 74 1 file changed, 30 insertions(+), 44 deletions(-) diff --git a/target/sparc/translate.c

[PATCH v2 13/21] target/sparc: Merge gen_branch2 into advance_pc

The function had only one caller. Canonicalize the cpu_cond test to TCG_COND_NE, the "natural" sense of its value. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git

[PATCH v2 19/21] target/sparc: Implement UDIVX and SDIVX inline

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 4 -- target/sparc/insns.decode | 4 +- target/sparc/helper.c | 24 - target/sparc/translate.c | 109 +- 4 files changed, 97 insertions(+), 44 deletions(-) diff --git

[PATCH v2 20/21] target/sparc: Implement UDIV inline

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +- target/sparc/translate.c | 67 +++ 2 files changed, 56 insertions(+), 14 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 52f54b87cc..2d26404cb2

[PATCH v2 18/21] target/sparc: Discard cpu_cond at the end of each insn

If the insn raises no exceptions, there will be no path in which cpu_cond is used, and so the computation may be optimized away. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 27 +++ 1 file changed, 27 insertions(+) diff --git

[PATCH v2 07/21] target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV

Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 - target/sparc/cc_helper.c | 190 +-- target/sparc/helper.c| 36 ++-- target/sparc/translate.c | 4 +- 4 files changed, 32 insertions(+), 200 deletions(-) diff --git

[PATCH v2 05/21] target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD

These are all related and implementable with common code. Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 3 - target/sparc/cc_helper.c | 92 --- target/sparc/translate.c | 247 ++- 3 files changed, 87 insertions(+), 255

[PATCH v2 12/21] target/sparc: Do flush_cond in advance_jump_cond

Do this here instead of in each caller. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dd6d43d1f1..2e7deb5e33 100644 ---

[PATCH v2 03/21] target/sparc: Remove CC_OP_LOGIC

Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 - target/sparc/cc_helper.c | 14 + target/sparc/translate.c | 66 3 files changed, 28 insertions(+), 53 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index

[PATCH v2 08/21] target/sparc: Remove CC_OP leftovers

All instructions have been converted to generate full condition codes explicitly. Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 21 --- target/sparc/helper.h | 2 - linux-user/sparc/cpu_loop.c | 5 -- target/sparc/cc_helper.c| 42 -

[PATCH v2 10/21] target/sparc: Change DisasCompare.c2 to int

We don't require c2 to be variable, so emphasize that. We don't currently require c2 to be non-zero, but that will change. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 33 ++--- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git

[PATCH v2 21/21] target/sparc: Check for invalid cond in gen_compare_reg

Consolidate the test here; drop the "inverted logic". Fix MOVr and FMOVR, which were missing the invalid test. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 45 +++- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git

[PATCH v2 01/21] target/sparc: Introduce cpu_put_psr_icc

Isolate linux-user from changes to icc representation. Signed-off-by: Richard Henderson --- target/sparc/cpu.h| 1 + linux-user/sparc/signal.c | 2 +- target/sparc/win_helper.c | 7 ++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.h

[PATCH v2 00/21] target/sparc: Cleanup condition codes etc

This was part of my guess for some of the performance problems. I saw compute_all_sub quite high in the profile at some point, and I believe that the test case has a partially rotated loop such that "cmp" is in a delay slot, and so the gen_compare fast path for CC_OP_SUB is not visible to the

Re: [PATCH v2 6/6] linux-user/loongarch64: Add LASX sigcontext save/restore

On 10/31/23 20:08, Song Gao wrote: Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 68 ++--- 1 file changed, 62 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 5/6] linux-user/loongarch64: Add LSX sigcontext save/restore

On 10/31/23 20:08, Song Gao wrote: Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 107 ++-- 1 file changed, 87 insertions(+), 20 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 4/6] linux-user/loongarch64: Use abi_{ulong, uint} types

On 10/31/23 20:08, Song Gao wrote: Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) Reviewed-by: Richard Henderson r~

[PATCH v2 6/6] linux-user/loongarch64: Add LASX sigcontext save/restore

Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 68 ++--- 1 file changed, 62 insertions(+), 6 deletions(-) diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c index 9c9b446a91..39ea82c814 100644 ---

[PATCH v2 3/6] linux-user/loongarch64: setup_sigframe() set 'end' context size 0

See: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c The kernel setup_sigcontext() set end context size 0. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- linux-user/loongarch64/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v2 0/6] linux-user/loongarch64: Add LSX/LASX sigcontext

Hi, This series adds save/restore LSX/LASX sigcontext. test: - use V1 test. - test with RISU https://patchew.org/QEMU/20231025092915.902814-1-gaos...@loongson.cn/ V2: - Rebase; - Remove extctx_flags; - Use abi_{ulong, uint} types; - R-b. Richard Henderson (1):

[PATCH v2 5/6] linux-user/loongarch64: Add LSX sigcontext save/restore

Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 107 ++-- 1 file changed, 87 insertions(+), 20 deletions(-) diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c index 9336f40ffe..9c9b446a91 100644 ---

[PATCH v2 1/6] linux-user/loongarch64: Use traps to track LSX/LASX usage

From: Richard Henderson Signed-off-by: Richard Henderson --- linux-user/loongarch64/cpu_loop.c | 13 + target/loongarch/insn_trans/trans_vec.c.inc | 11 --- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/linux-user/loongarch64/cpu_loop.c

[PATCH v2 4/6] linux-user/loongarch64: Use abi_{ulong,uint} types

Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c index cc8324b4b3..9336f40ffe 100644 --- a/linux-user/loongarch64/signal.c

[PATCH v2 2/6] linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context size

See: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c The alloc size is sizeof(struct target_fpu_context). Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- linux-user/loongarch64/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH v3 1/3] qapi: Moved architecture agnostic data types to `machine`

Hi, I noticed that qapi now has a machine-common category - do you think these changes would be more appropriate in that file rather than "machine" for the revision? Thanks and sorry for the delay, -Dinah On Tue, Aug 1, 2023 at 9:09 AM Markus Armbruster wrote: > Dinah Baum writes: > > >

Re: [PATCH] target/i386/kvm: call kvm_put_vcpu_events() before kvm_put_nested_state()

FYI: The EINVAL in vmx_set_nested_state() is caused by the following condition: * vcpu->arch.hflags == 0 * kvm_state->hdr.vmx.smm.flags == KVM_STATE_NESTED_SMM_VMXON Please feel free to ask me any more data points you need. Thanks, Eiichi > On Oct 26, 2023, at 17:52, Vitaly Kuznetsov wrote: >

Re: [PATCH v1 2/6] target/loongarch: Add set_vec_extctx to set LSX/LASX instructions extctx_flags

在 2023/10/31 下午10:50, Richard Henderson 写道: On 10/30/23 23:16, gaosong wrote: Anyway, I think my previous suggestion is better: Oh,  Could you  show more details?  I think I didn't get you point. If you want to track what the program is using, you should do it exactly like the real kernel:

Re: [PATCH v3] tests/avocado: add test to exercize processor address space memory bound checks

> On 27-Oct-2023, at 4:12 PM, Ani Sinha wrote: > > QEMU has validations to make sure that a VM is not started with more memory > (static and hotpluggable memory) than what the guest processor can address > directly with its addressing bits. This change adds a test to make sure QEMU > fails to

Re: [PATCH] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot

On Wed, Nov 1, 2023 at 6:53 AM Daniel Henrique Barboza wrote: > > These regs were added in Linux 6.6. > > Signed-off-by: Daniel Henrique Barboza Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/kvm/kvm-cpu.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git

Re: [PATCH] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot

On Wed, Nov 1, 2023 at 6:53 AM Daniel Henrique Barboza wrote: > > These regs were added in Linux 6.6. > > Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm-cpu.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git

Re: [PULL 00/19] Updates for testing, gitlab, gdbstub, plugins and semihosting

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/38] Migration 20231031 patches

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/27] Block layer patches

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v2 21/29] migration/multifd: Add pages to the receiving side

Peter Xu writes: > On Mon, Oct 23, 2023 at 05:36:00PM -0300, Fabiano Rosas wrote: >> Currently multifd does not need to have knowledge of pages on the >> receiving side because all the information needed is within the >> packets that come in the stream. >> >> We're about to add support to

Re: [PATCH 3/4] target/s390x: Fix LAALG not updating cc_src

On 10/30/23 22:32, Ilya Leoshkevich wrote: LAALG uses op_laa() and cout_addu64(). The latter expects cc_src to be set, but the former does not do it. This can lead to assertion failures if something sets cc_src to neither 0 nor 1 before. Fix by setting cc_src in op_laa(). Fixes: 4dba4d6fef61

Re: [PATCH 2/4] tests/tcg/s390x: Test CLC with inaccessible second operand

On 10/30/23 22:32, Ilya Leoshkevich wrote: +int main(void) +{ +register unsigned long r0 asm("r0"); +unsigned long mem = 42, rhs = 500; +struct sigaction act; +int err; + +memset(, 0, sizeof(act)); +act.sa_sigaction = handle_sigsegv; +act.sa_flags = SA_SIGINFO; +

Re: [PATCH v13 00/11] Add VIRTIO sound card

Manos Pitsidianakis writes: > This patch series adds an audio device implementing the recent virtio > sound spec (1.2) and a corresponding PCI wrapper device. > > v13 can be found online at: > > https://gitlab.com/epilys/qemu/-/tree/virtio-snd-v13 > > Ref e7fb941cf7636fdff40cbdcdcd660dec5f15ca3c

Re: [PATCH 1/4] target/s390x: Fix CLC corrupting cc_src

On 10/30/23 22:32, Ilya Leoshkevich wrote: CLC updates cc_src before accessing the second operand; if the latter is inaccessible, the former ends up containing a bogus value. Fix by reading cc_src into a temporary first. Fixes: 4f7403d52b1c ("target-s390: Convert CLC") Closes:

Re: [PATCH v15 13/14] migration: Implement MigrateChannelList to hmp migration flow.

Het Gala wrote: > On 01/11/23 12:25 am, Juan Quintela wrote: >> I intrehated al parches until this forma next pull. > I should just add the last 2 patches as individual ones, is that what > you mean ? Take a look at: https://gitlab.com/juan.quintela/qemu/-/commits/migration-next This is my

Re: [PATCH v6 5/5] default-configs: Add TARGET_XML_FILES definition

Philippe Mathieu-Daudé writes: > On 30/10/23 06:46, Akihiko Odaki wrote: >> loongarch64-linux-user has references to XML files so include them. >> Fixes: d32688ecdb ("default-configs: Add loongarch linux-user >> support") >> Signed-off-by: Akihiko Odaki >> --- >>

Re: [PATCH v4 3/5] tests/migration-test: Add a test for postcopy hangs during RECOVER

Fabiano Rosas wrote: > Peter Xu writes: > >> From: Fabiano Rosas >> >> To do so, create two paired sockets, but make them not providing real data. >> Feed those fake sockets to src/dst QEMUs for recovery to let them go into >> RECOVER stage without going out. Test that we can always kick it

Re: [PATCH] target/i386: Only allow injecting MCE on x86 CPUs

On 10/30/23 03:21, Philippe Mathieu-Daudé wrote: When using heterogeneous machines, we can try to inject a MCE on a non-x86 CPU. Filter the CPU is injectable, otherwise display a hint. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/monitor.c | 15 ++- 1 file changed, 10

Re: [PATCH 0/4] Fix IRQ routing in via south bridge

On Tue, 31 Oct 2023, BALATON Zoltan wrote: On Tue, 31 Oct 2023, Mark Cave-Ayland wrote: On 30/10/2023 21:57, BALATON Zoltan wrote: On Mon, 30 Oct 2023, Mark Cave-Ayland wrote: On 29/10/2023 13:45, BALATON Zoltan wrote: On Sun, 29 Oct 2023, Mark Cave-Ayland wrote: On 29/10/2023 00:56,

Re: [PATCH v3 1/1] hmp: synchronize cpu state for lapic info

Hi Juan, On 10/30/23 09:31, Juan Quintela wrote: > Dongli Zhang wrote: >> While the default "info lapic" always synchronizes cpu state ... >> >> mon_get_cpu() >> -> mon_get_cpu_sync(mon, true) >>-> cpu_synchronize_state(cpu) >> -> ioctl KVM_GET_LAPIC (taking KVM as example) >> >> ...

Re: [PATCH 0/4] tcg: Canonicalize SUBI to ANDI

Ping. On 10/25/23 18:39, Richard Henderson wrote: Supercedes: 20231025185956.72677-1-pbonz...@redhat.com ("tcg: allow a target to request canonicalization of SUBI to ADDI") Based-on: 20231025072707.833943-1-richard.hender...@linaro.org ("tcg: Introduce TCG_COND_TST{EQ,NE}") There a couple of

Re: [PATCH v4 3/5] tests/migration-test: Add a test for postcopy hangs during RECOVER

On Tue, Oct 31, 2023 at 07:01:02PM -0300, Fabiano Rosas wrote: > This patch breaks the windows build. We need this: Oops.. I hope this can still catch Juan's next pull, or I'll squash the fix if to repost. Thanks, -- Peter Xu

Re: [PATCH v2 21/29] migration/multifd: Add pages to the receiving side

On Mon, Oct 23, 2023 at 05:36:00PM -0300, Fabiano Rosas wrote: > Currently multifd does not need to have knowledge of pages on the > receiving side because all the information needed is within the > packets that come in the stream. > > We're about to add support to fixed-ram migration, which

Re: [PATCH 5/6] hw/i2c/pm_smbus: Convert DPRINTF to trace events

On Sat, Oct 28, 2023 at 02:24:14PM +0200, Bernhard Beschow wrote: > Let the trace messages slightly deviate from the function names > ("smb" -> "smbus") being traced in order to avoid conflights with the SMB > protocol. > > Signed-off-by: Bernhard Beschow Looks good to me. Acked-by: Corey

Re: [PATCH v4 3/5] tests/migration-test: Add a test for postcopy hangs during RECOVER

Peter Xu writes: > From: Fabiano Rosas > > To do so, create two paired sockets, but make them not providing real data. > Feed those fake sockets to src/dst QEMUs for recovery to let them go into > RECOVER stage without going out. Test that we can always kick it out and > recover again with the

Re: [RFC PATCH 0/5] hw/ppc/e500: Pass array of CPUs as array of canonical QOM paths

On 10/30/23 11:39, Philippe Mathieu-Daudé wrote: Following the discussion with Peter on my "cpus: Step toward removing global 'first_cpu'" series [*], we now pass the array of CPUs via property. Since we can not pass array of "link" properties, we pass the QOM path of each CPU as a

Re: [PATCH v2 20/29] migration/multifd: Add incoming QIOChannelFile support

On Mon, Oct 23, 2023 at 05:35:59PM -0300, Fabiano Rosas wrote: > On the receiving side we don't need to differentiate between main > channel and threads, so whichever channel is defined first gets to be > the main one. And since there are no packets, use the atomic channel > count to index into

Re: [RFC PATCH 5/5] hw/ppc/e500: Pass array of CPUs as array of canonical QOM paths

On 10/30/23 11:39, Philippe Mathieu-Daudé wrote: Devices should avoid calling qemu_get_cpu() because this call doesn't work as expected with heterogeneous machines. Such devices often iterate over a cluster of CPUs, which the device's parent has direct access (when creating the child device).

Re: [PATCH 4/5] hw/ppc/e500: Inline sysbus_create_simple(E500_SPIN)

On 10/30/23 11:39, Philippe Mathieu-Daudé wrote: In the next commit we'll set properties to the TYPE_E500_SPIN object. In order to ease next commit review, inline the sysbus_create_simple() call first. Signed-off-by: Philippe Mathieu-Daudé --- Reviewed-by: Daniel Henrique Barboza

Re: [PATCH 3/5] hw/ppc/e500: QOM-attach CPUs to the machine container

On 10/30/23 11:39, Philippe Mathieu-Daudé wrote: Instead of having CPUs dangling in the /unattached/device bucket, attach them to the machine container. Signed-off-by: Philippe Mathieu-Daudé --- Reviewed-by: Daniel Henrique Barboza hw/ppc/e500.c | 1 + 1 file changed, 1 insertion(+)

Re: [PATCH 2/5] hw/ppc/e500: Declare CPU QOM types using DEFINE_TYPES() macro

On 10/30/23 11:39, Philippe Mathieu-Daudé wrote: When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Signed-off-by: Philippe Mathieu-Daudé ---

Re: [PATCH 0/4] Fix IRQ routing in via south bridge

On Tue, 31 Oct 2023, Mark Cave-Ayland wrote: On 30/10/2023 21:57, BALATON Zoltan wrote: On Mon, 30 Oct 2023, Mark Cave-Ayland wrote: On 29/10/2023 13:45, BALATON Zoltan wrote: On Sun, 29 Oct 2023, Mark Cave-Ayland wrote: On 29/10/2023 00:56, BALATON Zoltan wrote: This is going back to my

[PATCH] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot

These regs were added in Linux 6.6. Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index a11c0e4a99..78fa1fa162 100644 --- a/target/riscv/kvm/kvm-cpu.c +++

[PATCH v7 10/16] target/riscv/tcg: add MISA user options hash

We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice

[PATCH v7 12/16] target/riscv/tcg: handle profile MISA bits

The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting

[PATCH v7 16/16] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion

Expose all profile flags for all CPUs when executing query-cpu-model-expansion. This will allow callers to quickly determine if a certain profile is implemented by a given CPU. This includes vendor CPUs - the fact that they don't have profile user flags doesn't mean that they don't implement the

[PATCH v7 02/16] target/riscv/tcg: do not use "!generic" CPU checks

Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In

[PATCH v7 15/16] target/riscv/tcg: validate profiles during finalize

Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are

[PATCH v7 07/16] target/riscv: add rva22u64 profile definition

The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of

[PATCH v7 13/16] target/riscv/tcg: add hash table insert helpers

Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 28 1 file changed, 16 insertions(+),

[PATCH v7 09/16] target/riscv/tcg: add user flag for profile support

The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG

[PATCH v7 06/16] riscv-qmp-cmds.c: expose named features in cpu_model_expansion

Named features (zic64b the sole example at this moment) aren't expose to users, thus we need another way to expose them. Go through each named feature, get its boolean value, do the needed conversions (bool to qbool, qbool to QObject) and add it to output dict. Another adjustment is needed:

[PATCH v7 11/16] target/riscv/tcg: add riscv_cpu_write_misa_bit()

We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei

[PATCH v7 00/16] rv64i CPU, RVA22U64 profile support

Hi, As discussed in v6, all our problems with the profile implementation cames from the rv64 CPU and how to deal with its defaults. Enabling a profile on top of it is straightforward, but disabling it (either via a script trying to undo a profile enablement, or users doing something silly) makes

[PATCH v7 05/16] target/riscv/tcg: add 'zic64b' support

zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications using this profile expects 64

[PATCH v7 14/16] target/riscv/tcg: honor user choice for G MISA bits

RVG behaves like a profile: a single flag enables a set of bits. Right now we're considering user choice when handling RVG and zicsr/zifencei and ignoring user choice on MISA bits. We'll add user warnings for profiles when the user disables its mandatory extensions in the next patch. We'll do the

[PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU

We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the

[PATCH v7 08/16] target/riscv/kvm: add 'rva22u64' flag as unavailable

KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support in the end. We'll revisit this

[PATCH v7 04/16] target/riscv: add zicbop extension flag

QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which

[PATCH v7 03/16] target/riscv: add rv64i CPU

We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to deal with if not by profile

Re: intermittent qtest-aarch64/xlnx-canfd-test test failure

Hi Michael & Cedric, On Mon, Oct 30, 2023 at 05:19:38PM +0100, Cédric Le Goater wrote: > On 9/21/23 09:51, Michael Tokarev wrote: > > Hi! > > > > While doing stable-8.1.1 preparation, I've a CI failure of > > ubuntu-20.04-s390x-all here: > > > >

Re: [PATCH v2 19/29] migration/multifd: Add outgoing QIOChannelFile support

On Mon, Oct 23, 2023 at 05:35:58PM -0300, Fabiano Rosas wrote: > Allow multifd to open file-backed channels. This will be used when > enabling the fixed-ram migration stream format which expects a > seekable transport. > > The QIOChannel read and write methods will use the preadv/pwritev >

Re: [PATCH] Missing CASA instruction handling for SPARC qemu-user

On 7/18/23 09:09, Luca Bonissi wrote: On qemu-sparc (user-space), the CASA instruction is not handled for SPARC32 even if the selected cpu (e.g. LEON3) supports it. This should be fixed now, with commit d0a11d25f0332dbaeb3a4f733a5cfb23ed40413d Author: Richard Henderson Date: Thu Oct 5

Re: [PATCH v2 16/29] migration/ram: Add support for 'fixed-ram' migration restore

Peter Xu writes: > On Mon, Oct 23, 2023 at 05:35:55PM -0300, Fabiano Rosas wrote: >> From: Nikolay Borisov >> >> Add the necessary code to parse the format changes for the 'fixed-ram' >> capability. >> >> One of the more notable changes in behavior is that in the 'fixed-ram' >> case ram pages

Re: [PATCH 0/4] Fix IRQ routing in via south bridge

On 30/10/2023 21:57, BALATON Zoltan wrote: On Mon, 30 Oct 2023, Mark Cave-Ayland wrote: On 29/10/2023 13:45, BALATON Zoltan wrote: On Sun, 29 Oct 2023, Mark Cave-Ayland wrote: On 29/10/2023 00:56, BALATON Zoltan wrote: This is going back to my otiginal proposal in

Re: [PATCH v2 16/29] migration/ram: Add support for 'fixed-ram' migration restore

On Mon, Oct 23, 2023 at 05:35:55PM -0300, Fabiano Rosas wrote: > From: Nikolay Borisov > > Add the necessary code to parse the format changes for the 'fixed-ram' > capability. > > One of the more notable changes in behavior is that in the 'fixed-ram' > case ram pages are restored in one go

Re: [PATCH v15 13/14] migration: Implement MigrateChannelList to hmp migration flow.

On 01/11/23 12:25 am, Juan Quintela wrote: I intrehated al parches until this forma next pull. I should just add the last 2 patches as individual ones, is that what you mean ? On Tue, Oct 31, 2023, 19:51 Het Gala wrote: On 31/10/23 11:12 pm, Juan Quintela wrote: > Fabiano Rosas

[PULL 12/27] block: avoid potential deadlock during bdrv_graph_wrlock() in bdrv_close()

From: Fiona Ebner by passing the BlockDriverState along, so the held AioContext can be dropped before polling. See commit 31b2ddfea3 ("graph-lock: Unlock the AioContext while polling") which introduced this functionality for more information. The only way to reach bdrv_close() is via

Re: [PATCH v2 28/29] migration: Add direct-io parameter

Daniel P. Berrangé writes: > On Tue, Oct 31, 2023 at 12:52:41PM -0300, Fabiano Rosas wrote: >> Daniel P. Berrangé writes: >> > >> > I guess I'm not seeing the problem still. A single FD is passed across >> > from libvirt, but QEMU is free to turn that into *many* FDs for its >> > internal use,

[PULL 14/27] block: rename blk_io_plug_call() API to defer_call()

From: Stefan Hajnoczi Prepare to move the blk_io_plug_call() API out of the block layer so that other subsystems call use this deferred call mechanism. Rename it to defer_call() but leave the code in block/plug.c. The next commit will move the code out of the block layer. Suggested-by: Ilya

[PULL 22/27] mirror: implement mirror_change method

From: Fiona Ebner which allows switching the @copy-mode from 'background' to 'write-blocking'. This is useful for management applications, so they can start out in background mode to avoid limiting guest write speed and switch to active mode when certain criteria are fulfilled. In presence of

Re: [PATCH v2 16/29] migration/ram: Add support for 'fixed-ram' migration restore

On Wed, Oct 25, 2023 at 11:07:33AM -0300, Fabiano Rosas wrote: > >> +static int parse_ramblock_fixed_ram(QEMUFile *f, RAMBlock *block, > >> ram_addr_t length) > >> +{ > >> +g_autofree unsigned long *bitmap = NULL; > >> +struct FixedRamHeader header; > >> +size_t bitmap_size; > >> +

[PULL 17/27] virtio-blk: remove batch notification BH

From: Stefan Hajnoczi There is a batching mechanism for virtio-blk Used Buffer Notifications that is no longer needed because the previous commit added batching to virtio_notify_irqfd(). Note that this mechanism was rarely used in practice because it is only enabled when EVENT_IDX is not

[PULL 25/27] blockjob: query driver-specific info via a new 'query' driver method

From: Fiona Ebner Signed-off-by: Fiona Ebner Message-ID: <20231031135431.393137-9-f.eb...@proxmox.com> Reviewed-by: Kevin Wolf Signed-off-by: Kevin Wolf --- include/block/blockjob_int.h | 5 + blockjob.c | 6 ++ 2 files changed, 11 insertions(+) diff --git

[PULL 23/27] qapi/block-core: use JobType for BlockJobInfo's type

From: Fiona Ebner In preparation to turn BlockJobInfo into a union with @type as the discriminator. That requires it to be an enum. Even without that requirement, it's nicer to have an enum instead of a str here. No functional change is intended. Signed-off-by: Fiona Ebner Reviewed-by:

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