On 2023/12/12 19:04, Philippe Mathieu-Daudé wrote:
On 10/12/23 05:05, Akihiko Odaki wrote:
It is no longer used.
Since commit f3558b1b76 ("qdev: Base object creation on QDict rather
than QemuOpts")?
One usage still remains and it will be removed with an earlier patch,
"[PATCH RFC v2 04/12]
On 12/12/23 01:34, Ilya Leoshkevich wrote:
Stop using TARGET_PAGE_MASK in order to make perf.c more
target-agnostic.
Signed-off-by: Ilya Leoshkevich
---
accel/tcg/perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
[Changes since v1]
used satp_mode.map instead of satp_mode.supported
[Original cover]
The SATP register is an SXLEN-bit read/write WARL register. It means that CSR
fields are only defined
for a subset of bit encodings, but allow any value to be written while
guaranteeing to return a legal
value
Added xATP_MODE validation for vsatp/hgatp CSRs.
The xATP register is an SXLEN-bit read/write WARL register, so
the legal value must be returned (See riscv-privileged-20211203,
SATP/VSATP/HGATP CSRs).
Signed-off-by: Irina Ryapolova
---
target/riscv/csr.c | 52
On 12/12/23 11:15, Philippe Mathieu-Daudé wrote:
On 12/12/23 00:29, Richard Henderson wrote:
On 12/11/23 13:19, Philippe Mathieu-Daudé wrote:
First, "exec/user/abitypes.h" is missing the following
includes (they are included by "cpu.h"):
- "exec/target_long.h"
- "exec/cpu-all.h"
-
On Tue, 12 Dec 2023 at 01:43, Tomoyuki Hirose
wrote:
>
> Thanks for comment.
>
> On Mon, Dec 11, 2023 at 10:57 PM Peter Maydell
> wrote:
> > We should definitely look at fixing the unaligned access
> > stuff, but the linked bug report is not trying to do an
> > unaligned access -- it wants to
GUEST_VIRTIO_MMIO_* was added in Xen 4.17, so only define them
for CONFIG_XEN_CTRL_INTERFACE_VERSIONs up to 4.16.
Reported-by: Daniel P. Berrangé
Signed-off-by: Paolo Bonzini
---
include/hw/xen/xen_native.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The following changes since commit abf635ddfe3242df907f58967f3c1e6763bbca2d:
Update version for v8.2.0-rc2 release (2023-11-28 16:31:16 -0500)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to
A misspelled condition in xen_native.h is hiding a bug in the enablement of
Xen for qemu-system-aarch64. The bug becomes apparent when building for
Xen 4.18.
While the i386 emulator provides the xenpv machine type for multiple
architectures,
and therefore can be compiled with Xen enabled even
On 12/12/23 00:29, Richard Henderson wrote:
On 12/11/23 13:19, Philippe Mathieu-Daudé wrote:
First, "exec/user/abitypes.h" is missing the following
includes (they are included by "cpu.h"):
- "exec/target_long.h"
- "exec/cpu-all.h"
- "exec/tswap.h"
Second, it only requires the definitions
On 12/12/23 02:18, Richard Henderson wrote:
On 12/11/23 13:19, Philippe Mathieu-Daudé wrote:
The abi_ptr type is declared in "exec/cpu_ldst.h" with all
the load/store helpers. Some source files requiring abi_ptr
type don't need the load/store helpers. In order to simplify,
create a new
On 10/12/23 05:05, Akihiko Odaki wrote:
It is no longer used.
Since commit f3558b1b76 ("qdev: Base object creation on QDict rather
than QemuOpts")?
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Akihiko Odaki
---
include/hw/qdev-core.h | 4
hw/core/qdev.c | 1 -
On 10/12/23 05:05, Akihiko Odaki wrote:
The device realization code may enable PCI multifunction for SR-IOV.
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Am 11.12.2023 um 16:32 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 18.09.2023 um 18:16 hat Stefan Hajnoczi geschrieben:
> >> virtio-blk and virtio-scsi devices will need a way to specify the
> >> mapping between IOThreads and virtqueues. At the moment all virtqueues
> >> are
On 12/8/23 16:19, Chalapathi V wrote:
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 12/8/23 16:19, Chalapathi V wrote:
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
On 12/8/23 16:19, Chalapathi V wrote:
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with
On 2023/12/12 13:12, Jason Wang wrote:
On Mon, Dec 11, 2023 at 4:29 PM Akihiko Odaki wrote:
On 2023/12/11 16:26, Jason Wang wrote:
On Mon, Dec 11, 2023 at 1:30 PM Akihiko Odaki wrote:
On 2023/12/11 11:52, Jason Wang wrote:
On Sun, Dec 10, 2023 at 12:06 PM Akihiko Odaki wrote:
On Mon, Dec 11, 2023 at 08:31:17AM -0500, Steven Sistare wrote:
> On 12/11/2023 1:56 AM, Peter Xu wrote:
> > On Wed, Dec 06, 2023 at 12:30:02PM -0500, Steven Sistare wrote:
> >> cpus: stop vm in suspended runstate
> >
> > This patch still didn't copy the QAPI maintainers, please remember to
On 2023/12/12 17:04, Marek Glogowski wrote:
Hi
I checked on the emulation "qemu-system-ppc -machine pegasos".
Full-screen seems to work fine. The screen is correctly initialised in
full-screen mode and there are no problems with closing the window when
the session is suspended.
With this
On 2023/12/12 2:01, Alex Bennée wrote:
Cleber Rosa writes:
Based on many runs, the average run time for these 4 tests is around
250 seconds, with 320 seconds being the ceiling. In any way, the
default 120 seconds timeout is inappropriate in my experience.
I would rather see these tests
On 2023/12/12 1:36, Philippe Mathieu-Daudé wrote:
On 8/12/23 20:09, Cleber Rosa wrote:
The asset used in the mentioned test gets truncated before it's used
in the test. This means that the file gets modified, and thus the
asset's expected hash doesn't match anymore. This causes cache misses
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