[PATCH v2 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 15 +-- target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c607a94bba

[PATCH v2 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 6 -- target/riscv/pmp.c | 13 ++--- target/riscv

[PATCH v2 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 54 +++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd379ee653..c607a94bba 100644 --- a/targ

[PATCH v2 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e6571ce99..13389ddc55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const RISCVIsaExt

[PATCH v2 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/riscv/cpu.c

[PATCH v2 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 23 +-- target/riscv/vector_helper.c | 10 ++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1eb501e0d3..c0c

[PATCH v2 0/6] Pointer Masking update for Zjpm v0.8

Hi, As per Richard's suggestion I made pmm field part of tb_flags. It allowed to get rid of global variable to store pmlen. Also it allowed to simplify all the machinery around it. Thanks [v1]: Hi all, It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore.

Re: [PATCH v2 12/12] hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions

On Tue, 19 Dec 2023, Bernhard Beschow wrote: Am 19. Dezember 2023 00:26:15 UTC schrieb BALATON Zoltan : On Mon, 18 Dec 2023, Bernhard Beschow wrote: The VIA south bridges are able to relocate and toggle (enable or disable) their SuperI/O functions. So far this is hardcoded such that all functio

Re: [PATCH v2 12/12] hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions

On Tue, 19 Dec 2023, Bernhard Beschow wrote: Am 19. Dezember 2023 00:26:15 UTC schrieb BALATON Zoltan : On Mon, 18 Dec 2023, Bernhard Beschow wrote: The VIA south bridges are able to relocate and toggle (enable or disable) their SuperI/O functions. So far this is hardcoded such that all functio

Re: [PATCH v5] accel/kvm: Turn DPRINTF macro use into tracepoints

02.12.2023 07:48, Jai Arora : Patch removes DPRINTF macro and adds multiple tracepoints to capture different kvm events. We also drop the DPRINTFs that don't add any additional information than trace_kvm_run_exit already does. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1827 .. Ap

Re: [PATCH] docs: fix typo

15.12.2023 01:53, Samuel Tardieu wrote: Signed-off-by: Samuel Tardieu --- docs/tools/qemu-img.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Applied to the trivial-patches tree, with a more specific subject line: docs/tools/qemu-img.rst: fix typo (sumarizes) Thanks, /mjt

Re: [PATCH 0/2] qemu-options: Improve -display cocoa documentation

14.12.2023 09:31, Akihiko Odaki : For the context, see: https://lore.kernel.org/all/e3839467-6d4c-e8e6-9247-a71fafe55...@eik.bme.hu/ Signed-off-by: Akihiko Odaki --- Akihiko Odaki (2): qemu-options: Unify the help entries for cocoa qemu-options: Tell more for -display cocoa qem

Re: [PATCH] target/riscv/kvm: do not use non-portable strerrorname_np()

18.12.2023 19:22, Natanael Copa: strerrorname_np is non-portable and breaks building with musl libc. Use strerror(errno) instead, like we do other places. Applied to the trivial-patches tree, finally.. /mjt

Re: Questions regarding the still unpublished qemu series https://github.com/yiliu1765/qemu/tree/zhenzhong/wip/iommufd_nesting_rfcv1

On Thu, Dec 21, 2023 at 03:33:47AM +, Duan, Zhenzhong wrote: > Hi Joel, > > >-Original Message- > >From: Joel Granados > >Subject: Questions regarding the still unpublished qemu series > >https://github.com/yiliu1765/qemu/tree/zhenzhong/wip/iommufd_nesting > >_rfcv1 > > > >Hello Every

Re: [PATCH 3/5] target/i386: Fix physical address truncation

Il sab 23 dic 2023, 11:34 Michael Brown ha scritto: > I am confused by how BOUND can result in an access to a linear address > outside of the address-size range. I don't know the internals well > enough, but I'm guessing it might be in the line in helper_boundl(): > > high = cpu_ldl_data_ra

Re: [PATCH 3/5] target/i386: Fix physical address truncation

On 22/12/2023 17:59, Paolo Bonzini wrote: The address translation logic in get_physical_address() will currently truncate physical addresses to 32 bits unless long mode is enabled. This is incorrect when using physical address extensions (PAE) outside of long mode, with the result that a 32-bit o