Hi, Thomas,
On Tue, Jan 09, 2024 at 08:21:53AM +0100, Thomas Huth wrote:
> Sorry for that :-(
Not at all! I actually appreciate more people looking after it.
> Maybe it's better if we remove the migration-test from
> the qtest section in MAINTAINERS? Since the migration test is very well
>
Hello Ninad,
+static void fsi_aspeed_apb2opb_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedAPB2OPBState *s = ASPEED_APB2OPB(dev);
+ int i;
+
+ sysbus_init_irq(sbd, >irq);
+
+ memory_region_init_io(>iomem, OBJECT(s), _apb2opb_ops, s,
On 09/01/2024 03.12, Peter Xu wrote:
On Mon, Jan 08, 2024 at 11:26:04AM -0300, Fabiano Rosas wrote:
Peter Xu writes:
On Wed, Jun 07, 2023 at 10:27:15AM +0200, Juan Quintela wrote:
Fabiano Rosas wrote:
We've found the source of flakiness in this test, so re-enable it.
Signed-off-by:
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Move it one layer down, so taking Virtio-migration as a feature for
migration.
Cc: Michael S. Tsirkin
Cc: Jason Wang
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/devel/migration/features.rst |
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Move it one layer down, so taking VFIO-migration as a feature for
migration.
Cc: Alex Williamson
Cc: Cédric Le Goater
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/devel/migration/features.rst |
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Reorganize the page, moving things around, and add a few
headlines ("Postcopy internals", "Postcopy features") to cover sub-areas.
Signed-off-by: Peter Xu
---
docs/devel/migration/postcopy.rst | 159 --
1
On Fri, Jan 05, 2024 at 03:04:48PM -0300, Fabiano Rosas wrote:
> The migration tests have support for being passed two QEMU binaries to
> test migration compatibility.
>
> Add a CI job that builds the lastest release of QEMU and another job
> that uses that version plus an already present build
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Split that into a separate file, put under "features".
Cc: Yong Huang
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/devel/migration/dirty-limit.rst | 71
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Split postcopy into a separate file. Introduce a head page "features.rst"
to keep all the features on top of migration framework.
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Move the two sections into a separate file called "best-practises.rst".
Add the entry into index.
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/devel/migration/best-practises.rst | 48
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Split the section from main.rst into a separate file. Reference it in the
index.rst.
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Convert the plain old .txt into .rst, add it into migration/index.rst.
Signed-off-by: Peter Xu
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/devel/migration/index.rst | 1 +
docs/devel/migration/virtio.rst | 115
Ankit Agrawal writes:
>>> +##
>>> +# @AcpiGenericInitiatorProperties:
>>> +#
>>> +# Properties for acpi-generic-initiator objects.
>>> +#
>>> +# @pci-dev: PCI device ID to be associated with the node
>>> +#
>>> +# @host-nodes: numa node list associated with the PCI device.
>>
>> NUMA
>>
>>
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Create an index page for migration module. Move VFIO migration there too.
A trivial touch-up on the title to use lower case there.
Since then we'll have "migration" as the top title, make the main doc file
renamed to "migration
On 1/9/24 07:46, pet...@redhat.com wrote:
From: Peter Xu
Migration documentation is growing into a single file too large. Create a
sub-directory for it for a split.
We also already have separate vfio/virtio documentations, move it all over
into the directory.
Note that the virtio one is
From: Peter Xu
Move it one layer down, so taking Virtio-migration as a feature for
migration.
Cc: Michael S. Tsirkin
Cc: Jason Wang
Signed-off-by: Peter Xu
---
docs/devel/migration/features.rst | 1 +
docs/devel/migration/index.rst| 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
From: Peter Xu
Split postcopy into a separate file. Introduce a head page "features.rst"
to keep all the features on top of migration framework.
Signed-off-by: Peter Xu
---
docs/devel/migration/features.rst | 9 +
docs/devel/migration/index.rst| 1 +
docs/devel/migration/main.rst
From: Peter Xu
Create an index page for migration module. Move VFIO migration there too.
A trivial touch-up on the title to use lower case there.
Since then we'll have "migration" as the top title, make the main doc file
renamed to "migration framework".
Cc: Alex Williamson
Cc: Cédric Le
From: Peter Xu
Move it one layer down, so taking VFIO-migration as a feature for
migration.
Cc: Alex Williamson
Cc: Cédric Le Goater
Signed-off-by: Peter Xu
---
docs/devel/migration/features.rst | 1 +
docs/devel/migration/index.rst| 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
From: Peter Xu
Reorganize the page, moving things around, and add a few
headlines ("Postcopy internals", "Postcopy features") to cover sub-areas.
Signed-off-by: Peter Xu
---
docs/devel/migration/postcopy.rst | 159 --
1 file changed, 84 insertions(+), 75
From: Peter Xu
Split that into a separate file, put under "features".
Cc: Yong Huang
Signed-off-by: Peter Xu
---
docs/devel/migration/dirty-limit.rst | 71
docs/devel/migration/features.rst| 1 +
docs/devel/migration/main.rst| 71
From: Peter Xu
Convert the plain old .txt into .rst, add it into migration/index.rst.
Signed-off-by: Peter Xu
---
docs/devel/migration/index.rst | 1 +
docs/devel/migration/virtio.rst | 115
docs/devel/migration/virtio.txt | 108
From: Peter Xu
Move the two sections into a separate file called "best-practises.rst".
Add the entry into index.
Signed-off-by: Peter Xu
---
docs/devel/migration/best-practises.rst | 48 +
docs/devel/migration/index.rst | 1 +
docs/devel/migration/main.rst
From: Peter Xu
Migration documentation is growing into a single file too large. Create a
sub-directory for it for a split.
We also already have separate vfio/virtio documentations, move it all over
into the directory.
Note that the virtio one is still not yet converted to rST. That is a job
From: Peter Xu
Migration docs grow larger and larger. There are plenty of things we can
do here in the future, but to start that we'd better reorganize the current
bloated doc files first and properly organize them into separate files.
This series kicks that off.
This series mostly does the
From: Peter Xu
Split the section from main.rst into a separate file. Reference it in the
index.rst.
Signed-off-by: Peter Xu
---
docs/devel/migration/compatibility.rst | 517
docs/devel/migration/index.rst | 1 +
docs/devel/migration/main.rst | 519
On 12/21/2023 9:47 PM, Wang, Wei W wrote:
On Thursday, December 21, 2023 7:54 PM, Li, Xiaoyao wrote:
On 12/21/2023 6:36 PM, Wang, Wei W wrote:
No need to specifically check for KVM_MEMORY_ATTRIBUTE_PRIVATE there.
I'm suggesting below:
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
09.01.2024 05:08, Zhang, Chen :
-Original Message-
From: Michael Tokarev
Sent: Sunday, January 7, 2024 7:25 PM
To: qemu-devel@nongnu.org
Cc: Michael Tokarev ; qemu-triv...@nongnu.org; Zhang,
Chen ; Li Zhijian
Subject: [PATCH trivial] colo: examples: remove mentions of script= and
On Tue, 09 Jan 2024 02:15:21 +0900,
Samuel Tardieu wrote:
>
> The shix machine has been designed and used at Télécom Paris from 2003
> to 2010. It had been added to QEMU in 2005 and has not been maintained
> since. Since nobody is using the physical board anymore nor interested
> in maintaining
On 1/8/2024 10:44 PM, Daniel P. Berrangé wrote:
On Fri, Dec 29, 2023 at 10:30:15AM +0800, Xiaoyao Li wrote:
On 11/16/2023 1:58 AM, Daniel P. Berrangé wrote:
On Wed, Nov 15, 2023 at 02:15:01AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation
Currently, when a VF is created, it uses the 'params' object of the PF
as it is. In other words, the 'params.serial' string memory area is
also shared. In this situation, if the VF is removed from the system,
the PF's 'params.serial' object is released with object_finalize()
followed by
>> > However, I'll leave it up to those more familiar with the QEMU numa
>> > control interface design to comment on whether this approach is preferable
>> > to making the gi part of the numa node entry or doing it like hmat.
>>
>> > -numa srat-gi,node-id=10,gi-pci-dev=dev1
>>
>> The current way
>> +##
>> +# @AcpiGenericInitiatorProperties:
>> +#
>> +# Properties for acpi-generic-initiator objects.
>> +#
>> +# @pci-dev: PCI device ID to be associated with the node
>> +#
>> +# @host-nodes: numa node list associated with the PCI device.
>
> NUMA
>
> Suggest "list of NUMA nodes associated
On Mon, Jan 08, 2024 at 12:37:46PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Fri, Jan 05, 2024 at 03:04:49PM -0300, Fabiano Rosas wrote:
> >> [This patch is not necessary anymore after 8.2 has been released]
> >>
> >> Add the 'since' annotations to recently added tests and adapt
在 2023/12/15 下午6:03, Bibo Mao 写道:
There are elements sw_ipmap and sw_coremap, which is usd to speed
up irq injection flow. They are saved and restored in vmstate during
migration, indeed they can calculated from hw registers. Here
post_load is added for get sw_ipmap and sw_coremap from extioi hw
在 2023/12/15 下午6:03, Bibo Mao 写道:
On LoongArch physical machine, one extioi interrupt controller only
supports 4 cpus. With processor more than 4 cpus, there are multiple
extioi interrupt controllers; if interrupts need to be routed to
other cpus, they are forwarded from extioi node0 to other
On Mon, Jan 08, 2024 at 11:49:45AM -0300, Fabiano Rosas wrote:
> >> +
> >> +if (major > tgt_major) {
> >> +return -1;
> >
> > This means the QEMU version is newer, the function will return negative.
> > Is this what we want? It seems it's inverted.
>
> The return "points" to which
在 2023/12/15 下午6:03, Bibo Mao 写道:
LoongArch system has iocsr address space, most iocsr registers are
per-board, however some iocsr register spaces banked for percpu such
as ipi mailbox and extioi interrupt status. For banked iocsr space,
each cpu has the same iocsr space, but separate data.
> -Original Message-
> From: Fabiano Rosas
> Sent: Tuesday, January 9, 2024 4:28 AM
> To: Liu, Yuan1 ; Hao Xiang
> Cc: Bryan Zhang ; qemu-devel@nongnu.org;
> marcandre.lur...@redhat.com; pet...@redhat.com; quint...@redhat.com;
> peter.mayd...@linaro.org; berra...@redhat.com
> Subject:
On Mon, Jan 08, 2024 at 11:26:04AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Wed, Jun 07, 2023 at 10:27:15AM +0200, Juan Quintela wrote:
> >> Fabiano Rosas wrote:
> >> > We've found the source of flakiness in this test, so re-enable it.
> >> >
> >> > Signed-off-by: Fabiano Rosas
> -Original Message-
> From: Michael Tokarev
> Sent: Sunday, January 7, 2024 7:25 PM
> To: qemu-devel@nongnu.org
> Cc: Michael Tokarev ; qemu-triv...@nongnu.org; Zhang,
> Chen ; Li Zhijian
> Subject: [PATCH trivial] colo: examples: remove mentions of script= and
> (wrong) downscript=
在 2023/12/15 下午6:03, Bibo Mao 写道:
There are two interface pairs for MemoryRegionOps, read/write and
read_with_attrs/write_with_attrs. The later is better for ipi device
emulation since initial cpu can be parsed from attrs.requester_id.
And requester_id can be overrided for IOCSR_IPI_SEND and
在 2024/1/9 上午4:26, David Woodhouse 写道:
From: David Woodhouse
Signed-off-by: David Woodhouse
---
hw/loongarch/virt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index
Hi Babu,
On Mon, Jan 08, 2024 at 11:46:50AM -0600, Moger, Babu wrote:
> Date: Mon, 8 Jan 2024 11:46:50 -0600
> From: "Moger, Babu"
> Subject: Re: [PATCH v7 00/16] Support smp.clusters for x86 in QEMU
>
> Hi Zhao,
>
> Ran few basic tests on AMD systems. Changes look good.
>
> Thanks
> Babu
>
On Mon, Jan 08, 2024 at 05:05:38PM -0800, Hao Xiang wrote:
> On Mon, Jan 8, 2024 at 2:47 PM Hao Xiang wrote:
> >
> > On Mon, Jan 8, 2024 at 9:15 AM Gregory Price
> > wrote:
> > >
> > > On Fri, Jan 05, 2024 at 09:59:19PM -0800, Hao Xiang wrote:
> > > > On Wed, Jan 3, 2024 at 1:56 PM Gregory
On Mon, Jan 8, 2024 at 2:47 PM Hao Xiang wrote:
>
> On Mon, Jan 8, 2024 at 9:15 AM Gregory Price
> wrote:
> >
> > On Fri, Jan 05, 2024 at 09:59:19PM -0800, Hao Xiang wrote:
> > > On Wed, Jan 3, 2024 at 1:56 PM Gregory Price
> > > wrote:
> > > >
> > > > For a variety of performance reasons,
Ping for review, thanks!!
> -Original Message-
> From: Alvin Che-Chia Chang(張哲嘉)
> Sent: Tuesday, December 19, 2023 8:33 PM
> To: qemu-ri...@nongnu.org; qemu-devel@nongnu.org
> Cc: alistair.fran...@wdc.com; bin.m...@windriver.com;
> liwei1...@gmail.com; dbarb...@ventanamicro.com;
>
On Mon, Jan 8, 2024 at 10:13 AM Alistair Francis wrote:
>
> A few bug fixes for some Gitlab issues and a Coverity fix
>
> Alistair Francis (3):
> target/riscv: Assert that the CSR numbers will be correct
> target/riscv: Don't adjust vscause for exceptions
> target/riscv: Ensure mideleg is
On Mon, Jan 8, 2024 at 10:10 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 1/5/24 19:13, Atish Patra wrote:
> > From: Kaiwen Xue
> >
> > This adds the properties for ISA extension smcntrpmf. Patches
> > implementing it will follow.
> >
> > Signed-off-by: Atish Patra
> > Signed-off-by: Kaiwen Xue
From: Kaiwen Xue
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by:
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 6 ++
target/riscv/cpu_bits.h | 29 +
2 files changed, 35
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP
From: Hao Wu
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2
From: Hao Wu
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 2 ++
From: Nabih Estefan Diaz
Implement Update IRQ Method for GMAC functionality.
Added relevant trace-events
Change-Id: I7a2d3cd3f493278bcd0cf483233c1e05c37488b7
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/net/npcm_gmac.c | 40
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu
Signed-off-by: Nabih
From: Nabih Estefan Diaz
[Changes since v10]
Fixed macOS build issue. Changed imports to not be linux-specific.
[Changes since v9]
More cleanup and fixes based on suggestions from Peter Maydell
(peter.mayd...@linaro.org) suggestions.
[Changes since v8]
Suggestions and Fixes from Peter Maydell
On Thu, Nov 23, 2023 at 5:53 AM Peter Maydell wrote:
>
> On Mon, 20 Nov 2023 at 19:19, John Snow wrote:
> >
> > On Wed, Nov 15, 2023 at 12:23 PM Daniel P. Berrangé
> > wrote:
> > > The Python Machine() class has passed one of a pre-created socketpair
> > > FDs for the serial port chardev. The
On Mon, Dec 18, 2023 at 8:20 AM Markus Armbruster wrote:
>
> Maksim Davydov writes:
>
> > On 12/1/23 12:51, Markus Armbruster wrote:
> >> Review, anyone?
> >
> > Only Vladimir
>
> To be clear: I'm soliciting a second review.
>
> [...]
>
I volunteer to review it from the Python maintenance POV,
Both the report() function as well as the initial gdbstub test sequence
are copy-pasted into ~10 files with slight modifications. This
indicates that they are indeed generic, so factor them out. While
at it, add a few newlines to make the formatting closer to PEP-8.
Signed-off-by: Ilya
gdbserver ignores page protection by virtue of using /proc/$pid/mem.
Teach qemu gdbstub to do this too. This will not work if /proc is not
mounted; accept this limitation.
One alternative is to temporarily grant the missing PROT_* bit, but
this is inherently racy. Another alternative is
RFC: https://lists.gnu.org/archive/html/qemu-devel/2023-12/msg02044.html
RFC -> v1: Use /proc/self/mem and accept that this will not work
without /proc.
Factor out a couple functions for gdbstub testing.
Add a test.
Hi,
I've noticed that gdbstub behaves
Make sure that qemu gdbstub, like gdbserver, allows reading from and
writing to PROT_NONE pages.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/Makefile.target | 9 +-
tests/tcg/multiarch/gdbstub/prot-none.py | 22 ++
tests/tcg/multiarch/prot-none.c | 38
On Mon, Jan 1, 2024 at 4:45 PM Hervé Poussineau wrote:
>
> Ping.
>
> Le 12/08/2023 à 10:59, Hervé Poussineau a écrit :
> > I don't understand when SEEK must be set or not, but it seems to fix
> > Minix...
> >
> > Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1522
> > Signed-off-by: Hervé
On 8/1/24 22:13, Richard Henderson wrote:
On 1/9/24 04:15, Philippe Mathieu-Daudé wrote:
+/*
+ * This can't go in hw/core/cpu.c because that file is compiled only
+ * once for both user-mode and system builds.
+ */
static Property cpu_common_props[] = {
-#ifndef CONFIG_USER_ONLY
+#ifdef
On 8/1/24 23:27, Nabih Estefan wrote:
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC
Hi Samuel,
On 8/1/24 18:15, Samuel Tardieu wrote:
The shix machine has been designed and used at Télécom Paris from 2003
to 2010. It had been added to QEMU in 2005 and has not been maintained
since. Since nobody is using the physical board anymore nor interested
in maintaining the QEMU port, it
On 8/1/24 20:20, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(!(iotlb & ~TARGET_PAGE_MASK))" check in tlb_set_page_full().
Ensure that the host ROM memory
On 8/1/24 19:03, Inès Varhol wrote:
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates
more than 32 event/interrupt requests and thus uses more registers
than STM32F4xx EXTI which generates 23 event/interrupt requests.
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Il lun 8 gen 2024, 22:45 Richard Henderson
ha scritto:
> > I was thinking: a lot of RISC targets simply do AND/ANDI
> > followed by the sequence used for TCG_COND_NE. Would it make sense to
> > have a TCG_TARGET_SUPPORTS_TST bit and, if absent, lower TSTEQ/TSTNE
> > to AND+EQ/NE directly in the
Hello Cedric,
On 12/12/23 08:48, Cédric Le Goater wrote:
On 11/29/23 00:56, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an
Replace the old Hexagon dectree.py with QEMU decodetree
Taylor Simpson (3):
Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
Hexagon (target/hexagon) Remove old dectree.py
target/hexagon/decode.h
The Decodetree Specification can be found here
https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructions, including HVX
We generate separate decoders for each instruction class. The reason
will be more apparent in the next patch in this series.
We add 2 new scripts
Section 10.3 of the Hexagon V73 Programmer's Reference Manual
A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
The sub-instructions that comprise a duplex are encoded as 13-bit fields
in the duplex.
Create a decoder for each subinstruction class (a, l1, l2, s1, s2).
Now that we are using QEMU decodetree.py, remove the old decoder
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.h| 2 -
target/hexagon/decode.c | 344
target/hexagon/gen_dectree_import.c | 49
target/hexagon/opcodes.c
On Mon, Jan 8, 2024 at 9:15 AM Gregory Price wrote:
>
> On Fri, Jan 05, 2024 at 09:59:19PM -0800, Hao Xiang wrote:
> > On Wed, Jan 3, 2024 at 1:56 PM Gregory Price
> > wrote:
> > >
> > > For a variety of performance reasons, this will not work the way you
> > > want it to. You are essentially
On Fri, Dec 22, 2023 at 7:51 AM Markus Armbruster wrote:
>
> Something odd is going on here.
>
> Your cover letter and PATCH 4 arrived here with
>
> Content-Type: text/plain; charset=UTF-8
>
> Good.
>
> PATCH 2:
>
> Content-Type: text/plain; charset="US-ASCII"; x-default=true
>
> PATCH 1
Hello Cedric,
On 12/12/23 08:49, Cédric Le Goater wrote:
On 11/29/23 00:56, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the
Alex,
A very long time ago QEMU supported disabling the translation cache via
"-translation no-cache". That option was deliberately removed. We are looking
into a hexagon-specific failure when there's a TB lookup miss from a
cpu_loop_exit_restore().I'd like to test our fix for this
From: Nabih Estefan Diaz
Implement Update IRQ Method for GMAC functionality.
Added relevant trace-events
Change-Id: I7a2d3cd3f493278bcd0cf483233c1e05c37488b7
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/net/npcm_gmac.c | 40
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu
Signed-off-by: Nabih
From: Hao Wu
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 2 ++
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2
From: Hao Wu
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication
From: Nabih Estefan Diaz
[Changes since v9]
More cleanup and fixes based on suggestions from Peter Maydell
(peter.mayd...@linaro.org) suggestions.
[Changes since v8]
Suggestions and Fixes from Peter Maydell (peter.mayd...@linaro.org),
also cleaned up changes so nothing is deleted in a later
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff
On 08/01/2024 20:07, Bernhard Beschow wrote:
Am 7. Januar 2024 14:13:44 UTC schrieb Mark Cave-Ayland
:
On 06/01/2024 21:05, Bernhard Beschow wrote:
This series implements relocation of the SuperI/O functions of the VIA south
bridges which resolves some FIXME's. It is part of my
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