John Snow writes:
> On Thu, Nov 23, 2023 at 9:12 AM Markus Armbruster wrote:
>>
>> John Snow writes:
>>
>> > Dict[str, object] is a stricter type, but with the way that code is
>> > currently arranged, it is infeasible to enforce this strictness.
>> >
>> > In particular, although expr.py's
John Snow writes:
> On Wed, Nov 22, 2023 at 11:02 AM John Snow wrote:
>>
>> On Wed, Nov 22, 2023 at 9:05 AM Markus Armbruster wrote:
>> >
>> > John Snow writes:
>> >
>> > > There are two related changes here:
>> > >
>> > > (1) We need to perform type narrowing for resolving the type of
>> > >
Hello Ninad,
Here are comments on the file organization and configs.
On 11/29/23 00:56, Ninad Palsule wrote:
Hello,
Please review the patch-set version 8.
I have incorporated review comments from Cedric.
- Fixed checkpatch failures.
- Fixed commit messages.
- Fixed LBUS memory map
On Wed, Dec 13, 2023 at 10:11:32AM -0800, Steve Sistare wrote:
> After calling notifiers, check if an error has been reported via
> migrate_set_error, and halt the migration.
>
> None of the notifiers call migrate_set_error at this time, so no
> functional change.
>
> Signed-off-by: Steve
From: Philippe Mathieu-Daudé
There might be cases where we know the number of bytes we can
pop from the FIFO, or we simply don't care how many bytes is
returned. Allow fifo8_pop_buf() to take a NULL numptr.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Reviewed-by:
From: Philippe Mathieu-Daudé
To be able to peek at FIFO content without popping it,
introduce the fifo8_peek_buf() method by factoring
common content from fifo8_pop_buf().
Reviewed-by: Francisco Iglesias
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard
The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2024-01-09 10:32:23 +)
are available in the Git repository at:
https://github.com/mcayland/qemu.git tags/qemu-sparc-20240110
On Wed, Dec 13, 2023 at 10:11:31AM -0800, Steve Sistare wrote:
> The existing notifiers should only apply to normal mode.
>
> No functional change.
Instead of adding such check in every notifier, why not make CPR a separate
list of notifiers? Just like the blocker lists.
Aside of this patch, I
On 05/01/2024 07:50, Mark Cave-Ayland wrote:
On 09/11/2023 19:28, Philippe Mathieu-Daudé wrote:
Missing review: #10
Hi,
This series add support for (async) FIFO on the transmit path
of the PL011 UART.
Since v3:
- Document migration bits (Alex, Richard)
- Just check FIFO is not empty in
On Jan 9 11:29, Minwoo Im wrote:
> Currently, when a VF is created, it uses the 'params' object of the PF
> as it is. In other words, the 'params.serial' string memory area is
> also shared. In this situation, if the VF is removed from the system,
> the PF's 'params.serial' object is released
On Nov 27 16:56, Sam Li wrote:
> ZNS emulation follows NVMe ZNS spec but the state of namespace
> zones does not persist accross restarts of QEMU. This patch makes the
> metadata of ZNS emulation persistent by using new block layer APIs and
> the qcow2 img as backing file. It is the second part
On Wed, Jan 10, 2024 at 07:03:06AM +0100, Markus Armbruster wrote:
> Peter Xu writes:
>
> > On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
> >> Hi Fabiano,
> >>
> >> On 9/1/24 21:21, Fabiano Rosas wrote:
> >> > Cédric Le Goater writes:
> >> >
> >> > > On 1/9/24 18:40,
For now, SEV pins guest's memory to avoid swapping or
moving ciphertext, but leading to the inhibition of
Memory Ballooning.
In Memory Ballooning, only guest's free pages will be relocated
in balloon inflation and deflation, so the difference of plaintext
doesn't matter to guest.
Memory
Peter Xu writes:
> On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
>> Hi Fabiano,
>>
>> On 9/1/24 21:21, Fabiano Rosas wrote:
>> > Cédric Le Goater writes:
>> >
>> > > On 1/9/24 18:40, Fabiano Rosas wrote:
>> > > > Cédric Le Goater writes:
>> > > >
>> > > > > On
On 1/10/24 05:09, Philippe Mathieu-Daudé wrote:
cpu_isar_feature(aa64_mte, cpu) is testing a AArch64-only ID
register. The ARM_FEATURE_AARCH64 check is redundant.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
On 1/10/24 10:05, Ilya Leoshkevich wrote:
gdbserver ignores page protection by virtue of using /proc/$pid/mem.
Teach qemu gdbstub to do this too. This will not work if /proc is not
mounted; accept this limitation.
One alternative is to temporarily grant the missing PROT_* bit, but
this is
On Mon, Jan 8, 2024 at 7:36 AM Philippe Mathieu-Daudé wrote:
> Don't we want to initialize min_pktsz here ...
>
>min_pktsz = sizeof(min_pkt);
>
> > +if (eth_pad_short_frame(min_pkt, _pktsz, pkt, pktsz)) {
>
> ... because eth_pad_short_frame() update it?
Thanks for the
Hello,
qcow2-rs[1] is one pure Rust library for reading/writing qcow2 image, it is
based on rsd's[2] internal qcow2 implementation, but with lots of change, so
far:
- supports read/write on data file, backing file and compressed image
- block device like interface, minimized read/write unit is
On Tue, Jan 09, 2024 at 11:46:32AM -0300, Fabiano Rosas wrote:
> Hm, it would be better to avoid the extra maintenance task at the start
> of every release, no? It also blocks us from doing n-2 even
> experimentally.
See my other reply, on whether we can use "n-1" for migration-test. If
that can
When sdtrig is turned off by "sdtrig=false" option, raise
and illegal instruction exception on any read/write to
sdtrig CSRs.
Signed-off-by: Himanshu Chauhan
---
target/riscv/csr.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
This patch makes the debug trigger (sdtrig) capability
as an extension and exports it as an ISA string. The sdtrig
extension may or may not be implemented in a system. The
-cpu rv64,sdtrig=
option can be used to dynamicaly turn sdtrig extension
on or off.
Signed-off-by: Himanshu Chauhan
All the CPUs may or may not implement the debug trigger (sdtrig)
extension. The presence of it should be dynamically detectable.
This patch exports the debug triggers as an extension which
can be turned on or off by sdtrig= option. It is
turned on by default.
"sdtrig" is concatenated to ISA
On Tue, Jan 09, 2024 at 10:00:17AM -0300, Fabiano Rosas wrote:
> > Can we opt-out those broken tests using either your "since:" thing or
> > anything similar?
>
> If it's something migration related, then yes. But there might be other
> types of breakages that have nothing to do with migration.
On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Fabiano,
>
> On 9/1/24 21:21, Fabiano Rosas wrote:
> > Cédric Le Goater writes:
> >
> > > On 1/9/24 18:40, Fabiano Rosas wrote:
> > > > Cédric Le Goater writes:
> > > >
> > > > > On 1/3/24 20:53, Fabiano Rosas wrote:
在 2023/12/15 下午6:03, Bibo Mao 写道:
On LoongArch system, there is iocsr address space simliar system io
address space on x86. And each cpu has its separate iocsr address space now,
with this patch, iocsr address space is changed with per-board, and
MemTxAttrs.requester_id is used to differentiate
在 2024/1/5 下午3:57, Tianrui Zhao 写道:
The linux headers in this patch synchronized from linux kernel
v6.7.0-rc8, and the loongarch kvm part of this patch series
based on the header files. And the linux kernel has added the
loongarch kvm support in master branch.
This series add loongarch kvm
On Tue, Jan 09, 2024 at 02:21:26PM +0100, Cédric Le Goater wrote:
>
> > A few things I'd like to mention alongside, because it's documentation
> > relevant too, and I'd like to collect if there's any comment.
> >
> > I just mostly rewrote two wiki pages completely:
> >
> >
在 2024/1/5 下午3:58, Tianrui Zhao 写道:
Add kvm.c into meson.build to compile it when kvm
is configed. Meanwhile in meson.build, we set the
kvm_targets to loongarch64-softmmu when the cpu is
loongarch. And fix the compiling error when config
is enable-kvm,disable-tcg.
Signed-off-by: Tianrui Zhao
On Tue, Jan 09, 2024 at 02:03:04PM -0300, Fabiano Rosas wrote:
> pet...@redhat.com writes:
>
> > From: Peter Xu
> >
> > Move the two sections into a separate file called "best-practises.rst".
>
> s/practises/practices/
Will fix, thanks.
--
Peter Xu
On Wednesday, January 10, 2024 12:32 AM, Li, Xiaoyao wrote:
> On 1/9/2024 10:53 PM, Wang, Wei W wrote:
> > On Tuesday, January 9, 2024 1:47 PM, Li, Xiaoyao wrote:
> >> On 12/21/2023 9:47 PM, Wang, Wei W wrote:
> >>> On Thursday, December 21, 2023 7:54 PM, Li, Xiaoyao wrote:
> On 12/21/2023
> -Original Message-
> From: Michael Tokarev
> Sent: Tuesday, January 9, 2024 1:44 PM
> To: Zhang, Chen ; qemu-devel@nongnu.org
> Cc: qemu-triv...@nongnu.org; Li Zhijian
> Subject: Re: [PATCH trivial] colo: examples: remove mentions of script= and
> (wrong) downscript=
>
> 09.01.2024
On Wed, Nov 22, 2023 at 11:02 AM John Snow wrote:
>
> On Wed, Nov 22, 2023 at 9:05 AM Markus Armbruster wrote:
> >
> > John Snow writes:
> >
> > > There are two related changes here:
> > >
> > > (1) We need to perform type narrowing for resolving the type of
> > > tag_member during check(),
> -Original Message-
> From: Daniel Henrique Barboza
> Sent: Wednesday, January 10, 2024 6:04 AM
> To: Alvin Che-Chia Chang(張哲嘉) ;
> qemu-ri...@nongnu.org; qemu-devel@nongnu.org
> Cc: alistair.fran...@wdc.com; bin.m...@windriver.com;
> liwei1...@gmail.com; zhiwei_...@linux.alibaba.com
>
On Thu, Nov 23, 2023 at 8:51 AM Markus Armbruster wrote:
>
> John Snow writes:
>
> > I'm actually not too sure about this one, it seems to hold up at runtime
> > but instead of lying and coming up with an elaborate ruse as a commit
> > message I'm just going to admit I just cribbed my own notes
On Thu, Nov 23, 2023 at 9:12 AM Markus Armbruster wrote:
>
> John Snow writes:
>
> > Dict[str, object] is a stricter type, but with the way that code is
> > currently arranged, it is infeasible to enforce this strictness.
> >
> > In particular, although expr.py's entire raison d'être is
On Tue, Jan 9, 2024 at 2:13 PM Gregory Price wrote:
>
> On Tue, Jan 09, 2024 at 01:27:28PM -0800, Hao Xiang wrote:
> > On Tue, Jan 9, 2024 at 11:58 AM Gregory Price
> > wrote:
> > >
> > > If you drop this line:
> > >
> > > -numa node,memdev=vmem0,nodeid=1
> >
> > We tried this as well and it
Hi,
Ido has noticed that LAE sets a wrong access register and proposed a
fix. This series fixes the issue and adds a test.
Best regards,
Ilya
Ilya Leoshkevich (2):
target/s390x: Fix LAE setting a wrong access register
tests/tcg/s390x: Test LOAD ADDRESS EXTENDED
Add a small test to prevent regressions. Userspace runs in primary
mode, so LAE should always set the access register to 0.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/lae.c | 25 +
2 files changed, 26
LAE should set the access register corresponding to the first operand,
instead, it always modifies access register 1.
Co-developed-by: Ido Plat
Cc: qemu-sta...@nongnu.org
Fixes: a1c7610a6879 ("target-s390x: implement LAY and LAEY instructions")
Signed-off-by: Ilya Leoshkevich
---
Both the report() function as well as the initial gdbstub test sequence
are copy-pasted into ~10 files with slight modifications. This
indicates that they are indeed generic, so factor them out. While
at it, add a few newlines to make the formatting closer to PEP-8.
Signed-off-by: Ilya
v1 -> v2: Use /proc/self/mem as a fallback. Handle TB invalidation
(Richard).
Test cross-page accesses.
RFC: https://lists.gnu.org/archive/html/qemu-devel/2023-12/msg02044.html
RFC -> v1: Use /proc/self/mem and accept that this will not work
without /proc.
gdbserver ignores page protection by virtue of using /proc/$pid/mem.
Teach qemu gdbstub to do this too. This will not work if /proc is not
mounted; accept this limitation.
One alternative is to temporarily grant the missing PROT_* bit, but
this is inherently racy. Another alternative is
Make sure that qemu gdbstub, like gdbserver, allows reading from and
writing to PROT_NONE pages.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/Makefile.target | 9 +-
tests/tcg/multiarch/gdbstub/prot-none.py | 22 +
tests/tcg/multiarch/prot-none.c | 40
Am 9. Januar 2024 08:51:37 UTC schrieb David Woodhouse :
>On Mon, 2024-01-08 at 00:16 +0100, Bernhard Beschow wrote:
>> This is a follow-up on commit 89965db43cce "hw/isa/piix3: Avoid Xen-specific
>> variant of piix3_write_config()" which introduced
>> piix_intx_routing_notifier_xen(). This
This is a part of patchset where FSI bus is introduced.
The FSI bus is a simple bus where FSI master is attached.
[ clg: - removed include/hw/fsi/engine-scratchpad.h and
hw/fsi/engine-scratchpad.c
- dropped FSI_SCRATCHPAD
- included FSIBus definition
- dropped
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain mapped memory for the devices. The
memory is mapped after CFAM config, peek table and FSI slave registers.
[ clg: - removed lbus_add_device() bc unused
- removed
Hello,
Please review the patch-set version 9.
I have incorporated review comments from Cedric.
Ninad Palsule (10):
hw/fsi: Introduce IBM's Local bus
hw/fsi: Introduce IBM's FSI Bus
hw/fsi: Introduce IBM's cfam,fsi-slave,scratchpad
hw/fsi: IBM's On-chip Peripheral Bus
hw/fsi: Introduce
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang
Documentation for IBM FSI model.
Signed-off-by: Cédric Le Goater
Signed-off-by: Ninad Palsule
---
docs/specs/fsi.rst | 138 +++
docs/specs/index.rst | 1 +
2 files changed, 139 insertions(+)
create mode 100644 docs/specs/fsi.rst
diff --git
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI master. CFAM is hanging out of FSI master which is a
bus controller.
The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER
Added maintainer for IBM FSI model
Signed-off-by: Cédric Le Goater
Signed-off-by: Ninad Palsule
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 00ec1f7eca..79f97a3fb9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3569,6 +3569,14 @@
Added basic qtests for FSI model.
Acked-by: Thomas Huth
Signed-off-by: Cédric Le Goater
Signed-off-by: Ninad Palsule
---
tests/qtest/aspeed-fsi-test.c | 205 ++
tests/qtest/meson.build | 1 +
2 files changed, 206 insertions(+)
create mode 100644
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
[ clg: -
This patchset introduces IBM's Flexible Service Interface(FSI).
Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.
FSI has long existed in POWER processes and so comes with
On Tue, Jan 09, 2024 at 01:27:28PM -0800, Hao Xiang wrote:
> On Tue, Jan 9, 2024 at 11:58 AM Gregory Price
> wrote:
> >
> > If you drop this line:
> >
> > -numa node,memdev=vmem0,nodeid=1
>
> We tried this as well and it works after going through the cxlcli
> process and created the devdax
Am 8. Januar 2024 22:12:12 UTC schrieb Mark Cave-Ayland
:
>On 08/01/2024 20:07, Bernhard Beschow wrote:
>
>> Am 7. Januar 2024 14:13:44 UTC schrieb Mark Cave-Ayland
>> :
>>> On 06/01/2024 21:05, Bernhard Beschow wrote:
>>>
This series implements relocation of the SuperI/O functions of
Hello Cedric,
+
+#define TYPE_FSI_SCRATCHPAD "fsi.scratchpad"
+#define SCRATCHPAD(obj) OBJECT_CHECK(FSIScratchPad, (obj),
TYPE_FSI_SCRATCHPAD)
+
+typedef struct FSIScratchPad {
+ FSILBusDevice parent;
+
+ uint32_t reg;
+} FSIScratchPad;
We could extend to 4 regs possibly.
On 12/19/23 09:32, Alvin Chang wrote:
The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.
Signed-off-by: Alvin Chang
---
The patch per se LGTM:
On 2024-01-10 08:33:11+1100, Richard Henderson wrote:
> On 1/8/24 01:01, Thomas Weißschuh wrote:
> > Signed-off-by: Thomas Weißschuh
> > ---
> > Changes in v2:
> > - Rebase on 8.2 master
> > - Resend after closed tree and holidays
> > - Link to v1:
> >
On 1/10/24 08:06, Helge Deller wrote:
What evidence? So far, all I can see is for your seabios button, which doesn't run on
physical hardware.
You are wrong on this.
My Seabios just mimics the real hardware. And the hardware has such a button
which is reported back by the PDC firmware.
Here
On 08/01/2024 23:06, Philippe Mathieu-Daudé wrote:
On 8/1/24 20:20, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(!(iotlb & ~TARGET_PAGE_MASK))" check in
On 1/10/24 06:39, Ilya Leoshkevich wrote:
On Wed, 2024-01-10 at 04:42 +1100, Richard Henderson wrote:
On 1/9/24 10:34, Ilya Leoshkevich wrote:
gdbserver ignores page protection by virtue of using
/proc/$pid/mem.
Teach qemu gdbstub to do this too. This will not work if /proc is
not
mounted;
On 1/8/24 23:53, Philippe Mathieu-Daudé wrote:
@@ -818,6 +867,9 @@ static void pflash_cfi01_realize(DeviceState *dev, Error
**errp)
pfl->cmd = 0x00;
pfl->status = 0x80; /* WSM ready */
pflash_cfi01_fill_cfi_table(pfl);
+
+pfl->blk_bytes = g_malloc(pfl->writeblock_size);
On 1/8/24 01:01, Thomas Weißschuh wrote:
Signed-off-by: Thomas Weißschuh
---
Changes in v2:
- Rebase on 8.2 master
- Resend after closed tree and holidays
- Link to v1:
https://lore.kernel.org/r/20231115-qemu-user-dumpable-v1-0-edbe7f0fb...@t-8ch.de
---
Thomas Weißschuh (2):
On Tue, Jan 9, 2024 at 11:58 AM Gregory Price
wrote:
>
> On Tue, Jan 09, 2024 at 11:33:04AM -0800, Hao Xiang wrote:
> > On Mon, Jan 8, 2024 at 5:13 PM Gregory Price
> > wrote:
> >
> > Sounds like the technical details are explained on the other thread.
> > From what I understand now, if we
Hi Fabiano,
On 9/1/24 21:21, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 1/9/24 18:40, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 1/3/24 20:53, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
+Peter/Fabiano
On 2/1/24 17:41, Cédric Le Goater wrote:
On 1/2/24 17:15,
On 9/1/24 13:56, Albert Esteve wrote:
Functions in the virtio-dmabuf module
start with 'virtio_*', which is too
generic and may not correctly identify
them as part of the virtio dmabuf API.
Rename all functions to 'virtio_dmabuf_*'
instead to avoid confusion.
Signed-off-by: Albert Esteve
On 9/1/24 19:45, Samuel Tardieu wrote:
Signed-off-by: Samuel Tardieu
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
---
hw/timer/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/1/24 22:07, Philippe Mathieu-Daudé wrote:
Hi Cédric,
On 9/1/24 19:06, Cédric Le Goater wrote:
On 1/9/24 18:40, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 1/3/24 20:53, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
+Peter/Fabiano
On 2/1/24 17:41, Cédric Le Goater
Hi Cédric,
On 9/1/24 19:06, Cédric Le Goater wrote:
On 1/9/24 18:40, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 1/3/24 20:53, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
+Peter/Fabiano
On 2/1/24 17:41, Cédric Le Goater wrote:
On 1/2/24 17:15, Philippe Mathieu-Daudé
On 1/9/24 17:18, Richard Henderson wrote:
On 1/9/24 22:22, Helge Deller wrote:
On 1/9/24 10:14, Richard Henderson wrote:
On 1/8/24 00:22, del...@kernel.org wrote:
From: Helge Deller
Fix the address translation for PDC space on PA2.0 if PSW.W=0.
Basically, for any address in the 32-bit PDC
Cédric Le Goater writes:
> On 1/5/24 19:04, Fabiano Rosas wrote:
>> The migration tests have support for being passed two QEMU binaries to
>> test migration compatibility.
>>
>> Add a CI job that builds the lastest release of QEMU and another job
>> that uses that version plus an already
Hello Cedric,
+ for (i = 0; i < ASPEED_FSI_NUM; i++) {
+ if (!qdev_realize_and_unref(DEVICE(>fsi[i]),
BUS(>opb[i]),
s->fsi[i] is not allocated. We should use qdev_realize instead.
I am not sure I understood this. FSIMasterState fsi[ASPEED_FSI_NUM];
is inside structure
Cédric Le Goater writes:
> On 1/9/24 18:40, Fabiano Rosas wrote:
>> Cédric Le Goater writes:
>>
>>> On 1/3/24 20:53, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
> +Peter/Fabiano
>
> On 2/1/24 17:41, Cédric Le Goater wrote:
>> On 1/2/24 17:15, Philippe
Hello Cedric,
+static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned
size)
+{
+ FSIMasterState *s = FSI_MASTER(opaque);
+
+ trace_fsi_master_read(addr, size);
+
+ if (addr + size > sizeof(s->regs)) {
See comment on patch 3
I fixed it.
+
On Tue, Jan 09, 2024 at 11:33:04AM -0800, Hao Xiang wrote:
> On Mon, Jan 8, 2024 at 5:13 PM Gregory Price
> wrote:
>
> Sounds like the technical details are explained on the other thread.
> From what I understand now, if we don't go through a complex CXL
> setup, it wouldn't go through the
The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO
device will be implemented, its output GPIOs will be connected to the
SYSCFG input GPIOs.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
This patch adds a new device STM32L4x5 SYSCFG device and is part
of a series implementing the STM32L4x5 with a few peripherals.
Changes from v3 to v4:
- swapping commit 2 (add tests) and commit 3 (connect syscfg to SoC)
so that the tests pass in the commit they're added
- in
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4x5_syscfg-test.c | 331
2 files changed,
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
docs/system/arm/b-l475e-iot01a.rst | 2 +-
hw/misc/Kconfig| 3 +
hw/misc/meson.build| 1 +
hw/misc/stm32l4x5_syscfg.c | 266 +
On Wed, 2024-01-10 at 04:42 +1100, Richard Henderson wrote:
> On 1/9/24 10:34, Ilya Leoshkevich wrote:
> > gdbserver ignores page protection by virtue of using
> > /proc/$pid/mem.
> > Teach qemu gdbstub to do this too. This will not work if /proc is
> > not
> > mounted; accept this limitation.
> >
On Tue, Jan 09, 2024 at 11:36:03AM -0800, Dan Williams wrote:
> Jason Gunthorpe wrote:
> > On Tue, Jan 09, 2024 at 06:02:03PM +0100, David Hildenbrand wrote:
> > > > Given that, an alternative proposal that I think would work
> > > > for you would be to add a 'placeholder' memory node definition
>
Jason Gunthorpe wrote:
> On Tue, Jan 09, 2024 at 06:02:03PM +0100, David Hildenbrand wrote:
> > > Given that, an alternative proposal that I think would work
> > > for you would be to add a 'placeholder' memory node definition
> > > in SRAT (so allow 0 size explicitly - might need a new SRAT
> > >
On Mon, Jan 8, 2024 at 5:13 PM Gregory Price wrote:
>
> On Mon, Jan 08, 2024 at 05:05:38PM -0800, Hao Xiang wrote:
> > On Mon, Jan 8, 2024 at 2:47 PM Hao Xiang wrote:
> > >
> > > On Mon, Jan 8, 2024 at 9:15 AM Gregory Price
> > > wrote:
> > > >
> > > > On Fri, Jan 05, 2024 at 09:59:19PM -0800,
Hello Cedric,
On 12/12/23 08:46, Cédric Le Goater wrote:
On 11/29/23 00:56, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain mapped memory for the devices. The
memory is mapped after CFAM config, peek table
From: Ari Sundholm
There is a bug in the blklogwrites driver pertaining to logging "write
zeroes" operations, causing log corruption. This can be easily observed
by setting detect-zeroes to something other than "off" for the driver.
The issue is caused by a concurrency bug pertaining to the
Signed-off-by: Samuel Tardieu
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
---
hw/timer/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 3eccef83858..8145e18e3da 100644
--- a/hw/timer/trace-events
On 1/9/24 8:25 AM, David Hildenbrand wrote:
On 09.01.24 15:15, Daniel P. Berrangé wrote:
On Tue, Jan 09, 2024 at 03:02:00PM +0100, David Hildenbrand wrote:
On 08.01.24 19:40, Mark Kanda wrote:
On 1/8/24 9:40 AM, David Hildenbrand wrote:
On 08.01.24 16:10, Mark Kanda wrote:
Refactor the
On 1/8/24 21:25, Atish Patra wrote:
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 2 ++
On 9/1/24 19:09, Philippe Mathieu-Daudé wrote:
The "has_el2" property is added to ARMCPU when the
ARM_FEATURE_EL2 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
On 9/1/24 19:09, Philippe Mathieu-Daudé wrote:
The "has_el3" property is added to ARMCPU when the
ARM_FEATURE_EL3 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
On 9/1/24 19:13, Philippe Mathieu-Daudé wrote:
On 9/1/24 19:09, Philippe Mathieu-Daudé wrote:
The "has_el3" property is added to ARMCPU when the
ARM_FEATURE_EL3 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus
Commit ff32bb53 tried to get minimal struct support into the string
output visitor by just making it return "". Unfortunately, it
forgot that the caller will still make more visitor calls for the
content of the struct.
If the struct is contained in a list, such as IOThreadVirtQueueMapping,
in the
On 1/5/24 19:04, Fabiano Rosas wrote:
The migration tests have support for being passed two QEMU binaries to
test migration compatibility.
Add a CI job that builds the lastest release of QEMU and another job
that uses that version plus an already present build of the current
version and run the
On 9/1/24 19:09, Philippe Mathieu-Daudé wrote:
The "has_el3" property is added to ARMCPU when the
ARM_FEATURE_EL3 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
The "has_el2" property is added to ARMCPU when the
ARM_FEATURE_EL2 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/vexpress.c | 3 ++-
hw/arm/virt.c
First, the "kvm-no-adjvtime" and "kvm-steal-time" are only
available when KVM is available, so guard this block within
a 'kvm_enabled()' check. Since the "kvm-steal-time" property
is always available under KVM, directly set it.
Then, the "kvm-no-adjvtime" property is added to ARMCPU when
the
The "has_el3" property is added to ARMCPU when the
ARM_FEATURE_EL3 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c | 4 ++--
All CPUs implementing ARM_FEATURE_M have the 'init-nsvtor' property.
Since setting the property can not fail, replace
object_property_set_uint(..., "init-nsvtor", ..., _abort);
by:
qdev_prop_set_uint32(..., "init-nsvtor", ...).
which is a one-to-one replacement.
Suggested-by: Peter
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