Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build

Hi, 在 2024/1/11 下午3:10, Thomas Huth 写道: On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- Used to test https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/ So why is it NOTFORMERGE ? Don't we want to test KVM-only

Re: [PATCH 08/40] vdpa: add back vhost_vdpa_net_first_nc_vdpa

On Fri, Dec 8, 2023 at 2:52 AM Si-Wei Liu wrote: > > Previous commits had it removed. Now adding it back because > this function will be needed by next patches. Need some description to explain why. Because it should not be needed as we have a "parent" structure now, anything that is common

Re: [PATCH 09/40] vdpa: no repeat setting shadow_data

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Since shadow_data is now shared in the parent data struct, it > just needs to be set only once by the first vq. This change > will make shadow_data independent of svq enabled state, which > can be optionally turned off when SVQ descritors and

Re: [PATCH 07/40] vdpa: move around vhost_vdpa_set_address_space_id

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Move it a few lines ahead to make function call easier for those > before it. No funtional change involved. Typo for functional. > > Signed-off-by: Si-Wei Liu Acked-by: Jason Wang Thanks > --- > net/vhost-vdpa.c | 36

Re: [PATCH 06/40] vhost: make svq work with gpa without iova translation

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Make vhost_svq_vring_write_descs able to work with GPA directly > without going through iova tree for translation. This will be > needed in the next few patches where the SVQ has dedicated > address space to host its virtqueues. Instead of

Re: [PATCH] hw/core: Handle cpu_model_from_type() returning NULL value

Hi Phil, On 1/11/24 16:47, Philippe Mathieu-Daudé wrote: Per cpu_model_from_type() docstring (added in commit 445946f4dd): * Returns: CPU model name or NULL if the CPU class doesn't exist We must check the return value in order to avoid surprises, i.e.: $ qemu-system-arm -machine virt

Re: [PATCH 1/2] gitlab: Introduce Loongarch64 runner

Hi, 在 2024/1/11 下午3:08, Thomas Huth 写道: On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote: Full build config to run CI tests on a Loongarch64 host. Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE in their CI namespace settings, see:

Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build

On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- Used to test https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/ So why is it NOTFORMERGE ? Don't we want to test KVM-only builds for loongarch in the long run?

Re: [PATCH 05/40] vdpa: populate desc_group from net_vhost_vdpa_init

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Add the desc_group field to struct vhost_vdpa, and get it > populated when the corresponding vq is initialized at > net_vhost_vdpa_init. If the vq does not have descriptor > group capability, or it doesn't have a dedicated ASID > group to host

Re: [PATCH 1/2] gitlab: Introduce Loongarch64 runner

On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote: Full build config to run CI tests on a Loongarch64 host. Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE in their CI namespace settings, see: https://www.qemu.org/docs/master/devel/ci.html#maintainer-controlled-job-variables

Re: [PATCH 04/40] vdpa: piggyback desc_group index when probing isolated cvq

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Same as the previous commit, but do it for cvq instead of data vqs. > > Signed-off-by: Si-Wei Liu > --- > net/vhost-vdpa.c | 21 + > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/net/vhost-vdpa.c

Re: [RFC PATCH v3 03/30] io: implement io_pwritev/preadv for QIOChannelFile

On Mon, Nov 27, 2023 at 05:25:45PM -0300, Fabiano Rosas wrote: > From: Nikolay Borisov > > The upcoming 'fixed-ram' feature will require qemu to write data to > (and restore from) specific offsets of the migration file. > > Add a minimal implementation of pwritev/preadv and expose them via the

Re: [PATCH v6 1/2] qom: new object to associate device to numa node

On Wed, Jan 10, 2024 at 03:19:05PM -0800, Dan Williams wrote: > David Hildenbrand wrote: > > On 09.01.24 17:52, Jonathan Cameron wrote: > > > On Thu, 4 Jan 2024 10:39:41 -0700 > > > Alex Williamson wrote: > > > > > >> On Thu, 4 Jan 2024 16:40:39 + > > >> Ankit Agrawal wrote: > > >> > > >>>

Re: [RFC PATCH v3 02/30] io: Add generic pwritev/preadv interface

On Mon, Nov 27, 2023 at 05:25:44PM -0300, Fabiano Rosas wrote: > From: Nikolay Borisov > > Introduce basic pwritev/preadv support in the generic channel layer. > Specific implementation will follow for the file channel as this is > required in order to support migration streams with fixed

Re: [PATCH] hw/core: Handle cpu_model_from_type() returning NULL value

On 11/1/24 07:47, Philippe Mathieu-Daudé wrote: Per cpu_model_from_type() docstring (added in commit 445946f4dd): * Returns: CPU model name or NULL if the CPU class doesn't exist We must check the return value in order to avoid surprises, i.e.: $ qemu-system-arm -machine virt -cpu

[PATCH] hw/core: Handle cpu_model_from_type() returning NULL value

Per cpu_model_from_type() docstring (added in commit 445946f4dd): * Returns: CPU model name or NULL if the CPU class doesn't exist We must check the return value in order to avoid surprises, i.e.: $ qemu-system-arm -machine virt -cpu cortex-a9 qemu-system-arm: Invalid CPU model: cortex-a9

Re: [External] Re: [PATCH 3/5] migration: Introduce unimplemented 'qatzip' compression method

On Mon, Jan 8, 2024 at 12:28 PM Fabiano Rosas wrote: > > "Liu, Yuan1" writes: > > >> -Original Message- > >> From: Hao Xiang > >> Sent: Saturday, January 6, 2024 7:53 AM > >> To: Fabiano Rosas > >> Cc: Bryan Zhang ; qemu-devel@nongnu.org; > >> marcandre.lur...@redhat.com;

Re: [PATCH v2 1/2] nubus-device: round Declaration ROM memory region address to qemu_target_page_size()

On 9/1/24 22:53, Mark Cave-Ayland wrote: On 08/01/2024 23:06, Philippe Mathieu-Daudé wrote: On 8/1/24 20:20, Mark Cave-Ayland wrote: Declaration ROM binary images can be any arbitrary size, however if a host ROM memory region is not aligned to qemu_target_page_size() then we fail the

Re: [PATCH 00/10] docs/migration: Reorganize migration documentations

On Tue, Jan 09, 2024 at 02:46:18PM +0800, pet...@redhat.com wrote: > From: Peter Xu > > Migration docs grow larger and larger. There are plenty of things we can > do here in the future, but to start that we'd better reorganize the current > bloated doc files first and properly organize them

Re: [PATCH] target/riscv: Check for 'A' extension on all atomic instructions

On Thu, Jan 11, 2024 at 3:44 AM Rob Bradford wrote: > > Add requirement that 'A' is enabled for all atomic instructions that > lack the check. This makes the 64-bit versions consistent with the > 32-bit versions in the same file. > > Signed-off-by: Rob Bradford Thanks! Applied to

Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]

On 1/8/2024 4:27 PM, Zhao Liu wrote: From: Zhao Liu Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms") is able to handle platforms with Module level enumerated via CPUID.1F. Expose the module level in CPUID[0x1F] if

Re: [PULL 29/71] hw/arm/virt: Check CPU type in machine_run_board_init()

Hi Peter, On 1/10/24 00:33, Peter Maydell wrote: On Fri, 5 Jan 2024 at 15:46, Philippe Mathieu-Daudé wrote: From: Gavin Shan Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do the check by ourselves. Hi; after this

Re: [PATCH v7 07/16] i386: Support modules_per_die in X86CPUTopoInfo

On 1/8/2024 4:27 PM, Zhao Liu wrote: From: Zhuocheng Ding Support module level in i386 cpu topology structure "X86CPUTopoInfo". Since x86 does not yet support the "clusters" parameter in "-smp", X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the module level width in APIC

Re: [External] Re: [PATCH v3 01/20] multifd: Add capability to enable/disable zero_page

On Mon, Jan 8, 2024 at 12:39 PM Fabiano Rosas wrote: > > Hao Xiang writes: > > > From: Juan Quintela > > > > We have to enable it by default until we introduce the new code. > > > > Signed-off-by: Juan Quintela > > --- > > migration/options.c | 15 +++ > > migration/options.h | 1

Re: [External] Re: [PATCH 3/5] migration: Introduce unimplemented 'qatzip' compression method

On Mon, Jan 8, 2024 at 6:26 PM Liu, Yuan1 wrote: > > > -Original Message- > > From: Fabiano Rosas > > Sent: Tuesday, January 9, 2024 4:28 AM > > To: Liu, Yuan1 ; Hao Xiang > > Cc: Bryan Zhang ; qemu-devel@nongnu.org; > > marcandre.lur...@redhat.com; pet...@redhat.com;

[PATCH] hw/arm/virt: Consolidate valid CPU types

It's found that some of the CPU type names in the array of valid CPU types are invalid because their corresponding classes aren't registered, as reported by Peter Maydell. [gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9 qemu-system-arm: Invalid CPU model: cortex-a9 The valid

Re: [PATCH 03/40] vdpa: probe descriptor group index for data vqs

On Fri, Dec 8, 2023 at 2:53 AM Si-Wei Liu wrote: > > Getting it ahead at initialization time instead of start time allows > decision making independent of device status, while reducing failure > possibility in starting device or during migration. > > Adding function vhost_vdpa_probe_desc_group()

Re: [PATCH] target/riscv: Check for 'A' extension on all atomic instructions

On Thu, Jan 11, 2024 at 3:44 AM Rob Bradford wrote: > > Add requirement that 'A' is enabled for all atomic instructions that > lack the check. This makes the 64-bit versions consistent with the > 32-bit versions in the same file. > > Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis

Re: [PATCH 02/40] vdpa: add vhost_vdpa_get_vring_desc_group

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Internal API to get the descriptor group index for a specific virtqueue > through the VHOST_VDPA_GET_VRING_DESC_GROUP ioctl. > > Signed-off-by: Si-Wei Liu Acked-by: Jason Wang Thanks > --- > net/vhost-vdpa.c | 19 +++ > 1

Re: [PATCH 01/40] linux-headers: add vhost_types.h and vhost.h

On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote: > > Signed-off-by: Si-Wei Liu It's better to document which version did this commit sync to. Thanks > --- > include/standard-headers/linux/vhost_types.h | 13 + > linux-headers/linux/vhost.h | 9 + > 2

Re: [PATCH v7 05/16] i386: Decouple CPUID[0x1F] subleaf with specific topology level

On 1/8/2024 4:27 PM, Zhao Liu wrote: From: Zhao Liu At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level. In fact, the specific topology level exposed in 0x1F depends on the platform's support for extension levels (module, tile and die). To help expose "module" level in

Re: [PATCH 00/10] docs/migration: Reorganize migration documentations

On Wed, Jan 10, 2024 at 04:21:12PM +0100, Cédric Le Goater wrote: > We also have a [feature request] label under gitlab and some issues are > tagged with it. I wonder how we can consolidate the 3 sources : wiki, > gitlab, https://www.qemu.org/docs/master/ Thanks for mentioning the gitlab issues!

Re: [PATCH v3 4/4] [NOT FOR MERGE] tests/qtest/migration: Adapt tests to use older QEMUs

On Wed, Jan 10, 2024 at 11:42:18AM -0300, Fabiano Rosas wrote: > Peter Xu writes: > > > On Tue, Jan 09, 2024 at 11:46:32AM -0300, Fabiano Rosas wrote: > >> Hm, it would be better to avoid the extra maintenance task at the start > >> of every release, no? It also blocks us from doing n-2 even >

Re: [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm

Hi, 在 2024/1/10 下午5:41, Philippe Mathieu-Daudé 写道: From: Tianrui Zhao Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao Signed-off-by: xianglai li Reviewed-by: Song Gao

Re: [PATCH V1 2/3] migration: notifier error reporting

On Wed, Jan 10, 2024 at 01:08:41PM -0500, Steven Sistare wrote: > On 1/10/2024 2:18 AM, Peter Xu wrote: > > On Wed, Dec 13, 2023 at 10:11:32AM -0800, Steve Sistare wrote: > >> After calling notifiers, check if an error has been reported via > >> migrate_set_error, and halt the migration. > >> > >>

Re: [PATCH V1 1/3] migration: check mode in notifiers

On Wed, Jan 10, 2024 at 01:08:01PM -0500, Steven Sistare wrote: > On 1/10/2024 2:09 AM, Peter Xu wrote: > > On Wed, Dec 13, 2023 at 10:11:31AM -0800, Steve Sistare wrote: > >> The existing notifiers should only apply to normal mode. > >> > >> No functional change. > > > > Instead of adding such

[PATCH v12 04/10] hw/net: Add NPCMXXX GMAC device

From: Hao Wu This patch implements the basic registers of GMAC device and sets registers for networking functionalities. Tested: The following message shows up with the change: Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)

[PATCH v12 08/10] hw/net: GMAC Rx Implementation

From: Nabih Estefan Diaz - Implementation of Receive function for packets - Implementation for reading and writing from and to descriptors in memory for Rx When RX starts, we need to flush the queued packets so that they can be received by the GMAC device. Without this it won't work with TAP

[PATCH v12 06/10] tests/qtest: Creating qtest for GMAC Module

From: Nabih Estefan Diaz - Created qtest to check initialization of registers in GMAC Module. - Implemented test into Build File. Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- tests/qtest/meson.build | 1 +

[PATCH v12 10/10] tests/qtest: Adding PCS Module test to GMAC Qtest

From: Nabih Estefan Diaz - Add PCS Register check to npcm_gmac-test Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12 Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- tests/qtest/npcm_gmac-test.c | 132 +++ 1 file changed, 132 insertions(+) diff

[PATCH v12 05/10] hw/arm: Add GMAC devices to NPCM7XX SoC

From: Hao Wu Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- hw/arm/npcm7xx.c | 36 ++-- include/hw/arm/npcm7xx.h | 2 ++ 2 files changed, 36 insertions(+), 2

[PATCH v12 02/10] hw/arm: Add PCI mailbox module to Nuvoton SoC

From: Hao Wu This patch wires the PCI mailbox module to Nuvoton SoC. Change-Id: I14c42c628258804030f0583889882842bde0d972 Signed-off-by: Hao Wu Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- docs/system/arm/nuvoton.rst | 2 ++ hw/arm/npcm7xx.c| 2 ++

[PATCH v12 09/10] hw/net: GMAC Tx Implementation

From: Nabih Estefan Diaz - Implementation of Transmit function for packets - Implementation for reading and writing from and to descriptors in memory for Tx NOTE: This function implements the steps detailed in the datasheet for transmitting messages from the GMAC. Added relevant trace-events

[PATCH v12 03/10] hw/misc: Add qtest for NPCM7xx PCI Mailbox

From: Hao Wu This patches adds a qtest for NPCM7XX PCI Mailbox module. It sends read and write requests to the module, and verifies that the module contains the correct data after the requests. Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275 Signed-off-by: Hao Wu Signed-off-by: Nabih

[PATCH v12 07/10] include/hw/net: General GMAC Implementation

From: Nabih Estefan Diaz Implemented GMAC IRQ Handling and added relevant trace-events Change-Id: I7a2d3cd3f493278bcd0cf483233c1e05c37488b7 Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting --- hw/net/npcm_gmac.c | 40 hw/net/trace-events | 1 +

[PATCH v12 00/10] Implementation of NPI Mailbox and GMAC Networking Module

From: Nabih Estefan Diaz [Changes since v11] Was running into error syncing into master. It seemed to be related to a hash problem introduced in patchset 10 (unrelated to the macOS build issue). carried the patches from v9 (before the syncing problem) and added the fixes from patchsets 10 and 11

[PATCH v12 01/10] hw/misc: Add Nuvoton's PCI Mailbox Module

From: Hao Wu The PCI Mailbox Module is a high-bandwidth communcation module between a Nuvoton BMC and CPU. It features 16KB RAM that are both accessible by the BMC and core CPU. and supports interrupt for both sides. This patch implements the BMC side of the PCI mailbox module. Communication

[PATCH v10 8/9] hw/fsi: Added FSI documentation

Documentation for IBM FSI model. Signed-off-by: Cédric Le Goater Signed-off-by: Ninad Palsule --- docs/specs/fsi.rst | 138 +++ docs/specs/index.rst | 1 + 2 files changed, 139 insertions(+) create mode 100644 docs/specs/fsi.rst diff --git

Re: [PATCH v8 00/10] Introduce model for IBM's FSI

Hello Cedric,   include/hw/fsi/aspeed-apb2opb.h |  34 aspeed-apb2opb is a HW logic bridging the FSI world and Aspeed. It doesn't belong to the FSI susbsytem. Since we don't have a directory for platform specific devices, I think the model shoud go under hw/misc/. Moved it to hw/misc

[PATCH v10 9/9] hw/fsi: Update MAINTAINER list

Added maintainer for IBM FSI model Signed-off-by: Cédric Le Goater Signed-off-by: Ninad Palsule --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 00ec1f7eca..79f97a3fb9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3569,6 +3569,14 @@

[PATCH v10 3/9] hw/fsi: Introduce IBM's cfam

This is a part of patchset where IBM's Flexible Service Interface is introduced. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on busses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang

[PATCH v10 1/9] hw/fsi: Introduce IBM's Local bus and scratchpad

This is a part of patchset where IBM's Flexible Service Interface is introduced. The LBUS is modelled to maintain mapped memory for the devices. The memory is mapped after CFAM config, peek table and FSI slave registers. The scratchpad provides a set of non-functional registers. The firmware is

[PATCH v10 5/9] hw/fsi: Aspeed APB2OPB interface, Onchip perif bus

This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The

[PATCH v10 7/9] hw/fsi: Added qtest

Added basic qtests for FSI model. Acked-by: Thomas Huth Signed-off-by: Cédric Le Goater Signed-off-by: Ninad Palsule --- tests/qtest/aspeed-fsi-test.c | 205 ++ tests/qtest/meson.build | 1 + 2 files changed, 206 insertions(+) create mode 100644

[PATCH v10 4/9] hw/fsi: Introduce IBM's FSI master

This is a part of patchset where IBM's Flexible Service Interface is introduced. This commit models the FSI master. CFAM is hanging out of FSI master which is a bus controller. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER

[PATCH v10 0/9] Introduce model for IBM's FSI

Hello, Please review the patch-set version 10. I have incorporated review comments from Cedric. v10: - Moved aspeed-apb2opb to hw/misc directory - Moved scratchpad to lbus files. - Moved fsi-slave to fsi files. - Merged opb changes in the aspeed-apb2opb files - Reduced number of config

[PATCH v10 2/9] hw/fsi: Introduce IBM's FSI Bus and FSI slave

This is a part of patchset where FSI bus is introduced. The FSI bus is a simple bus where FSI master is attached. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear

[PATCH v10 6/9] hw/arm: Hook up FSI module in AST2600

This patchset introduces IBM's Flexible Service Interface(FSI). Time for some fun with inter-processor buses. FSI allows a service processor access to the internal buses of a host POWER processor to perform configuration or debugging. FSI has long existed in POWER processes and so comes with

Re: [RFC/PATCH v1 07/11] gunyah: Specify device-tree location

Srivatsa Vaddagiri writes: > * Philippe Mathieu-Daud? [2024-01-09 14:31:03]: > >> Hi Srivatsa, >> >> On 9/1/24 10:00, Srivatsa Vaddagiri wrote: >> > Specify the location of device-tree and its size, as Gunyah requires the >> > device-tree to be parsed before VM can begin its execution. >> >

[PATCH v3 23/38] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp

Return the x86 condition codes to use after the compare. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc

[PATCH v3 20/38] tcg/arm: Factor tcg_out_cmp() out

Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-12-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 1/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108145244.72421-1-phi...@linaro.org> --- tcg/arm/tcg-target.c.inc | 32

[PATCH v3 24/38] tcg/i386: Support TCG_COND_TST{EQ,NE}

Merge tcg_out_testi into tcg_out_cmp and adjust the two uses. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 95 --- 2 files changed, 60 insertions(+), 37 deletions(-)

[PATCH v3 38/38] tcg/tci: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 +- tcg/tci.c| 14 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 609b2f4e4a..a076f401d2 100644 ---

[PATCH v3 25/38] tcg/i386: Improve TSTNE/TESTEQ vs powers of two

Use "test x,x" when the bit is one of the 4 sign bits. Use "bt imm,x" otherwise. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 6 ++-- tcg/i386/tcg-target-con-str.h | 1 + tcg/i386/tcg-target.c.inc | 54 +++ 3 files changed, 53

[PATCH v3 29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.h | 2 +- tcg/sparc64/tcg-target.c.inc | 16 ++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index

[PATCH v3 19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX

... and the inverse, CBZ for TSTEQ. Suggested-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 8 1 file changed, 8 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 55225313ad..0c98c48f68 100644 ---

[PATCH v3 28/38] tcg/sparc64: Pass TCGCond to tcg_out_cmp

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e16b25e309..10fb8a1a0d 100644 ---

[PATCH v3 27/38] tcg/sparc64: Hoist read of tcg_cond_to_rcond

Use a non-zero value here (an illegal encoding) as a better condition than is_unsigned_cond for when MOVR/BPR is usable. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 25 ++--- 1 file changed, 14 insertions(+), 11

[PATCH v3 37/38] tcg/s390x: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 139 + 2 files changed, 97 insertions(+), 44 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 53bed8c8d2..ae448c3a3a 100644

[PATCH v3 34/38] tcg/ppc: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.c.inc | 122 --- 2 files changed, 115 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 60ce49e672..04a7aba4d3 100644 ---

[PATCH v3 35/38] tcg/s390x: Split constraint A into J+U

Signed 33-bit == signed 32-bit + unsigned 32-bit. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 8 tcg/s390x/tcg-target-con-str.h | 2 +- tcg/s390x/tcg-target.c.inc | 36 +- 3 files changed, 23 insertions(+), 23 deletions(-)

[PATCH v3 15/38] target/s390x: Improve general case of disas_jcc

Avoid code duplication by handling 7 of the 14 cases by inverting the test for the other 7 cases. Use TCG_COND_TSTNE for cc in {1,3}. Use (cc - 1) <= 1 for cc in {1,2}. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 82 +--- 1 file changed,

[PATCH v3 17/38] tcg/aarch64: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 5 +-- tcg/aarch64/tcg-target-con-str.h | 1 + tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 56 ++-- 4 files changed, 44 insertions(+), 20 deletions(-) diff

[PATCH v3 26/38] tcg/i386: Use TEST r,r to test 8/16/32 bits

From: Paolo Bonzini Just like when testing against the sign bits, TEST r,r can be used when the immediate is 0xff, 0xff00, 0x, 0x. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 17 + 1

[PATCH v3 36/38] tcg/s390x: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 6 +-- tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.c.inc | 72 +- 3 files changed, 58 insertions(+), 21

[PATCH v3 08/38] target/alpha: Pass immediate value to gen_bcond_internal()

Simplify gen_bcond() by passing an immediate value. Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-33-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 1/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108205247.83234-1-phi...@linaro.org> ---

[PATCH v3 33/38] tcg/ppc: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. We can't yet remove the fallback to load constants into a scratch because of tcg_out_cmp2, but that path should not be as frequent. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 5 ++--

[PATCH v3 18/38] tcg/aarch64: Generate TBZ, TBNZ

Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 100 --- 1 file changed, 81 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc

[PATCH v3 30/38] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc

Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 28 +--- 1 file changed, 17 insertions(+),

[PATCH v3 22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov

Hoist the tcg_cond_to_jcc index outside the function. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc

[PATCH v3 14/38] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}

These are all test-and-compare type instructions. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 62ab2be8b1..ae4e7b27ec

[PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-12-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108145244.72421-2-phi...@linaro.org> --- tcg/arm/tcg-target.h | 2 +-

[PATCH v3 32/38] tcg/ppc: Tidy up tcg_target_const_match

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b9323baa86..26e0bc31d7 100644 ---

[PATCH v3 11/38] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 49 +++- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c7daf46de7..c68c2bcd21

[PATCH v3 10/38] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 49e6a7b62d..c7daf46de7 100644 --- a/target/alpha/translate.c

[PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel

Using cr0 means we could choose to use rc=1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 68 1 file changed, 34 insertions(+), 34 deletions(-) diff --git

[PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 74 ++--- 1 file changed, 33 insertions(+), 41 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..f30b92f2d4 100644 --- a/target/m68k/translate.c +++

[PATCH v3 02/38] tcg: Introduce TCG_TARGET_HAS_tst

Define as 0 for all tcg backends. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h| 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h| 2 ++ tcg/ppc/tcg-target.h | 2 ++

[PATCH v3 16/38] tcg: Add TCGConst argument to tcg_target_const_match

Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 34 ++-- tcg/aarch64/tcg-target.c.inc | 3 ++-

[PATCH v3 05/38] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2

Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 107 ++--- 1 file changed, 57 insertions(+), 50

[PATCH v3 09/38] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}

Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-33-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108205247.83234-2-phi...@linaro.org> --- target/alpha/translate.c | 20 ++-- 1

[PATCH v3 13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..b96633dde1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -506,6

[PATCH v3 03/38] tcg/optimize: Split out arg_is_const_val

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 38 +++--- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f2d01654c5..73019b9996 100644 --- a/tcg/optimize.c +++

[PATCH v3 06/38] tcg/optimize: Handle TCG_COND_TST{EQ,NE}

Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PATCH v3 01/38] tcg: Introduce TCG_COND_TST{EQ,NE}

Add the enumerators, adjust the helpers to match, and dump. Not supported anywhere else just yet. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 2 ++ include/tcg/tcg-cond.h | 74 ++ tcg/tcg.c

[PATCH v3 07/38] tcg/optimize: Lower TCG_COND_TST{EQ, NE} if unsupported

After having performed other simplifications, lower any remaining test comparisons with AND. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 2 ++ tcg/optimize.c | 60 +++--- tcg/tcg.c | 2 +- 3 files changed, 55 insertions(+), 9

[PATCH v3 00/38] tcg: Introduce TCG_COND_TST{EQ,NE}

Expose a pair of comparison operators that map to the "test" comparison that is available on many architectures. Changes for v3: * Make support for TCG_COND_TST* optional (paolo) * Drop riscv, loongarch64 and (unposted) mips backend changes. * Incorporate Paolo's tcg/i386 TEST improvements

[PATCH v3 04/38] tcg/optimize: Split out do_constant_folding_cond1

Handle modifications to the arguments and condition in a single place. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 57 -- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/tcg/optimize.c

Re: [PATCH v3 07/33] linux-user/arm: Remove qemu_host_page_size from init_guest_commpage

On 1/8/24 20:38, Pierrick Bouvier wrote: On 1/2/24 05:57, Richard Henderson wrote: Use qemu_real_host_page_size. If the commpage is not within reserved_va, use MAP_FIXED_NOREPLACE. Signed-off-by: Richard Henderson ---   linux-user/elfload.c | 13 -   1 file changed, 8

[PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates

From: Paolo Bonzini In the case where OR or XOR has an 8-bit immediate between 128 and 255, we can operate on a low-byte register and shorten the output by two or three bytes (two if a prefix byte is needed for REX.B). Signed-off-by: Paolo Bonzini Message-Id:

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