From: Paolo Bonzini
Extend the existing conditional that generates INC/DEC, to also swap an
ADD for a SUB and vice versa when the immediate is 128. This facilitates
using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.
Signed-off-by: Paolo Bonzini
Message-Id: <20231228120514.70205-1-pbonz...@redhat.
The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:
Merge tag 'pull-riscv-to-apply-20240110' of
https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tag
From: Natanael Copa
Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers
instead of the GNU specific PPC_FEATURE2_HAS_ISEL and
PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861
Sig
LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.
This requires new support in process_op_defs and tcg_reg_alloc_op.
Cc: qemu-sta...@nongnu.org
Fixes: 526cd4ec01f ("tcg
+cminyard
Accidentally typed Corey's email address wrong in the initial send, oops.
On Wed, Jan 10, 2024 at 1:26 PM Joe Komlodi wrote:
>
> Hi all,
>
> This series adds some resets for SMBus and for the I2C core. Along with
> it, we make SMBus slave error printing a little more helpful.
>
> The
When a reset happens, both the SMBusDevice and PCA954x class do their
variable resetting on an enter reset. Because of this, only the PCA954x
has its reset called, which can leave the SMBusDevice in a bad state if
it was in the middle of a transaction.
To fix this we add parent reset functions for
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
in
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 30 +-
include/hw/i2c/i2c.h | 6 +-
2 files changed, 30 insertions(
Hi all,
This series adds some resets for SMBus and for the I2C core. Along with
it, we make SMBus slave error printing a little more helpful.
These reset issues were very infrequent, they would maybe occur in 1 out
of hundreds of resets in our testing, but the way they happen is pretty
straightfo
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..e24a1ef472 100644
--- a
On 1/10/24 1:30 PM, Cédric Le Goater wrote:
> On 9/12/23 13:41, Thomas Huth wrote:
>> From: Janosch Frank
>>
>> Bound APQNs have to be reset before tearing down the secure config via
>> s390_machine_unprotect(). Otherwise the Ultravisor will return a error
>> code.
>>
>> So let's do a subsystem_re
On Wed, Nov 22, 2023, 9:02 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Differentiate between "actively in the process of checking" and
> > "checking has completed". This allows us to clean up the types of some
> > internal fields such as QAPISchemaObjectType's members field which
> > c
Reorganize a bit by first setting properties which are not
dependent of CPU features (and can not fail).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/armv7m.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 8900730e53..b752049add 10
The "tag-memory" property is added to ARMCPU when the
A64_MTE bit is set in the feature ID register. Rather
than checking whether the QOM property is present, directly
check the feature bit.
Since when ARM_FEATURE_AARCH64 is disabled the isar_aa64_mte
register is invalid, also check for it (see th
First, the "kvm-no-adjvtime" and "kvm-steal-time" are only
available when KVM is available, so guard this block within
a 'kvm_enabled()' check. Since the "kvm-steal-time" property
is always available under KVM, directly set it.
Then, the "kvm-no-adjvtime" property is added to ARMCPU when
the ARM_F
ARMV7M container can only accept M-profile CPU types.
Check requested type is valid once to allow further simplifications.
Suggested-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/armv7m.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7
The "aarch64" property is added to ARMCPU when the
ARM_FEATURE_AARCH64 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 2 +-
1 file changed, 1 in
The "reset-cbar" property is added to ARMCPU when the
ARM_FEATURE_CBAR[_RO] features are available. Rather than
checking whether the QOM property is present, directly
check the features.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/highbank.c | 3 ++-
hw/arm/
The "pmu" property is added to ARMCPU when the
ARM_FEATURE_PMU feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 2 +-
1 file changed, 1 insertion(
The "pmsav7-dregion" property is added to ARMCPU when the
ARM_FEATURE_V7 feature is available. Rather than checking
whether the QOM property is present, directly check the
feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/armv7m.c | 4 ++--
1 file changed
The "has_el3" property is added to ARMCPU when the
ARM_FEATURE_EL3 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c | 4 ++--
hw/arm/integr
The "has_el2" property is added to ARMCPU when the
ARM_FEATURE_EL2 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/vexpress.c | 3 ++-
hw/arm/virt.c
All CPUs implementing ARM_FEATURE_M have the 'init-nsvtor' property.
Since setting the property can not fail, replace
object_property_set_uint(..., "init-nsvtor", ..., &error_abort);
by:
qdev_prop_set_uint32(..., "init-nsvtor", ...).
which is a one-to-one replacement.
Suggested-by: Peter
The "dsp" property is added to ARMCPU when the ARM_FEATURE_THUMB_DSP
feature is available. Rather than checking whether the QOM property
is present, directly check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/armv7m.c | 2 +-
1 file changed, 1 in
We are going to cast s->cpu as DeviceState multiple times.
Add a local 'cpudev' variable to simplify code review, having
a single DEVICE(s->cpu) conversion.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/armv7m.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/arm
Since v2 [2]:
- Dropped "Simplify checking A64_MTE bit in FEATURE_ID register"
- Correct object_property_get_bool() uses
- Update ARM_FEATURE_AARCH64 && aa64_mte
Since RFC [1]:
- Split one patch per feature
- Addressed Peter's review comments
[1] https://lore.kernel.org/qemu-devel/20231214171447.
Both "idau" and "init-svtor" properties are added to ARMCPU
when the ARM_FEATURE_M_SECURITY feature is available. Rather
than checking whether the QOM properties are present, directly
check the feature.
Since we are sure the "init-svtor" is present, the
object_property_set_uint() can't fail.
Inste
On Thu, Nov 23, 2023, 8:03 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Wed, Nov 22, 2023 at 7:59 AM Markus Armbruster
> wrote:
> >>
> >> John Snow writes:
> >>
> >> > There's more conditionals in here than we can reasonably pack into a
> >> > terse little statement, so break it ap
Himanshu,
We spoke offline but let's make everyone aware:
- 'sdtrig' should be marked with 'x-' and be an experimental extension since
the spec isn't yet frozen;
- Alvin sent a patch to the ML adding the 'mcontext' CSR for 'sdtrig' some time
ago:
"[PATCH v2] target/riscv: Implement optional CS
On 1/10/24 13:39, Rob Bradford wrote:
Add requirement that 'A' is enabled for all atomic instructions that
lack the check. This makes the 64-bit versions consistent with the
32-bit versions in the same file.
Signed-off-by: Rob Bradford
---
Reviewed-by: Daniel Henrique Barboza
target/r
Rob,
Given that you'll need to resend the patches due to the conflict in patch 2,
I think it would be nice to mention in this commit message that we're ok with
enabling RVB in the 'max' CPU, even though RVB per se is experimental, because
it's just an alias for extensions that the CPU already use
On 1/9/24 14:07, Rob Bradford wrote:
Signed-off-by: Rob Bradford
---
target/riscv/tcg/tcg-cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f10871d352..9705daec93 100644
--- a/target/riscv/tcg/tcg-cpu.c
On 9/12/23 13:41, Thomas Huth wrote:
From: Janosch Frank
Bound APQNs have to be reset before tearing down the secure config via
s390_machine_unprotect(). Otherwise the Ultravisor will return a error
code.
So let's do a subsystem_reset() which includes a AP reset before the
unprotect call. We'l
On 1/9/24 14:07, Rob Bradford wrote:
If the B extension is enabled warn if the user has disabled any of the
required extensions that are part of the 'B' extension. Conversely
enable the extensions that make up the 'B' extension if it is enabled.
Signed-off-by: Rob Bradford
---
This patch d
On 1/9/24 14:07, Rob Bradford wrote:
Add the infrastructure for the 'B' extension which is the union of the
Zba, Zbb and Zbs instructions.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu.h | 1 +
target/riscv/tcg/tcg-cpu.c | 1 +
3 files ch
On 1/10/2024 2:18 AM, Peter Xu wrote:
> On Wed, Dec 13, 2023 at 10:11:32AM -0800, Steve Sistare wrote:
>> After calling notifiers, check if an error has been reported via
>> migrate_set_error, and halt the migration.
>>
>> None of the notifiers call migrate_set_error at this time, so no
>> function
On 1/10/2024 2:09 AM, Peter Xu wrote:
> On Wed, Dec 13, 2023 at 10:11:31AM -0800, Steve Sistare wrote:
>> The existing notifiers should only apply to normal mode.
>>
>> No functional change.
>
> Instead of adding such check in every notifier, why not make CPR a separate
> list of notifiers? Just
On Tue, Jan 09, 2024 at 05:40:26PM +, Jonathan Cameron wrote:
> On Fri, 22 Dec 2023 18:00:48 +0900
> Hyeonggon Yoo <42.hye...@gmail.com> wrote:
>
> > Fix build errors in cxl_type3_stubs.c due to a the incorrect definition
> > of the qmp_cxl_{add,release}_dynamic_capacity functions.
> >
> > Si
Am 10.01.2024 um 16:21 hat Ari Sundholm geschrieben:
> On 1/10/24 15:39, Kevin Wolf wrote:
> > Am 09.01.2024 um 19:46 hat meg...@gmx.com geschrieben:
> > > From: Ari Sundholm
> > >
> > > There is a bug in the blklogwrites driver pertaining to logging "write
> > > zeroes" operations, causing log c
On 10/01/2024 00.22, Ilya Leoshkevich wrote:
Add a small test to prevent regressions. Userspace runs in primary
mode, so LAE should always set the access register to 0.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/lae.c | 25 ++
Add requirement that 'A' is enabled for all atomic instructions that
lack the check. This makes the 64-bit versions consistent with the
32-bit versions in the same file.
Signed-off-by: Rob Bradford
---
target/riscv/insn_trans/trans_rva.c.inc | 11 +++
1 file changed, 11 insertions(+)
di
ilable in the Git repository at:
>
> https://github.com/mcayland/qemu.git tags/qemu-sparc-20240110
>
> for you to fetch changes up to 995d8348eb3d8ddf24882ed384a5c50eaf3aeae9:
>
> util/fifo8: Introduce fifo8_peek_buf() (2024-01-10 06:58:50 +)
>
> --
ilable in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240110
>
> for you to fetch changes up to 71b76da33a1558bcd59100188f5753737ef6fa21:
>
> target/riscv: Ensure mideleg is set
On Wed, Jan 10, 2024 at 10:55:11AM +, Alex Bennée wrote:
> Alex Bennée writes:
>
> > A lot of our vhost-user stubs are large chunks of boilerplate that do
> > (mostly) the same thing. This series continues the cleanups by
> > splitting the vhost-user-base and vhost-user-generic implementation
Hi Jason,
On 10/1/24 16:24, Jason Thorpe wrote:
Having recently written a driver for the Goldfish TTY for NetBSD, I found it a
bit odd (and a little annoying) that the device has a PUT_CHAR register but not
a GET_CHAR register, something particularly useful for early-console or
in-kernel debu
Hi Srivatsa,
On 9/1/24 10:00, Srivatsa Vaddagiri wrote:
Complete the cpu execution loop. At this time, we recognize exits
associated with only MMIO access. Future patches will add support for
recognizing other exit reasons, such as PSCI calls made by guest.
Signed-off-by: Srivatsa Vaddagiri
--
Hi Srivatsa,
On 9/1/24 10:00, Srivatsa Vaddagiri wrote:
Complete the cpu execution loop. At this time, we recognize exits
associated with only MMIO access. Future patches will add support for
recognizing other exit reasons, such as PSCI calls made by guest.
Signed-off-by: Srivatsa Vaddagiri
--
On 10/1/24 15:29, Thomas Huth wrote:
It's a common scenario to copy guest images from one host to another
to run the guest on the other machine. This (of course) does not work
with "secure exection" guests since they are encrypted with one certain
"execution"
host key. However, if you still (
Having recently written a driver for the Goldfish TTY for NetBSD, I found it a
bit odd (and a little annoying) that the device has a PUT_CHAR register but not
a GET_CHAR register, something particularly useful for early-console or
in-kernel debugger use. As it stands, to get a single character
On 1/10/24 03:37, Peter Xu wrote:
On Tue, Jan 09, 2024 at 02:21:26PM +0100, Cédric Le Goater wrote:
A few things I'd like to mention alongside, because it's documentation
relevant too, and I'd like to collect if there's any comment.
I just mostly rewrote two wiki pages completely:
https:
Hi, Kevin!
On 1/10/24 15:39, Kevin Wolf wrote:
Am 09.01.2024 um 19:46 hat meg...@gmx.com geschrieben:
From: Ari Sundholm
There is a bug in the blklogwrites driver pertaining to logging "write
zeroes" operations, causing log corruption. This can be easily observed
by setting detect-zeroes to s
Peter Xu writes:
> On Tue, Jan 09, 2024 at 11:46:32AM -0300, Fabiano Rosas wrote:
>> Hm, it would be better to avoid the extra maintenance task at the start
>> of every release, no? It also blocks us from doing n-2 even
>> experimentally.
>
> See my other reply, on whether we can use "n-1" for mi
Hello,
I have faced an issue in using serial ports when I need to skip a couple of
ports in the CLI.
For example the ARM machine netduinoplus2 supports up to 7 UARTS.
Following case works (the first UART is used to send data in the firmware):
qemu-system-arm -machine netduinoplus2 -nographic -ser
ping !
please review this patch :
https://patchew.org/QEMU/20231227071540.4035803-1-peng...@smartx.com/
thanks
On Fri, Jan 5, 2024 at 9:47 PM Philippe Mathieu-Daudé
wrote:
> On 27/12/23 08:15, peng...@smartx.com wrote:
> > From: Peng Ji
> >
> > When a volume has more than one disk, all disks
On Tue, 9 Jan 2024 15:55:46 -0800
Hao Xiang wrote:
> On Tue, Jan 9, 2024 at 2:13 PM Gregory Price
> wrote:
> >
> > On Tue, Jan 09, 2024 at 01:27:28PM -0800, Hao Xiang wrote:
> > > On Tue, Jan 9, 2024 at 11:58 AM Gregory Price
> > > wrote:
> > > >
> > > > If you drop this line:
> > > >
> >
It's a common scenario to copy guest images from one host to another
to run the guest on the other machine. This (of course) does not work
with "secure exection" guests since they are encrypted with one certain
host key. However, if you still (accidentally) do it, you only get a
very user-unfriendl
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Peter Xu writes:
>>
>>> On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
Hi Fabiano,
On 9/1/24 21:21, Fabiano Rosas wrote:
> Cédric Le Goater writes:
>
> > On 1/9/24 18:40, Fabiano Ros
Am 09.01.2024 um 19:46 hat meg...@gmx.com geschrieben:
> From: Ari Sundholm
>
> There is a bug in the blklogwrites driver pertaining to logging "write
> zeroes" operations, causing log corruption. This can be easily observed
> by setting detect-zeroes to something other than "off" for the driver.
Markus Armbruster writes:
> Peter Xu writes:
>
>> On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
>>> Hi Fabiano,
>>>
>>> On 9/1/24 21:21, Fabiano Rosas wrote:
>>> > Cédric Le Goater writes:
>>> >
>>> > > On 1/9/24 18:40, Fabiano Rosas wrote:
>>> > > > Cédric Le Goater
Le 21/12/2023 à 09:09, Akihiko Odaki a écrit :
On 2023/12/19 16:53, Huang Rui wrote:
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable virglrenderer 0.10 interface. Only enabled when available and
via the blob config. E.g. -device virtio
Le 09/01/2024 à 19:45, Samuel Tardieu a écrit :
Signed-off-by: Samuel Tardieu
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
---
hw/timer/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 3eccef838
On 09/01/2024 17.51, Cédric Le Goater wrote:
On 1/9/24 15:30, Thomas Huth wrote:
It's a common scenario to copy guest images from one host to another
to run the guest on the other machine. This (of course) does not work
with "secure exection" guests since they are encrypted with one certain
ho
Hi
On Wed, Jan 10, 2024 at 3:16 PM Daniel P. Berrangé wrote:
>
> The chardev socket backend will unref the QIOChannel object while
> it is still potentially open. When using TLS there could be a
> pending TLS handshake taking place. If the channel is left open
> then when the TLS handshake callba
On 10/1/24 12:16, Daniel P. Berrangé wrote:
Signed-off-by: Daniel P. Berrangé
---
io/channel-tls.c | 1 +
io/trace-events | 1 +
2 files changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Please use comma instead of slash. cs->nr_cores/cs->nr_threads looks
like one variable.
Since the names of cs->n
On Wed, Jan 10, 2024 at 10:25:37AM +, Conor Dooley wrote:
> From: Conor Dooley
>
> A few months ago I submitted a patch to various lists, deprecating
> "riscv,isa" with a lengthy commit message [0] that is now commit
> aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
> ke
On Wed, Jan 10, 2024 at 10:25:36AM +, Conor Dooley wrote:
> From: Conor Dooley
>
> A cpu may not have the same xlen as the compile time target, and
> misa_mxl_max is the source of truth for what the hart supports.
>
> Reported-by: Andrew Jones
> Link:
> https://lore.kernel.org/qemu-riscv/2
On Wed, 10 Jan 2024 at 06:01, Richard Henderson
wrote:
>
> On 1/10/24 05:09, Philippe Mathieu-Daudé wrote:
> > cpu_isar_feature(aa64_mte, cpu) is testing a AArch64-only ID
> > register. The ARM_FEATURE_AARCH64 check is redundant.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
> > target/
> Anyone has suggestion?
>
> When the host kernel before this commit 2e8cd7a3b828 ("kvm: x86: limit the
> maximum number of vPMU
> fixed counters to 3") on icelake microarchitecture and newer, execute cpuid
> in the Guest:
>
> Architecture Performance Monitoring Features (0xa/edx):
> number o
The chardev socket backend will unref the QIOChannel object while
it is still potentially open. When using TLS there could be a
pending TLS handshake taking place. If the channel is left open
then when the TLS handshake callback runs, it can end up accessing
free'd memory in the tcp_chr_tls_handsha
Signed-off-by: Daniel P. Berrangé
---
io/channel-tls.c | 1 +
io/trace-events | 1 +
2 files changed, 2 insertions(+)
diff --git a/io/channel-tls.c b/io/channel-tls.c
index 58fe1aceee..1d9c9c72bf 100644
--- a/io/channel-tls.c
+++ b/io/channel-tls.c
@@ -381,6 +381,7 @@ static int qio_channel_tls
Alex Bennée writes:
> A lot of our vhost-user stubs are large chunks of boilerplate that do
> (mostly) the same thing. This series continues the cleanups by
> splitting the vhost-user-base and vhost-user-generic implementations.
> After adding a new vq_size property the rng, gpio and i2c vhost-us
On 09/01/2024 21.58, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 1/5/24 19:04, Fabiano Rosas wrote:
The migration tests have support for being passed two QEMU binaries to
test migration compatibility.
Add a CI job that builds the lastest release of QEMU and another job
that uses that ve
From: Conor Dooley
A cpu may not have the same xlen as the compile time target, and
misa_mxl_max is the source of truth for what the hart supports.
Reported-by: Andrew Jones
Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/
Signed-off-by: Conor Dooley
---
Perhaps
From: Conor Dooley
Making it a series to keep the standalone change to riscv_isa_string()
that Drew reported separate.
Changes in v3:
- g_free() isa_extensions too
- use misa_mxl_max rather than the compile target for the base isa
- add a new patch changing riscv_isa_string() to do the same
- dr
From: Conor Dooley
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set o
Anyone has suggestion?
When the host kernel before this commit 2e8cd7a3b828 ("kvm: x86: limit the
maximum number of vPMU
fixed counters to 3") on icelake microarchitecture and newer, execute cpuid in
the Guest:
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters
在 2024/1/10 下午5:42, Philippe Mathieu-Daudé 写道:
Hi Song,
On 10/1/24 03:46, gaosong wrote:
在 2024/1/5 下午3:57, Tianrui Zhao 写道:
This series add loongarch kvm support, mainly implement
some interfaces used by kvm, such as kvm_arch_get/set_regs,
kvm_arch_handle_exit, kvm_loongarch_set_interrupt,
From: Abhiram Tilak
When running the command `qemu-img snapshot -l SNAPSHOT` the output of
VM_CLOCK (measures the offset between host and VM clock) cannot to
accommodate values in the order of thousands (4-digit).
This line [1] hints on the problem. Additionally, the column width for
the VM_CLOC
Hi Song,
On 10/1/24 03:46, gaosong wrote:
在 2024/1/5 下午3:57, Tianrui Zhao 写道:
This series add loongarch kvm support, mainly implement
some interfaces used by kvm, such as kvm_arch_get/set_regs,
kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc.
Tianrui Zhao (9):
linux-headers: Syn
From: Tianrui Zhao
In preparation of supporting KVM in the next commit.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn>
[PMD: Split from bigger patch, part 1]
Signed-off-by: Philippe Mathieu-Daudé
---
From: Tianrui Zhao
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn>
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using
> -Original Message-
> From: JeeHeng Sia
> Sent: Wednesday, January 10, 2024 4:02 PM
> To: Daniel Henrique Barboza ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; qemu-
> ri...@nongnu.org
> Cc: m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com;
> peter.mayd...@linaro.org; shanno
Hi Tianrui,
On 5/1/24 08:58, Tianrui Zhao wrote:
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
---
target/loongarch/cpu.c
From: Heinrich Schuchardt
Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI
table generation. Add it to the documentation.
Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI")
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Daniel Henrique Barboza
Reviewed-b
From: Daniel Henrique Barboza
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profile support requires tne
From: Daniel Henrique Barboza
Our current logic in get/setters of MISA and multi-letter extensions
works because we have only 2 CPU types, generic and vendor, and by using
"!generic" we're implying that we're talking about vendor CPUs. When adding
a third CPU type this logic will break so let's h
From: Daniel Henrique Barboza
This CPU was suggested by Alistair [1] and others during the profile
design discussions. It consists of the bare 'rv64i' CPU with rva22u64
enabled by default, like an alias of '-cpu rv64i,rva22u64=true'.
Users now have an even easier way of consuming this user-mode
On 10.01.24 00:22, Ilya Leoshkevich wrote:
LAE should set the access register corresponding to the first operand,
instead, it always modifies access register 1.
Co-developed-by: Ido Plat
Cc: qemu-sta...@nongnu.org
Fixes: a1c7610a6879 ("target-s390x: implement LAY and LAEY instructions")
Signed-
On Mon, Nov 27, 2023 at 05:25:44PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> Introduce basic pwritev/preadv support in the generic channel layer.
> Specific implementation will follow for the file channel as this is
> required in order to support migration streams with fixed locatio
From: Daniel Henrique Barboza
The TCG emulation implements all the extensions described in the
RVA22U64 profile, both mandatory and optional. The mandatory extensions
will be enabled via the profile flag. We'll leave the optional
extensions to be enabled by hand.
Given that this is the first pro
From: Daniel Henrique Barboza
KVM does not have the means to support enabling the rva22u64 profile.
The main reasons are:
- we're missing support for some mandatory rva22u64 extensions in the
KVM module;
- we can't make promises about enabling a profile since it all depends
on host support
From: Sunil V L
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
M
From: Ivan Klokov
This patch changes behavior on writing RW=01 to pmpcfg with MML=0.
RWX filed is form of collective WARL with the combination of
pmpcfg.RW=01 remains reserved for future standard use.
According to definition of WARL writing the CSR has no other side
effect. But current implement
On Mon, Nov 27, 2023 at 05:25:46PM -0300, Fabiano Rosas wrote:
> Make sure the data is flushed to disk before closing file
> channels. This will ensure data is on disk at the end of a migration
> to file.
>
> Signed-off-by: Fabiano Rosas
> ---
> io/channel-file.c | 5 +
> 1 file changed, 5 i
From: Daniel Henrique Barboza
Add a new profile CPU 'rva22s64' to work as an alias of
-cpu rv64i,rva22s64
Like the existing rva22u64 CPU already does with the RVA22U64 profile.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-ID: <202312
On Mon, Nov 27, 2023 at 05:25:45PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> The upcoming 'fixed-ram' feature will require qemu to write data to
> (and restore from) specific offsets of the migration file.
>
> Add a minimal implementation of pwritev/preadv and expose them via the
>
From: Sunil V L
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
R
From: Daniel Henrique Barboza
The RVA22S64 profile consists of the following:
- all mandatory extensions of RVA22U64;
- priv spec v1.12.0;
- satp mode sv39;
- Ssccptr, a cache related named feature that we're assuming always
enable since we don't implement a cache;
- Other named features alrea
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