From: Peter Xu
Now multifd's logic is designed to have no spurious wakeup. I still
remember a talk to Juan and he seems to agree we should drop it now, and if
my memory was right it was there because multifd used to hit that when
still debugging.
Let's drop it and see what can explode; as long
From: Peter Xu
Introduce a helper multifd_send_prepare_header() to setup the header packet
for multifd sender.
It's fine to setup the IOV[0] _before_ send_prepare() because the packet
buffer is already ready, even if the content is to be filled in.
With this helper, we can already slightly
From: Peter Xu
Now with a split SYNC handler, we always have pages->num set for
pending_job==true. Assert it instead.
Signed-off-by: Peter Xu
---
migration/multifd.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/migration/multifd.c b/migration/multifd.c
From: Peter Xu
We've already done that with multifd_flush_after_each_section, for multifd
in general. Drop the stale "TODO-like" comment.
Reviewed-by: Fabiano Rosas
Signed-off-by: Peter Xu
---
migration/multifd.c | 11 ---
1 file changed, 11 deletions(-)
diff --git
From: Peter Xu
Multifd send side has two fields to indicate error quits:
- MultiFDSendParams.quit
- _send_state->exiting
Merge them into the global one. The replacement is done by changing all
p->quit checks into the global var check. The global check doesn't need
any lock.
A few more
From: Peter Xu
This patchset contains quite a few refactorings to current multifd:
- It picked up some patches from an old series of mine [0] (the last
patches were dropped, though; I did the cleanup slightly differently):
I still managed to include one patch to split pending_job,
On Wed, Jan 31, 2024 at 06:13:29PM +0800, Zhao Liu wrote:
> From: Zhao Liu
>
> Hi list,
>
> This is the our v8 patch series, rebased on the master branch at the
> commit 11be70677c70 ("Merge tag 'pull-vfio-20240129' of
> https://github.com/legoater/qemu into staging").
>
> Compared with v7
Hi!
qemu-system-aarch64 -device virtio-vga
this one loads vgabios-virtio.bin. Why?
Does this bios work on aarch64 (or any other non-x86 arch)?
Should there may be some conditional in this and similar places?
The same is true for x86 pxe roms and other x86-only roms.
Thanks,
/mjt
On Wed, Jan 31, 2024 at 11:20:41AM +0800, lixianglai wrote:
> > > In the qemu code, loongarch virt machine does only create a pflash,
> > >
> > > which is used for nvram, and uefi code is loaded by rom.
> > >
> > > In summary, loongarch virt machine can use nvram with the following
> > > command:
Am 29.01.2024 um 17:30 hat Hanna Czenczek geschrieben:
> I don’t like using drain as a form of lock specifically against AioContext
> changes, but maybe Stefan is right, and we should use it in this specific
> case to get just the single problem fixed. (Though it’s not quite trivial
> either.
Hi Eugenio,
Maybe there's some patch missing, but I saw this core dump when x-svq=on
is specified while waiting for the incoming migration on destination host:
(gdb) bt
#0 0x5643b24cc13c in vhost_iova_tree_map_alloc (tree=0x0,
map=map@entry=0x7ffd58c54830) at
On Wed, Jan 31, 2024 at 08:53:49AM +0100, Helge Deller wrote:
> On 1/31/24 01:18, Ilya Leoshkevich wrote:
> > Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the
> > calling thread, and not the entire process. Therefore, implement it
> > using a syscall, and not a libc call.
> >
> >
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than 1
modules.
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology
From: Zhao Liu
Introduce module-id to be consistent with the module-id field in
CpuInstanceProperties.
Following the legacy smp check rules, also add the module_id validity
into x86_cpu_pre_plug().
Tested-by: Yongwei Ma
Co-developed-by: Zhuocheng Ding
Signed-off-by: Zhuocheng Ding
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
Reviewed-by: Yanan Wang
Tested-by: Babu Moger
Tested-by: Yongwei Ma
Acked-by: Michael S. Tsirkin
From: Zhao Liu
For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs
sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits
25:14]) to 0, and this means i-cache and d-cache are shared in the SMT
level.
This is correct if there's single thread per core, but is
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using APIC ID offset/width (like L3
From: Zhao Liu
Add "modules" parameter parsing support in -smp.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
---
Changes since v7:
* New commit to introduce module level in -smp.
---
hw/core/machine-smp.c | 39 +--
From: Zhao Liu
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Since x86 does not yet support the "modules" parameter in "-smp",
X86CPUTopoInfo.modules_per_die is currently always 1.
Therefore, the module level width in APIC ID, which can be calculated by
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
And since with the helper
From: Zhao Liu
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so also update APIC ID parsing
rule to support module level. With this support, the conversions with
module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are
completed.
module_id can be also
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf
with
From: Zhao Liu
Intel CPUs implement module level on hybrid client products (e.g.,
ADL-N, MTL, etc) and E-core server products.
A module contains a set of cores that share certain resources (in
current products, the resource usually includes L2 cache, as well as
module scoped features and MSRs).
From: Zhao Liu
As module-level topology support is added to X86CPU, now we can enable
the support for the modules parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,modules=*,cores=*,threads=*.
Additionally,
From: Zhao Liu
Currently, QEMU checks the specify number of topology domains to detect
if there's extended topology levels (e.g., checking nr_dies).
With this bitmap, the extended CPU topology (the levels other than SMT,
core and package) could be easier to detect without touching the
topology
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores and cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone
to confusion
From: Zhao Liu
Add module-id in CpuInstanceProperties, to locate the CPU with module
level.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
---
Changes since v7:
* New commit to introduce module_id to locate the CPU with module
level.
---
From: Zhao Liu
Hi list,
This is the our v8 patch series, rebased on the master branch at the
commit 11be70677c70 ("Merge tag 'pull-vfio-20240129' of
https://github.com/legoater/qemu into staging").
Compared with v7 [1], v8 mainly has the following changes:
* Introduced smp.modules for x86
From: Zhao Liu
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x8026]) have the different definitions with different
enumeration values.
Though
From: Zhao Liu
Module is a level above the core, thereby supporting numa
configuration on the module level can bring user more numa flexibility.
This is the natural further support for module level.
Add module level support in numa configuration.
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
From: Zhao Liu
In x86, module is the topology level above core, which contains a set
of cores that share certain resources (in current products, the resource
usually includes L2 cache, as well as module scoped features and MSRs).
To build the module level topology for x86 CPUs, introduce module
On 31/01/24 12:28 am, Alex Williamson wrote:
On Tue, 30 Jan 2024 23:32:26 +0530
Vinayak Kale wrote:
Missed adding Michael, Marcel, Alex and Avihai earlier, apologies.
Regards,
Vinayak
On 30/01/24 3:26 pm, Vinayak Kale wrote:
In case of migration, during restore operation, qemu checks
On Mon, Jan 29, 2024 at 09:51:06AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Jan 29, 2024 at 01:41:01AM +, Liu, Yuan1 wrote:
> >> Because this change has an impact on the previous live migration
> >> With IAA Patch, does the submission of the next version needs
> >> to
On Wed, Jan 31, 2024 at 02:54:19PM +0800, Zhao Liu wrote:
> On Wed, Jan 31, 2024 at 10:47:29AM +0530, Ani Sinha wrote:
> > Date: Wed, 31 Jan 2024 10:47:29 +0530
> > From: Ani Sinha
> > Subject: Re: [PATCH v2] pc: q35: Bump max_cpus to 1856 vcpus
> >
> > On Wed, Jan 31, 2024 at 9:27 AM Zhao Liu
This adds a "ncpus" property to the "grlib-irqmp" device to be used later,
this required a little refactoring of how we initialize the device (ie: use
realize instead of init).
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
---
According to the doc (see §4.2.15 in [1]), the reset operation should
not impact %SP.
[1] https://gaisler.com/doc/gr712rc-usermanual.pdf
Signed-off-by: Clément Chigot
---
hw/sparc/leon3.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index
On 26/01/2024 18.25, David Woodhouse wrote:
From: David Woodhouse
The MIPS SIM platform instantiates its NIC only if a corresponding
configuration exists for it. Use qemu_create_nic_device() function for
that.
Signed-off-by: David Woodhouse
---
hw/mips/mipssim.c | 13 +++--
1 file
Now there is an ncpus property, use it in order to deliver the IRQ to
multiple CPU.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
---
hw/intc/grlib_irqmp.c | 41 +--
hw/sparc/leon3.c | 3
This allows to register more than one CPU on the leon3_generic machine.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
---
hw/sparc/leon3.c | 98 ++--
1 file changed, 70 insertions(+), 28 deletions(-)
diff --git a/hw/sparc/leon3.c
V3 modifications
- Patch 3: Fix indentation
- Patch 4: Fix types and improves variable declarations
- Patch 6 (NEW): Remove SP initialization in leon3
- Patch 7: Add assert in leon3_start_cpu
- Patch 8: Improve comment
---
V2 modifications
- Patch1: Add SPDX copyright tags.
- Patch3: Add
This allows the guest program to know its cpu id.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/sparc/helper.c| 16
target/sparc/helper.h| 1 +
target/sparc/translate.c |
This implements the multiprocessor status register in grlib-irqmp and bind
it to a start signal, which will be later wired in leon3-generic to
start a cpu.
The EIRQ and BA bits are not implemented.
Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, §8.3.5.
Co-developed-by: Frederic Konrad
Now that SMP is possible, the asr17 must be checked in the little boot code
or the secondary CPU will reinitialize the Timer and the Uart.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
---
hw/sparc/leon3.c | 22 --
1
CC: Fabien Chouteau
Signed-off-by: Clément Chigot
Reviewed-by: Fabien Chouteau
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index dfaca8323e..f076c97fcb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1708,7 +1708,7 @@ F:
... and move them in their right hardware directory.
Update Copyright and add SPDX-License-Identifier at the same time.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
---
hw/char/grlib_apbuart.c | 6 ++--
On 26/01/2024 18.25, David Woodhouse wrote:
From: David Woodhouse
Signed-off-by: David Woodhouse
---
hw/arm/mps2-tz.c | 8 ++--
hw/arm/msf2-soc.c| 6 +-
hw/arm/musicpal.c| 3 +--
hw/arm/xilinx_zynq.c | 11 ---
hw/arm/xlnx-versal.c | 7 +--
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