Philippe Mathieu-Daudé writes:
> On 6/2/24 06:53, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>>> On Mon, Feb 05, 2024 at 12:18:19PM -0500, Stefan Hajnoczi wrote:
C99 mixed declarations support interleaving of local variable
declarations and code.
The coding
On 06/02/2024 18.12, Peter Maydell wrote:
Currently QEMU will warn if there is a NIC on the board that
is not connected to a backend. By default the '-nic user' will
get used for all NICs, but if you manually connect a specific
NIC to a specific backend, then the other NICs on the board
have no
This option was not documented.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1240
Signed-off-by: Michael Tokarev
---
qemu-nbd.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qemu-nbd.c b/qemu-nbd.c
index bac0b5e3ec..d7b3ccab21 100644
--- a/qemu-nbd.c
+++ b/qemu-nbd.c
@@ -114,6
On 2/6/2024 10:19 PM, Daniel P. Berrangé wrote:
On Tue, Feb 06, 2024 at 03:28:48AM -0500, Xiaoyao Li wrote:
This series is inspired and suggested by Daniel:
https://lore.kernel.org/qemu-devel/zbfoqseuv6_zw...@redhat.com/
Currently, different confidential VMs in different architectures have
On Wed, 7 Feb 2024, Richard Henderson wrote:
> On 2/7/24 06:48, Alexander Monakov wrote:
> > Make buffer_is_zero a 'static inline' function that tests up to three
> > bytes from the buffer before handing off to an unrolled loop. This
> > eliminates call overhead for most non-zero buffers, and
On 2/6/2024 10:16 PM, Daniel P. Berrangé wrote:
On Tue, Feb 06, 2024 at 03:28:50AM -0500, Xiaoyao Li wrote:
Use confidential_guest_kvm_init() instead of calling SEV specific
sev_kvm_init(). As a bouns, it fits to future TDX when TDX implements
its own confidential_guest_support and .kvm_init().
Stefan Hajnoczi writes:
> The aio_co_reschedule_self() API is designed to avoid the race
> condition between scheduling the coroutine in another AioContext and
> yielding.
>
> The QMP dispatch code uses the open-coded version that appears
> susceptible to the race condition at first glance:
>
>
On Wed, Feb 07, 2024 at 07:07:58AM +0100, Markus Armbruster wrote:
> pet...@redhat.com writes:
>
> > From: Peter Xu
> >
> > As reported in Markus's recent enforcement series on qapi doc [1], we
> > accidentally miss one entry for tls-authz. Add it. Then we can drop
> > @MigrateSetParameters
Zhao Liu writes:
> Hi Philippe,
>
> On Wed, Jan 31, 2024 at 05:48:24PM +0100, Philippe Mathieu-Daudé wrote:
>> Date: Wed, 31 Jan 2024 17:48:24 +0100
>> From: Philippe Mathieu-Daudé
>> Subject: Re: [PATCH] hw/intc: Handle the error of
>> IOAPICCommonClass.realize()
>>
>> Hi Zhao,
>>
>> On
On Tue, 6 Feb 2024, Elena Ufimtseva wrote:
> Hello Alexander
>
> On Tue, Feb 6, 2024 at 12:50 PM Alexander Monakov
> wrote:
>
> > Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
> > routines are invoked much more rarely in normal use when most buffers
> > are non-zero.
pet...@redhat.com writes:
> From: Peter Xu
>
> As reported in Markus's recent enforcement series on qapi doc [1], we
> accidentally miss one entry for tls-authz. Add it. Then we can drop
> @MigrateSetParameters from documentation-exceptions safely later.
>
> [1]
On 2/7/24 07:45, Richard Henderson wrote:
On 2/6/24 19:24, Pierrick Bouvier wrote:
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -442,6 +442,13 @@ static TCGOp *append_inline_cb(const struct
qemu_plugin_dyn_cb *cb,
char *ptr = cb->userp;
size_t elem_size = 0;
On 2/7/24 07:42, Richard Henderson wrote:
On 2/6/24 19:24, Pierrick Bouvier wrote:
Instead of working on a fixed memory location, allow to address it based
on cpu_index, an element size and a given offset.
Result address: ptr + offset + cpu_index * element_size.
With this, we can target a
On 31/1/24 11:13, Zhao Liu wrote:
From: Zhao Liu
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x8026]) have the different definitions with different
On 2/7/24 07:21, Richard Henderson wrote:
On 2/6/24 19:24, Pierrick Bouvier wrote:
We introduce a cpu local storage, automatically managed (and extended)
by QEMU itself. Plugin allocate a scoreboard, and don't have to deal
with how many cpus are launched.
This API will be used by new inline
On 31/1/24 11:13, Zhao Liu wrote:
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores and cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of
On 6/2/24 06:53, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Mon, Feb 05, 2024 at 12:18:19PM -0500, Stefan Hajnoczi wrote:
C99 mixed declarations support interleaving of local variable
declarations and code.
The coding style "generally" forbids C99 mixed declarations with some
This patch adds loopback for sent characters as well as
modem-control signals.
Loopback of send and modem-control is often used for uart
self tests in real hardware but missing from current pl011
model, resulting in self-test failures when running in QEMU.
Signed-off-by: Tong Ho
Signed-off-by:
This changes the ohci validation to not assert if invalid
data is fed to the ohci controller. The poc suggested in
https://bugs.launchpad.net/qemu/+bug/1907042
and then migrated to bug #303 does the following to
feed it a SETUP pid and EndPt of 1:
uint32_t MaxPacket = 64;
uint32_t
On Tue, Feb 06, 2024 at 11:19:06PM +, Hao Xiang wrote:
> This implements the zero page detection and handling on the multifd
> threads.
>
> Signed-off-by: Hao Xiang
> ---
> migration/multifd.c | 62 +
> migration/multifd.h | 5
> 2 files
On Wed, Feb 07, 2024 at 12:13:10PM +0800, Peter Xu wrote:
> On Tue, Feb 06, 2024 at 11:19:04PM +, Hao Xiang wrote:
> > This change extends the MigrationStatus interface to track zero pages
> > and zero bytes counter.
> >
> > Signed-off-by: Hao Xiang
>
> Reviewed-by: Peter Xu
I'll need to
On Tue, Feb 06, 2024 at 11:19:05PM +, Hao Xiang wrote:
> diff --git a/migration/multifd.c b/migration/multifd.c
> index 25cbc6dc6b..a20d0ed10e 100644
> --- a/migration/multifd.c
> +++ b/migration/multifd.c
> @@ -264,6 +264,7 @@ static void multifd_send_fill_packet(MultiFDSendParams *p)
>
On Tue, Feb 06, 2024 at 11:19:04PM +, Hao Xiang wrote:
> This change extends the MigrationStatus interface to track zero pages
> and zero bytes counter.
>
> Signed-off-by: Hao Xiang
Reviewed-by: Peter Xu
When post anything QAPI relevant, please always remember to copy QAPI
maintainers
On Tue, Feb 06, 2024 at 11:19:03PM +, Hao Xiang wrote:
> diff --git a/qapi/migration.json b/qapi/migration.json
> index 819708321d..ff033a0344 100644
> --- a/qapi/migration.json
> +++ b/qapi/migration.json
> @@ -874,6 +874,11 @@
> # @mode: Migration mode. See description in @MigMode. Default
On 2/6/24 19:24, Pierrick Bouvier wrote:
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -442,6 +442,13 @@ static TCGOp *append_inline_cb(const struct
qemu_plugin_dyn_cb *cb,
char *ptr = cb->userp;
size_t elem_size = 0;
size_t offset = 0;
+if (!ptr) {
+
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, February 7, 2024 1:00 AM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee
> Subject: Re: [PATCH v0 1/2] aspeed: support uart
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, February 7, 2024 12:48 AM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee
> Subject: Re: [v0 0/2] uart base and hardcode boot
On 2/6/24 19:24, Pierrick Bouvier wrote:
Instead of working on a fixed memory location, allow to address it based
on cpu_index, an element size and a given offset.
Result address: ptr + offset + cpu_index * element_size.
With this, we can target a member in a struct array from a base pointer.
On Tue, Feb 06, 2024 at 11:19:02PM +, Hao Xiang wrote:
> This patchset is based on Juan Quintela's old series here
> https://lore.kernel.org/all/20220802063907.18882-1-quint...@redhat.com/
>
> In the multifd live migration model, there is a single migration main
> thread scanning the page
You are right. I'll send patch v2 shortly. Thank you for the reply.
Richard Henderson 於 2024年2月7日 週三 上午4:24寫道：
> On 2/6/24 23:18, Jason Chien wrote:
> > The original implementation sets $pc to the address read from the jump
> > vector table first and links $ra with the address of the next
From: Peter Xu
As reported in Markus's recent enforcement series on qapi doc [1], we
accidentally miss one entry for tls-authz. Add it. Then we can drop
@MigrateSetParameters from documentation-exceptions safely later.
[1] https://lore.kernel.org/r/20240205074709.3613229-1-arm...@redhat.com
On 2/6/24 19:24, Pierrick Bouvier wrote:
We introduce a cpu local storage, automatically managed (and extended)
by QEMU itself. Plugin allocate a scoreboard, and don't have to deal
with how many cpus are launched.
This API will be used by new inline functions but callbacks can benefit
from this
On Mon, Feb 05, 2024 at 08:46:54AM +0100, Markus Armbruster wrote:
> qapi/migration.json
> MigrateSetParameters 1
It's tls-authz. I'll send a patch for this one.
Thanks,
--
Peter Xu
On Tue, Feb 6, 2024 at 4:31 PM Stefano Garzarella wrote:
>
> On Tue, Feb 06, 2024 at 10:47:40AM +0800, Jason Wang wrote:
> >On Mon, Feb 5, 2024 at 6:51 PM Stefano Garzarella
> >wrote:
> >>
> >> On Fri, Feb 02, 2024 at 02:25:21PM +0100, Kevin Wolf wrote:
> >> >VDUSE requires that virtqueues are
On 2/6/24 19:24, Pierrick Bouvier wrote:
This ensures we run during a cpu_exec, which allows to call start/end
exclusive from this init hook (needed for new scoreboard API introduced
later).
async work is run before any tb is translated/executed, so we can
guarantee plugin init will be called
On 2/6/24 19:24, Pierrick Bouvier wrote:
We found that vcpu_init_hook was called*after* idle callback.
vcpu_init is called from cpu_realize_fn, while idle/resume cb are called
from qemu_wait_io_event (in vcpu thread).
This change ensures we only call idle and resume cb only once a plugin
was
When we added SVE_MTEDESC_SHIFT, we effectively limited the
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter
These functions "use the standard load helpers", but
fail to clean_data_tbi or populate mtedesc.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sve.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
The TBI and TCMA bits are located within mtedesc, not desc.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/sme_helper.c | 8
target/arm/tcg/sve_helper.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
The API does not generate an error for setting ASYNC | SYNC; that merely
constrains the selection vs the per-cpu default. For qemu linux-user,
choose SYNC as the default.
Cc: qemu-sta...@nongnu.org
Reported-by: Gustavo Romero
Signed-off-by: Richard Henderson
---
The field is encoded as [0-3], which is convenient for
indexing our array of function pointers, but the true
value is [1-4]. Adjust before calling do_mem_zpa.
Add an assert, and move the comment re passing ZT to
the helper back next to the relevant code.
Cc: qemu-sta...@nongnu.org
Fixes:
Changes for v3:
- As if /sys/devices/system/cpu/cpu/mte_tcf_preferred is "sync".
- Fix do_st_zpa as well as do_ld_zpa. Oops.
Because of the above, I dropped Gustavo's t-b.
r~
Richard Henderson (6):
linux-user/aarch64: Choose SYNC as the preferred MTE mode
target/arm: Fix nregs
Share code that creates mtedesc and embeds within simd_desc.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.h | 2 ++
target/arm/tcg/translate-sme.c | 15 +++
target/arm/tcg/translate-sve.c | 47
On Tue, Feb 06, 2024 at 06:51:12PM -0300, Fabiano Rosas wrote:
> Based-on: 20240202102857.110210-1-pet...@redhat.com
> [PATCH v2 00/23] migration/multifd: Refactor ->send_prepare() and cleanups
> https://lore.kernel.org/r/20240202102857.110210-1-pet...@redhat.com
>
> Hi,
>
> For v3 I fixed the
On 2/7/24 00:23, Peter Maydell wrote:
+++ b/linux-user/aarch64/target_prctl.h
@@ -173,21 +173,22 @@ static abi_long
do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
if (cpu_isar_feature(aa64_mte, cpu)) {
-
From: Peter Xu
The new build-previous-qemu job relies on QEMU release tag being present,
while that may not be always true for personal git repositories since by
default tag is not pushed. The job can fail on those CI kicks, as reported
by Peter Maydell.
Fix it by fetching the tags remotely
From: Peter Xu
It turns out that we may not be able to enable this test even for the
upcoming v9.0. Document what we're still missing.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Peter Xu
---
.gitlab-ci.d/buildtest.yml | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
From: Peter Xu
v2:
- Fix a typo in patch 2 on QEMU_PREV_VERSION
- Added R-bs for Dan
Hi,
This small patchset updates the recent cross-binary test for migration on
a few things.
Patch 1 modifies the aarch64 test GIC version to 3 rather than "max",
paving way for enabling it, even if the CPU
From: Peter Xu
Recently we introduced cross-binary migration test. It's always wanted
that migration-test uses stable guest ABI for both QEMU binaries in this
case, so that both QEMU binaries will be compatible on the migration
stream with the cmdline specified.
Switch to a static gic version
On 2/7/24 00:46, Peter Maydell wrote:
@@ -4600,7 +4601,7 @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
* accessible via the instruction encoding.
*/
assert(fn != NULL);
-do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
+do_mem_zpa(s, zt, pg, addr,
-Original Message-
From: Nabih Estefan
Sent: Wednesday, February 7, 2024 7:24 AM
To: peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing
; wuhao...@google.com; jasow...@redhat.com; IS20 Avi
Fishman ; nabiheste...@google.com; CS20 KWLiu
; IS20 Tomer
On 2/7/24 00:23, Peter Maydell wrote:
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
When MTE3 is supported, the kernel maps
PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
to
MTE_CTRL_TCF_ASYMM
and from there to
SCTLR_EL1.TCF0 = 3
This depends on the setting of
Hello Alexander
On Tue, Feb 6, 2024 at 12:50 PM Alexander Monakov
wrote:
> Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
> routines are invoked much more rarely in normal use when most buffers
> are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
>
Nabih Estefan (1):
tests/qtest: Fixing GMAC test to run in 7xx
tests/qtest/meson.build | 4 ++--
tests/qtest/npcm_gmac-test.c | 12 ++--
2 files changed, 4 insertions(+), 12 deletions(-)
--
2.43.0.594.gd9cf4e227d-goog
Fixing the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
of 8xx. Also fixing comments referencing this and values expecting 8xx.
Change-Id: I07b91e8be473e6a1ece65a2202608b52ed4025b8
Signed-Off-By: Nabih Estefan
---
tests/qtest/meson.build | 4 ++--
This implements the zero page detection and handling on the multifd
threads.
Signed-off-by: Hao Xiang
---
migration/multifd.c | 62 +
migration/multifd.h | 5
2 files changed, 62 insertions(+), 5 deletions(-)
diff --git a/migration/multifd.c
This change adds zero page counters and updates multifd send/receive
tracing format to track the newly added counters.
Signed-off-by: Hao Xiang
---
migration/migration-hmp-cmds.c | 4
migration/multifd.c| 43 ++
migration/multifd.h|
Now that zero page checking is done on the multifd sender threads by
default, we still provide an option for backward compatibility. This
change adds a qtest migration test case to set the multifd-zero-page
option to false and run multifd migration with zero page checking on the
migration main
This change adds a dedicated handler for MigrationOps::ram_save_target_page in
multifd live migration. Now zero page checking can be done in the multifd
threads
and this becomes the default configuration. We still provide backward
compatibility
where zero page checking is done from the migration
This change extends the MigrationStatus interface to track zero pages
and zero bytes counter.
Signed-off-by: Hao Xiang
---
qapi/migration.json | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index
This new parameter controls where the zero page checking is running. If
this parameter is set to true, zero page checking is done in the multifd
sender threads. If this parameter is set to false, zero page checking is
done in the migration main thread.
Signed-off-by: Hao Xiang
---
This patchset is based on Juan Quintela's old series here
https://lore.kernel.org/all/20220802063907.18882-1-quint...@redhat.com/
In the multifd live migration model, there is a single migration main
thread scanning the page map, queuing the pages to multiple multifd
sender threads. The migration
On 2/7/24 06:48, Alexander Monakov wrote:
Increase unroll factor in SIMD loops from 4x to 8x in order to move
their bottlenecks from ALU port contention to load issue rate (two loads
per cycle on popular x86 implementations).
Ah, that answers my question re 128 vs 256 byte minimum.
So as far
On 2/7/24 08:34, Richard Henderson wrote:
On 2/7/24 06:48, Alexander Monakov wrote:
- /* Otherwise, use the unaligned memory access functions to
- handle the beginning and end of the buffer, with a couple
+ /* Use unaligned memory access functions to handle
+
On 2/7/24 06:48, Alexander Monakov wrote:
Make buffer_is_zero a 'static inline' function that tests up to three
bytes from the buffer before handing off to an unrolled loop. This
eliminates call overhead for most non-zero buffers, and allows to
optimize out length checks when it is known at
On 2/7/24 06:48, Alexander Monakov wrote:
-/* Otherwise, use the unaligned memory access functions to
- handle the beginning and end of the buffer, with a couple
+/* Use unaligned memory access functions to handle
+ the beginning and end of the buffer, with a
On 2/5/24 20:47, Sven Schnelle wrote:
Netbsd isn't able to detect a link on the emulated tulip card. That's
because netbsd reads the Chip Status Register of the Phy (address
0x14). The default phy data in the qemu tulip driver is all zero,
which means no link is established and autonegotation
On 2/7/24 06:48, Alexander Monakov wrote:
Use of prefetching in bufferiszero.c is quite questionable:
- prefetches are issued just a few CPU cycles before the corresponding
line would be hit by demand loads;
- they are done for simple access patterns, i.e. where hardware
prefetchers can
On 2/7/24 06:48, Alexander Monakov wrote:
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
routines are invoked much more rarely in normal use when most buffers
are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
frequency and voltage transition periods
On Wed, Jan 24, 2024 at 03:47:21PM +, Jonathan Cameron wrote:
> On Tue, 7 Nov 2023 10:07:09 -0800
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > Add (file/memory backed) host backend, all the dynamic capacity regions
> > will share a single, large enough host backend. Set up
On 2/7/24 06:48, Alexander Monakov wrote:
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the
On 2/6/24 23:29, Peter Maydell wrote:
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
also by enabling the AUXCR feature which defines the ACTLR
and HACTLR registers. As is our usual practice, we make these
simple reads-as-zero stubs for now.
Signed-off-by: Peter Maydell
---
It is possible that one of the multifd channels fails to be created at
multifd_new_send_channel_async() while the rest of the channel
creation tasks are still in flight.
This could lead to multifd_save_cleanup() executing the
qemu_thread_join() loop too early and not waiting for the threads
which
We currently have an unfavorable situation around multifd channels
creation and the migration thread execution.
We create the multifd channels with qio_channel_socket_connect_async
-> qio_task_run_in_thread, but only connect them at the
multifd_new_send_channel_async callback, called from
During multifd channel creation (multifd_send_new_channel_async) when
TLS is enabled, the multifd_channel_connect function is called twice,
once to create the TLS handshake thread and another time after the
asynchrounous TLS handshake has finished.
This creates a slightly confusing call stack
We currently only need p->running to avoid calling qemu_thread_join()
on a non existent thread if the thread has never been created.
However, there are at least two bugs in this logic:
1) On the sending side, p->running is set too early and
qemu_thread_create() can be skipped due to an error
Hide the error handling inside multifd_send_setup to make it cleaner
for the next patch to move the function around.
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
---
migration/migration.c | 6 +-
migration/multifd.c | 24 +---
migration/multifd.h | 2 +-
3
We're currently leaking the resources of the TLS thread by not joining
it and also overwriting the p->thread pointer altogether.
Fixes: a1af605bd5 ("migration/multifd: fix hangup with TLS-Multifd due to
blocking handshake")
Cc: qemu-stable
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
Based-on: 20240202102857.110210-1-pet...@redhat.com
[PATCH v2 00/23] migration/multifd: Refactor ->send_prepare() and cleanups
https://lore.kernel.org/r/20240202102857.110210-1-pet...@redhat.com
Hi,
For v3 I fixed the refcounting issue spotted by Avihai. The situation
there is a bit clunky due
On 2/6/24 23:29, Peter Maydell wrote:
The MPS2 SCC device is broadly the same for all FPGA images, but has
minor differences in the behaviour of the CFG registers depending on
the image. In many cases we don't really care about the functionality
controlled by these registers and a
On 2/6/24 23:29, Peter Maydell wrote:
The MPS SCC device has a lot of different flavours for the various
different MPS FPGA images, which look mostly similar but have
differences in how particular registers are handled. Currently we
deal with this with a lot of open-coded checks on
On 2/6/24 23:29, Peter Maydell wrote:
We currently guard the CFG3 register read with
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
which is clearly wrong as it is never true.
This register is present on all board types except AN524
and AN527; correct the condition.
Fixes:
On 2/6/24 23:29, Peter Maydell wrote:
Architecturally, the AArch32 MSR/MRS to/from banked register
instructions are UNPREDICTABLE for attempts to access a banked
register that the guest could access in a more direct way (e.g.
using this insn to access r8_fiq when already in FIQ mode). QEMU has
On Tue, 6 Feb 2024 at 21:24, Peter Maydell wrote:
>
> On Tue, 6 Feb 2024 at 03:22, Richard Henderson
> wrote:
> >
> > v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
> >
> >
> > r~
> >
> >
> > The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
On Tue, 6 Feb 2024 at 03:22, Richard Henderson
wrote:
>
> v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
>
>
> r~
>
>
> The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
>
> Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru
On Tue, 6 Feb 2024 at 20:38, Richard Henderson
wrote:
>
> On 2/6/24 23:29, Peter Maydell wrote:
> > The Cortex-R52 implements the Configuration Base Address Register
> > (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
> > type, so that our implementation provides the
On Tue, 6 Feb 2024 at 20:34, Richard Henderson
wrote:
>
> On 2/6/24 23:29, Peter Maydell wrote:
> > We support two different encodings for the AArch32 IMPDEF
> > CBAR register -- older cores like the Cortex A9, A7, A15
> > have this at 4, c15, c0, 0; newer cores like the
> > Cortex A35, A53, A57
On Tue, 6 Feb 2024 at 19:21, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 6/2/24 14:29, Peter Maydell wrote:
> > The AN536 is another FPGA image for the MPS3 development board. Unlike
> > the existing FPGA images we already model, this board uses a Cortex-R
> > family CPU, and it does not
On Tue, Feb 6, 2024 at 9:39 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/6/24 12:40, Alexandre Ghiti wrote:
> > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > when it is large (for example syzbot kernels are). From the kernel side,
> > there is no reason we could
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the complex decoder, and since
CMP+JNE are
Take into account that the inline wrapper ensures len >= 4.
Use __attribute__((may_alias)) for accesses via non-char pointers.
Avoid using out-of-bounds pointers in loop boundary conditions by
reformulating the 'for' loop as 'if (...) do { ... } while (...)'.
Signed-off-by: Alexander Monakov
Make buffer_is_zero a 'static inline' function that tests up to three
bytes from the buffer before handing off to an unrolled loop. This
eliminates call overhead for most non-zero buffers, and allows to
optimize out length checks when it is known at compile time (which is
often the case in Qemu).
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
routines are invoked much more rarely in normal use when most buffers
are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
frequency and voltage transition periods during which the CPU operates
at reduced
Use of prefetching in bufferiszero.c is quite questionable:
- prefetches are issued just a few CPU cycles before the corresponding
line would be hit by demand loads;
- they are done for simple access patterns, i.e. where hardware
prefetchers can perform better;
- they compete for load ports
Increase unroll factor in SIMD loops from 4x to 8x in order to move
their bottlenecks from ALU port contention to load issue rate (two loads
per cycle on popular x86 implementations).
Avoid using out-of-bounds pointers in loop boundary conditions.
Follow SSE2 implementation strategy in the AVX2
I am posting a new revision of buffer_is_zero improvements (v2 can be found at
https://patchew.org/QEMU/20231027143704.7060-1-mmroma...@ispras.ru/ ).
In our experiments buffer_is_zero took about 40%-50% of overall qemu-img run
time, even though Glib I/O is not very efficient. Hence, it remains an
On 2/6/24 12:40, Alexandre Ghiti wrote:
Currently, the initrd is placed at 128MB, which overlaps with the kernel
when it is large (for example syzbot kernels are). From the kernel side,
there is no reason we could not push the initrd further away in memory
to accommodate large kernels, so
On 2/6/24 23:29, Peter Maydell wrote:
The Cortex-R52 implements the Configuration Base Address Register
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
type, so that our implementation provides the register and the
associated qdev property.
Signed-off-by: Peter Maydell
On 2/6/24 23:29, Peter Maydell wrote:
We support two different encodings for the AArch32 IMPDEF
CBAR register -- older cores like the Cortex A9, A7, A15
have this at 4, c15, c0, 0; newer cores like the
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
When we implemented this we picked which
On 2/6/24 23:18, Jason Chien wrote:
The original implementation sets $pc to the address read from the jump
vector table first and links $ra with the address of the next instruction
after the updated $pc. After jumping to the updated $pc and executing the
next ret instruction, the program jumps
1 - 100 of 262 matches
Mail list logo
