Hi Laszlo, Igor, Gerd,
(old patch, now commit 5ce45c7a2b)
On 26/1/17 02:44, Laszlo Ersek wrote:
The generic edk2 SMM infrastructure prefers
EFI_SMM_CONTROL2_PROTOCOL.Trigger() to inject an SMI on each processor. If
Trigger() only brings the current processor into SMM, then edk2 handles it
in
On Thu, Feb 08, 2024 at 10:53:53AM -0800, Steve Sistare wrote:
> Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
> guest drivers' suspend methods flush outstanding requests and re-initialize
> the devices, and thus there is no device state to save and restore. The
> user
On Tue, Feb 20, 2024 at 12:39:35PM +0530, Srujana Challa wrote:
> Currently, virtio_pci_queue_mem_mult function always returns 4K
> when VIRTIO_PCI_FLAG_PAGE_PER_VQ is set. But this won't
> work for vhost vdpa when host has page size other than 4K.
> This patch introduces a new
On Tue, Feb 20, 2024 at 2:31 PM Markus Armbruster wrote:
> yong.hu...@smartx.com writes:
>
> > From: Hyman Huang
> >
> > To support detached LUKS header creation, make the existing 'file'
> > field in BlockdevCreateOptionsLUKS optional.
> >
> > Signed-off-by: Hyman Huang
> > Reviewed-by:
On Thu, Feb 08, 2024 at 10:54:03AM -0800, Steve Sistare wrote:
> When migration for cpr is initiated, stop the vm and set state
> RUN_STATE_FINISH_MIGRATE before ram is saved. This eliminates the
> possibility of ram and device state being out of sync, and guarantees
> that a guest in the
On 18/2/24 14:17, Bernhard Beschow wrote:
This function is used once in the pc machines. Remove it since it contains one
line only.
Signed-off-by: Bernhard Beschow
---
include/hw/input/i8042.h | 1 -
hw/i386/pc.c | 2 +-
hw/input/pckbd.c | 5 -
3 files changed, 1
On 18/2/24 14:16, Bernhard Beschow wrote:
Fixes: fbd758008f0f "hw/isa: extract FDC37M81X to a separate file"
Signed-off-by: Bernhard Beschow
---
hw/isa/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
$ git grep -i alphab
On 19/2/24 20:17, Thomas Huth wrote:
On 19/02/2024 12.32, Philippe Mathieu-Daudé wrote:
On 19/2/24 11:49, Thomas Huth wrote:
Let's start to unentangle internal.h by moving public IDE device
related definitions to ide-dev.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dev.h | 145
On Thu, Feb 08, 2024 at 10:54:02AM -0800, Steve Sistare wrote:
> Check the status returned by migration notifiers and report errors.
> If notifiers fail, call the notifiers again so they can clean up.
> None of the notifiers return an error status at this time.
>
> Signed-off-by: Steve Sistare
>
On 20/2/24 03:45, Zhao Liu wrote:
Hi Philippe,
On Mon, Feb 19, 2024 at 03:14:11PM +0100, Philippe Mathieu-Daudé wrote:
Date: Mon, 19 Feb 2024 15:14:11 +0100
From: Philippe Mathieu-Daudé
Subject: [PATCH 5/5] hw/i386/q35: Include missing 'hw/acpi/acpi.h' header
X-Mailer: git-send-email 2.41.0
On 20/2/24 03:33, Zhao Liu wrote:
Hi Philippe,
On Mon, Feb 19, 2024 at 03:14:09PM +0100, Philippe Mathieu-Daudé wrote:
Date: Mon, 19 Feb 2024 15:14:09 +0100
From: Philippe Mathieu-Daudé
Subject: [PATCH 3/5] hw/acpi/ich9: Include missing headers
X-Mailer: git-send-email 2.41.0
The
Currently, virtio_pci_queue_mem_mult function always returns 4K
when VIRTIO_PCI_FLAG_PAGE_PER_VQ is set. But this won't
work for vhost vdpa when host has page size other than 4K.
This patch introduces a new property(page-per-vdpa-vq) for vdpa
use case to fix the same.
Signed-off-by: Srujana
On Thu, Feb 08, 2024 at 10:54:00AM -0800, Steve Sistare wrote:
> Keep a separate list of migration notifiers for each migration mode.
>
> Suggested-by: Peter Xu
> Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
--
Peter Xu
On 19/2/24 19:16, Marek Marczykowski-Górecki wrote:
Introduce global xen_is_stubdomain variable when qemu is running inside
a stubdomain instead of dom0. This will be relevant for subsequent
patches, as few things like accessing PCI config space need to be done
differently.
Signed-off-by: Marek
++Alistair.
Sorry for that! It seems some typo or paste issue occurred when
pushing the patch.
Hi Alistair,
Could you help review this patch?
Thanks,
Haibo
On Mon, Jan 29, 2024 at 7:37 PM Haibo Xu wrote:
>
> On Mon, Jan 29, 2024 at 5:47 PM Andrew Jones wrote:
> >
> > On Mon, Jan 29, 2024 at
On Thu, Feb 08, 2024 at 10:53:59AM -0800, Steve Sistare wrote:
> Define MigrationNotifyFunc to improve type safety and simplify migration
> notifiers.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
--
Peter Xu
On 19/02/2024 23.59, Rayhan Faizel wrote:
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel
---
tests/qtest/bcm2835-i2c-test.c | 105 +
tests/qtest/meson.build| 2 +-
2
On Thu, Feb 08, 2024 at 10:53:58AM -0800, Steve Sistare wrote:
> postcopy_after_devices and migration_in_postcopy_after_devices are no
> longer used, so delete them.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
--
Peter Xu
On Thu, Feb 08, 2024 at 10:53:57AM -0800, Steve Sistare wrote:
> Passing MigrationState to notifiers is unsound because they could access
> unstable migration state internals or even modify the state. Instead, pass
> the minimal info needed in a new MigrationEvent struct, which could be
>
On 19/2/24 17:38, Philippe Mathieu-Daudé wrote:
Only files including "hw/acpi/ich9_tco.h" require
the ich9_generate_smi() declaration.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/acpi/ich9_tco.h| 1 +
include/hw/southbridge/ich9.h | 2 --
2 files changed, 1 insertion(+), 2
yong.hu...@smartx.com writes:
> From: Hyman Huang
>
> To support detached LUKS header creation, make the existing 'file'
> field in BlockdevCreateOptionsLUKS optional.
>
> Signed-off-by: Hyman Huang
> Reviewed-by: Daniel P. Berrangé
[...]
> diff --git a/qapi/block-core.json
On Fri, Feb 16, 2024 at 09:06:24AM +, Het Gala wrote:
> Ideally QAPI 'migrate' and 'migrate-incoming' does not allow 'uri' and
> 'channels' both arguments to be present in the arguments list as they
> are mutually exhaustive.
>
> Add a negative test case to validate the same. Even before the
On 19/2/24 19:24, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
Expose TYPE_ICH_DMI_PCI_BRIDGE to the new
"hw/pci-bridge/ich_dmi_pci.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS
On Fri, Feb 16, 2024 at 09:06:23AM +, Het Gala wrote:
> migration QAPIs can now work with either 'channels' or 'uri' as their
> argument.
>
> Signed-off-by: Het Gala
> ---
> tests/qtest/migration-test.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
On Fri, Feb 16, 2024 at 09:06:22AM +, Het Gala wrote:
> Introduce support for adding a 'channels' argument to migrate_qmp_fail
> and migrate_qmp functions within the migration qtest framework, enabling
> enhanced control over migration scenarios.
>
> Signed-off-by: Het Gala
> ---
>
On 19/2/24 19:31, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
Instantiate TYPE_ICH9_AHCI in TYPE_ICH9_SOUTHBRIDGE.
Since the PC machines can disable SATA (see the
PC_MACHINE_SATA dynamic property), add the 'sata-enabled'
property to disable it.
Signed-off-by:
On Thu, Feb 15, 2024 at 05:27:58PM +0500, Roman Khapov wrote:
> migrate_set_state(>state, MIGRATION_STATUS_COLO,
> - MIGRATION_STATUS_COMPLETED);
> + MIGRATION_STATUS_COMPLETED, NULL);
Instead of enforcing migrate_set_error() to always pass an error,
On Mon, Feb 19, 2024 at 05:43:56PM +0100, Philippe Mathieu-Daudé wrote:
> On 19/2/24 17:09, X512 via wrote:
> > MCFG segments should point to PCI configuration range, not BAR MMIO.
> >
>
> Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and
> devices")
> Reviewed-by: Philippe
On Tue, Feb 13, 2024 at 04:49:01PM +0100, Paolo Bonzini wrote:
> The build-previous-qemu job is now trying to fetch from the upstream
> repository, but the tag is only fetched into FETCH_HEAD:
>
> $ git remote add upstream https://gitlab.com/qemu-project/qemu 00:00
> $ git fetch upstream
On Mon, Feb 12, 2024 at 12:06:12AM -0800, Mattias Nissler wrote:
> Changes from v6:
>
> * Rebase, resolve straightforward merge conflict in system/dma-helpers.c
Hi, Mattias,
If the change is trivial, feel free to carry over my R-bs in the first two
patches in the commit message.
Thanks,
--
On Tue Feb 20, 2024 at 6:30 AM AEST, BALATON Zoltan wrote:
> Documentation on how to run Linux on the amigaone, pegasos2 and
> sam460ex machines is currently buried in the depths of the qemu-devel
> mailing list and in the source code. Let's collect the information in
> the QEMU handbook for a one
Use the generic llsc protection feature to implement real reservation
protection for larx/stcx.
This is more complicated and quite a bit slower than the cmpxchg
pseudo-reservation, so it's questionable whether it should be merged
or ever made the default.
It could possibly be sped up more by
The TCG TLB keeps a TLB_NOTDIRTY bit that must be kept coherent
with the cpu physical dirty memory bitmaps. If any bits are clear,
TLB_NOTDIRTY *must* be set in all CPUs so that the nodirty_write()
slowpath is guaranteed to be called on a write access.
TLB_NOTDIRTY may be set if none of the bits
This uses the cpu physical memory dirty mechanism to provide a LL/SC
protection system, so that a CPU can set llsc protection on a block of
memory, and it can check whether any other CPUs have stored to that
memory in a way that can be done race-free to perform a store
conditional on that check.
I've been toying with how we might do a more faithful ll/sc emulation.
Our cmpxchg based one actually had problems on some firmware code we're
testing.
The using the dirty memory bitmap to detect stores coming from other
CPUs and invalidating active protection / reservations seems to be a
On Tue Feb 20, 2024 at 12:10 AM AEST, Thomas Huth wrote:
> On 19/02/2024 07.17, Nicholas Piggin wrote:
> > The fastpath in cpu_physical_memory_sync_dirty_bitmap() to test large
> > aligned ranges forgot to bring the TCG TLB up to date after clearing
> > some of the dirty memory bitmap bits. This
Hi Philippe,
On Mon, Feb 19, 2024 at 03:14:11PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 19 Feb 2024 15:14:11 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 5/5] hw/i386/q35: Include missing 'hw/acpi/acpi.h' header
> X-Mailer: git-send-email 2.41.0
>
> "hw/acpi/acpi.h" is
On 2/20/24 06:15, Markus Armbruster wrote:
> Making this member @size mandatory means we must specify it when
> BlockdevCreateOptionsQcow2 member @zone is present and @zone's member
> @mode is "host-managed". Feels right to me. Am I missing anything?
That's right. And the
On Mon, Feb 19, 2024 at 03:14:10PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 19 Feb 2024 15:14:10 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 4/5] hw/acpi/ich9_tco: Include missing
> 'migration/vmstate.h' header
> X-Mailer: git-send-email 2.41.0
>
> We need the
Hi Philippe,
On Mon, Feb 19, 2024 at 03:14:09PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 19 Feb 2024 15:14:09 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 3/5] hw/acpi/ich9: Include missing headers
> X-Mailer: git-send-email 2.41.0
>
> The ICH9LPCPMRegs structure has
On Mon, Feb 19, 2024 at 03:14:07PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 19 Feb 2024 15:14:07 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 1/5] hw/acpi: Include missing 'qapi/qapi-types-acpi.h'
> generated header
> X-Mailer: git-send-email 2.41.0
>
> ACPIOSTInfo is a QAPI
On Mon, Feb 19, 2024 at 11:32 PM Markus Armbruster
wrote:
> Yong Huang writes:
>
> > On Tue, Feb 13, 2024 at 6:26 PM Michael S. Tsirkin
> wrote:
> >
> >> On Fri, Feb 02, 2024 at 10:32:15PM +0800, Hyman Huang wrote:
> >> > x-query-virtio-status returns several sets of virtio feature and
> >> >
On Tue Feb 20, 2024 at 12:49 AM AEST, BALATON Zoltan wrote:
> On Mon, 19 Feb 2024, Nicholas Piggin wrote:
> > FreeBSD project provides qcow2 images that work well for testing QEMU.
> > Add pseries tests for HPT and Radix, KVM and TCG. This uses a short
> > term VM image, because FreeBSD has not
into
> > staging (2024-02-16 11:05:14 +)
> >
> > are available in the Git repository at:
> >
> > https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-20240219
> >
> > for you to fetch changes up to 922e408e12315121d3e09304b8b8f462ea051af1:
>
On Tue Feb 20, 2024 at 12:10 AM AEST, Thomas Huth wrote:
> On 19/02/2024 07.17, Nicholas Piggin wrote:
> > The fastpath in cpu_physical_memory_sync_dirty_bitmap() to test large
> > aligned ranges forgot to bring the TCG TLB up to date after clearing
> > some of the dirty memory bitmap bits. This
On Fri Feb 16, 2024 at 3:50 AM AEST, Peter Maydell wrote:
> On Thu, 15 Feb 2024 at 17:16, Nicholas Piggin wrote:
> >
> > Calculate the BHRB base from arithmetic on the tcg_env target ptr.
> >
> > Signed-off-by: Nicholas Piggin
> > ---
> > Hi Glenn,
> >
> > I think I have to squash this into the
On Fri Feb 16, 2024 at 5:42 AM AEST, Richard Henderson wrote:
> On 2/15/24 07:15, Nicholas Piggin wrote:
> > diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> > index 731dd8df35..3541cd83cd 100644
> > --- a/target/ppc/machine.c
> > +++ b/target/ppc/machine.c
> > @@ -724,7 +724,7 @@ static
This patch series implements support for the Broadcom Serial Controller used
by BCM2835 based boards for I2C.
[Changes in v2]
- Fixed and simplified writing to status register
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c:
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 32 +---
include/hw/arm/bcm2835_peripherals.h | 3 ++-
3 files changed, 32
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel
---
tests/qtest/bcm2835-i2c-test.c | 105 +
tests/qtest/meson.build| 2 +-
2 files changed, 106 insertions(+), 1 deletion(-)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer
Am 18. Februar 2024 16:12:30 UTC schrieb BALATON Zoltan :
>On Sun, 18 Feb 2024, Bernhard Beschow wrote:
>> This series attempts to make QEMU's south bridge families PIIX, ICH9, and VIA
>> 82xx more self-contained by integrating IO port 92 like the originals do.
>>
>> In QEMU, the IO port is
On Mon, Feb 19, 2024 at 07:16:06PM +0100, Marek Marczykowski-Górecki wrote:
> From: Frédéric Pierret (fepitre)
This shouldn't be here, it's my patch.
> When running in a stubdomain, the config space access via sysfs needs to
> use BDF as seen inside stubdomain (connected via xen-pcifront),
Sam Li writes:
> Markus Armbruster 于2024年2月19日周一 21:42写道：
>>
>> Sam Li writes:
>>
>> > Markus Armbruster 于2024年2月19日周一 16:56写道：
>> >>
>> >> Sam Li writes:
>> >>
>> >> > Markus Armbruster 于2024年2月19日周一 15:40写道：
>> >> >>
>> >> >> Sam Li writes:
>> >> >>
>> >> >> > Markus Armbruster
Markus Armbruster 于2024年2月19日周一 21:42写道：
>
> Sam Li writes:
>
> > Markus Armbruster 于2024年2月19日周一 16:56写道：
> >>
> >> Sam Li writes:
> >>
> >> > Markus Armbruster 于2024年2月19日周一 15:40写道：
> >> >>
> >> >> Sam Li writes:
> >> >>
> >> >> > Markus Armbruster 于2024年2月19日周一 13:05写道：
> >> >> >>
> >>
On 2/19/24 04:15, Ilya Leoshkevich wrote:
A CPU's TaskState is stored in the CPUState's void *opaque field,
accessing which is somewhat awkward due to having to use a cast.
Introduce a wrapper and use it everywhere.
Suggested-by: Alex Bennée
Signed-off-by: Ilya Leoshkevich
---
Sam Li writes:
> Markus Armbruster 于2024年2月19日周一 16:56写道：
>>
>> Sam Li writes:
>>
>> > Markus Armbruster 于2024年2月19日周一 15:40写道：
>> >>
>> >> Sam Li writes:
>> >>
>> >> > Markus Armbruster 于2024年2月19日周一 13:05写道：
>> >> >>
>> >> >> One more thing...
>> >> >>
>> >> >> Markus Armbruster writes:
Am 19. Februar 2024 08:51:07 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 17/2/24 11:46, Bernhard Beschow wrote:
>> The interrupt handlers need to be populated before the device is realized
>> since
>> internal devices such as the RTC are wired during realize(). If the interrupt
>> handlers
On Fri, 16 Feb 2024, Thomas Huth wrote:
On 16/02/2024 01.10, BALATON Zoltan wrote:
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently burried in the depths of the qemu-devel
s/burried/buried/
mailing list and in the source code. Let's collect the
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently buried in the depths of the qemu-devel
mailing list and in the source code. Let's collect the information in
the QEMU handbook for a one stop solution.
Co-authored-by: Bernhard Beschow
Signed-off-by:
Tests:
- the ability to change the sysclk of the device
- the ability to enable/disable/configure the PLLs
- if the clock multiplexers work
- the register flags and the generation of irqs
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Acked-by: Thomas Huth
---
tests/qtest/meson.build
Now that we can generate reliable clock frequencies from the RCC, remove
the hacky definition of the sysclk in the b_l475e_iot01a initialisation
code and use the correct RCC clock.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Acked-by: Alistair Francis
---
hw/arm/b-l475e-iot01a.c
Add write protections for the fields in the CR register.
PLL configuration write protections (among others) have not
been handled yet. This is planned in a future patch set.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/misc/stm32l4x5_rcc.c | 164
Update the RCC state and propagate frequency changes when writing to the
RCC registers. Currently, ICSCR, CIER, the reset registers and the stop
mode registers are not implemented.
Some fields have not been implemented due to uncertainty about
how to handle them (Like the clock security system
Instanciate the whole clock tree and using the Clock multiplexers and
the PLLs defined in the previous commits. This allows to statically
define the clock tree and easily follow the clock signal from one end to
another.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
This object represents the PLLs and their channels. The PLLs allow for a
more fine-grained control of the clocks frequency.
Wasn't sure about how to handle the reset and the migration so used the
same appproach as the BCM2835 CPRMAN.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
This object is used to represent every multiplexer in the clock tree as
well as every clock output, every presecaler, frequency multiplier, etc.
This allows to use a generic approach for every component of the clock tree
(except the PLLs).
Wasn't sure about how to handle the reset and the
Add the necessary files to add a simple RCC implementation with just
reads from and writes to registers. Also instanciate the RCC in the
STM32L4x5_SoC. It is needed for accurate emulation of all the SoC
clocks and timers.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Acked-by:
This patch adds the STM32L4x5 RCC (Reset and Clock Control) device and is part
of a series implementing the STM32L4x5 with a few peripherals.
Due to the high number of lines, I tried to split the patch into several
independent commits.
Each commit compiles on its own but I had to add temporary
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
---
tests/qtest/bcm2835-i2c-test.c | 105 +
tests/qtest/meson.build|
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 32 +---
include/hw/arm/bcm2835_peripherals.h | 3 ++-
3 files changed, 32
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer
This patch series implements support for the Broadcom Serial Controller used
by BCM2835 based boards for I2C.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c: Implement Broadcom Serial Controller (BSC)
hw/arm: Connect BSC to
On 19/02/2024 12.53, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Thomas Huth wrote:
These definitions are required outside of the hw/ide/ code, too,
so lets's move them from internal.h to a new header called ide-dma.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dma.h | 30
The QMP command query_migrate might see incorrect throughput numbers
if it runs after we've set the migration completion status but before
migration_calculate_complete() has updated s->total_time and s->mbps.
The migration status would show COMPLETED, but the throughput value
would be the one
Am 19.02.24 um 17:26 schrieb Thomas Huth:
On 19/02/2024 16.53, Daniel P. Berrangé wrote:
On Mon, Feb 19, 2024 at 03:37:31PM +, Peter Maydell wrote:
Our msys2 32-bit Windows host CI job has been failing recently
because upstream MSYS2 are starting to phase out 32-bit windows
host support
On 19/02/2024 12.32, Philippe Mathieu-Daudé wrote:
On 19/2/24 11:49, Thomas Huth wrote:
Let's start to unentangle internal.h by moving public IDE device
related definitions to ide-dev.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dev.h | 145 +-
probe_target_compiler() when checking for multilib support checks if
-nostdlib works together with -lgcc. It isn't necessary for building
various components in pc-bios/optionrom, as evidenced by looking at
actually used link flags there.
Alpine Linux for x86_64 does not ship with 32bit libgcc, but
On 19/02/2024 12.45, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Thomas Huth wrote:
qdev.c is a mixture between IDE bus specific functions and IDE device
functions. Let's split it up to make it more obvious which part is
related to bus handling and which part is related to device handling.
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
Instantiate TYPE_ICH9_AHCI in TYPE_ICH9_SOUTHBRIDGE.
Since the PC machines can disable SATA (see the
PC_MACHINE_SATA dynamic property), add the 'sata-enabled'
property to disable it.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS
On 2/19/24 18:14, Corey Minyard wrote:
On Mon, Feb 19, 2024 at 04:53:47PM +, Paz Offer wrote:
Thank you very much Corey,
I am simulating an external module that wants to communicate with the board
management controller (BMC).
The real device will be connected to the board using i2c bus,
On Mon, 19 Feb 2024, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
Expose TYPE_ICH_DMI_PCI_BRIDGE to the new
"hw/pci-bridge/ich_dmi_pci.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
From: Frédéric Pierret (fepitre)
When running in a stubdomain, the config space access via sysfs needs to
use BDF as seen inside stubdomain (connected via xen-pcifront), which is
different from the real BDF. For other purposes (hypercall parameters
etc), the real BDF needs to be used.
Get the
Introduce global xen_is_stubdomain variable when qemu is running inside
a stubdomain instead of dom0. This will be relevant for subsequent
patches, as few things like accessing PCI config space need to be done
differently.
Signed-off-by: Marek Marczykowski-Górecki
---
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Tuesday, February 13, 2024 9:23 PM
> To: Srujana Challa
> Cc: qemu-devel@nongnu.org; Vamsi Krishna Attunuru
> ; Jerin Jacob
> Subject: Re: [EXT] Re: [PATCH] virtio-pci: correctly set virtio pci queue mem
> multiplier
>
> On
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
Expose TYPE_ICH_DMI_PCI_BRIDGE to the new
"hw/pci-bridge/ich_dmi_pci.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
include/hw/pci-bridge/ich_dmi_pci.h | 20
On 2/1/24 08:28, Zhenzhong Duan wrote:
> From: Yi Liu
>
> Add a framework to check and synchronize host IOMMU cap/ecap with
> vIOMMU cap/ecap.
>
> The sequence will be:
>
> vtd_cap_init() initializes iommu->cap/ecap.
> vtd_check_hdev() update iommu->cap/ecap based on host cap/ecap.
>
On 2/1/24 08:28, Zhenzhong Duan wrote:
> From: Yi Liu
>
> This adds set/unset_iommu_device() implementation in Intel vIOMMU.
> In set call, a pointer to host IOMMU device info is stored in hash
> table indexed by PCI BDF.
>
> Signed-off-by: Yi Liu
> Signed-off-by: Yi Sun
> Signed-off-by:
Hi Jonathan,
Thanks for the feedbacks.
>-Original Message-
>From: Jonathan Cameron
>Sent: 19 February 2024 16:59
>To: Shiju Jose
>Cc: qemu-devel@nongnu.org; linux-...@vger.kernel.org; tanxiaofei
>; Zengtao (B) ; Linuxarm
>
>Subject: Re: [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add
Hi Zhenzhong,
On 2/1/24 08:28, Zhenzhong Duan wrote:
> From: Yi Liu
>
> This adds pci_device_set/unset_iommu_device() to set/unset
> HostIOMMUDevice for a given PCIe device. Caller of set
> should fail if set operation fails.
>
> Extract out pci_device_get_iommu_bus_devfn() to facilitate
>
On i386, after fixing the page walking code to work with pages in
MMIO memory (specifically CXL emulated interleaved memory),
a crash was seen in an interrupt handling path.
Useful part of backtrace
7 0x55ab1929 in bql_lock_impl (file=0x56049122
"../../accel/tcg/cputlb.c",
From: Gregory Price
CXL emulation of interleave requires read and write hooks due to
requirement for subpage granularity. The Linux kernel stack now enables
using this memory as conventional memory in a separate NUMA node. If a
process is deliberately forced to run from that node
$ numactl
From: Peter Maydell
If a page table is in IO memory and lookup_tb_ptr probes
the TLB it can result in a page table walk for the instruction
fetch. If this hits IO memory and io_prepare falsely assumes
it needs to do a TLB recompile.
Avoid that by setting can_do_io at the start of
v2: Changes documented in patch 3.
- I have not addressed Richard's comment on recursive locks as that
seems to be a more general issue not specific to this patch set.
CXL memory is interleaved at granularities as fine as 64 bytes.
To emulate this each read and write access undergoes
Hi Zhenzhong,
On 2/1/24 08:28, Zhenzhong Duan wrote:
> This callback will be used to initialize base and public elements
> in IOMMULegacyDevice.
>
> Signed-off-by: Zhenzhong Duan
> ---
> hw/vfio/container.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/vfio/container.c
On Mon, Feb 19, 2024 at 04:53:47PM +, Paz Offer wrote:
> Thank you very much Corey,
>
> I am simulating an external module that wants to communicate with the board
> management controller (BMC).
> The real device will be connected to the board using i2c bus, and could
> initiate
in the Git repository at:
>
> https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-20240219
>
> for you to fetch changes up to 922e408e12315121d3e09304b8b8f462ea051af1:
>
> target/ppc: optimise ppcemb_tl
On Mon, 19 Feb 2024 23:00:25 +0800
wrote:
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> control feature.
>
> The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
> Specification (JESD79-5) and allows the DRAM to
Thank you very much Corey,
I am simulating an external module that wants to communicate with the board
management controller (BMC).
The real device will be connected to the board using i2c bus, and could
initiate communication at any time, by sending bytes over the bus.
I am not sure whether
On Mon, Feb 19, 2024 at 04:40:38PM +, Peter Maydell wrote:
> On Mon, 19 Feb 2024 at 16:26, Thomas Huth wrote:
> >
> > On 19/02/2024 16.53, Daniel P. Berrangé wrote:
> > > On Mon, Feb 19, 2024 at 03:37:31PM +, Peter Maydell wrote:
> > >> Our msys2 32-bit Windows host CI job has been
1 - 100 of 312 matches
Mail list logo
