IODA PCT table (#3) is implemented
without any functionality, being a debug table.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 6 ++
include/hw/pci-host/pnv_phb4.h | 2 ++
include/hw/pci-host/pnv_phb4_regs.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/h
On Thu, 21 Mar 2024 at 09:27, Jinjie Ruan wrote:
>
>
>
> On 2024/3/20 1:28, Peter Maydell wrote:
> > On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
> >>
> >> This only implements the external delivery method via the GICv3.
> >>
> >> Signed-off-by: Jinjie Ruan
> >> Reviewed-by: Richard Henderso
On 20/3/24 21:50, dongwon@intel.com wrote:
From: Dongwon Kim
This commit introduces new methods within ui/console to handle the allocation,
initialization, and field retrieval of QemuDmaBuf. By isolating these
operations within ui/console, it enhances safety and encapsulation of
the struct.
On 20/3/24 21:50, dongwon@intel.com wrote:
From: Dongwon Kim
QemuDmaBuf struct is defined and primarily used by ui/console/gl so it is
better to handle its creation, initialization and access within ui/console
rather than within hw modules such as hw/display/virtio-gpu and
hw/vfio/display.
Since commit v8.1.0-511-g399e5e7125 "target/arm: Implement FEAT_PACQARMA3",
pauth-qarma3 is the default pauth scheme. However this one is very slow.
When people run aarch64 code in qemu tcg, an immediate reaction is like,
"this seems to be a bug somewhere", since the code run insanely slower tha
On 2024/3/20 1:28, Peter Maydell wrote:
> On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
>>
>> This only implements the external delivery method via the GICv3.
>>
>> Signed-off-by: Jinjie Ruan
>> Reviewed-by: Richard Henderson
>> ---
>> v8:
>> - Fix the rcu stall after sending a VNMI in qem
PMC5 does not count instructions when single stepping (with gdb,
haven't tried single stepping inside the target), or when taking
exceptions. At least the single-steppig is a bit of a landmine for
replay.
I don't quite understand the logic of the approach taken for
counting now. AFAIKS instruction
On 2024/3/21 16:18, Richard Henderson wrote:
On 3/20/24 17:58, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set
to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the
element
agnostic policy.
However, this function can't deal the bi
On 3/20/24 17:58, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.
However, this function can't deal the big endian situation. This patch fixes
the problem b
I will re-send shortly. Thanks.
Daniel Henrique Barboza 於 2024年3月20日 週三
上午5:19寫道：
> Hi Jason,
>
> Care to re-send please? The patches don't apply to neither
> riscv-to-apply.next
> nor master.
>
>
> Thanks,
>
> Daniel
>
> On 3/19/24 13:23, Jason Chien wrote:
> > Ping. Can anyone review the patch
On 21/3/24 08:01, Kim, Dongwon wrote:
Hi Phlippe,
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Wednesday, March 20, 2024 11:57 PM
To: Kim, Dongwon ; qemu-devel@nongnu.org
Cc: marcandre.lur...@redhat.com
Subject: Re: [PATCH 0/3] ui/console: initialize QemuDmaBuf in ui/console
Hi Phlippe,
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, March 20, 2024 11:57 PM
> To: Kim, Dongwon ; qemu-devel@nongnu.org
> Cc: marcandre.lur...@redhat.com
> Subject: Re: [PATCH 0/3] ui/console: initialize QemuDmaBuf in ui/console
>
> Hi Dongwon,
>
> On 20/3/
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