On 2024/3/28 22:50, Peter Maydell wrote:
> On Mon, 25 Mar 2024 at 08:53, Jinjie Ruan wrote:
>>
>> Add the NMIAR CPU interface registers which deal with acknowledging NMI.
>>
>> When introduce NMI interrupt, there are some updates to the semantics for the
>> register ICC_IAR1_EL1 and
Shiyang Ruan wrote:
> The transaction types are defined in General Media Event Record/DRAM Event
> per CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 and
> Section 8.2.9.2.1.2; Table 8-44. Add them for Event Record handler use.
Combine this patch with the one that uses them so that the use case can
Shiyang Ruan wrote:
> Poison injection from debugfs is silent too. Add calling
> cxl_mem_report_poison() to make it able to do memory_failure().
Why does this needs to be signalled? It is a debug interface, the
debugger can also trigger a read after the injection, or trigger page
soft-offline.
Shiyang Ruan wrote:
> The GMER only has "Physical Address" field, no such one indicates length.
> So, when a poison event is received, we could use GET_POISON_LIST command
> to get the poison list. Now driver has cxl_mem_get_poison(), so
> reuse it and add a parameter 'bool report', report poison
On 2024/3/28 22:54, Peter Maydell wrote:
> On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>>
>> A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
>> non-maskable property in PendingIrq and GICR/GICD. Since add new device
>> state, it also needs to be migrated, so also
Shiyang Ruan wrote:
> If poison is detected(reported from cxl memdev), OS should be notified to
> handle it. So, introduce this helper function for later use:
> 1. translate DPA to HPA;
> 2. enqueue records into memory_failure's work queue;
>
> Signed-off-by: Shiyang Ruan
This patch is too
Shiyang Ruan wrote:
> The length of Physical Address in General Media Event Record/DRAM Event
> Record is 64-bit, so the field mask should be defined as such length.
> Otherwise, this causes cxl_general_media and cxl_dram tracepoints to
> mask off the upper-32-bits of DPA addresses. The cxl_poison
target_msqid_ds::msg_*time field pairs are reversed on 32-bit TARGET_PPC
and TARGET_SPARC and on big-endian TARGET_MIPS and TARGET_XTENSA.
Fix the order to match the kernel definitions.
The issue is spotted by the libc-test http://nsz.repo.hu/git/?p=libc-test
on big-endian xtensa core.
Cc:
This operation is trivial and does not require a helper.
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/helper.h | 1 -
target/hppa/sys_helper.c | 4 ++--
target/hppa/translate.c | 17 +
3 files changed, 15 insertions(+), 7 deletions(-)
diff
With r1 as zero is by far the most common usage of UADDCM, as the
easiest way to invert a register. The compiler does occasionally
use the addition step as well, and we can simplify that to avoid
a temp and write directly into the destination.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
on xtensa and thus need to use tswap32.
The issue is spotted by the libc-test http://nsz.repo.hu/git/?p=libc-test
on big-endian xtensa core.
Cc: qemu-sta...@nongnu.org
Fixes: a3da8be5126b ("target/xtensa: linux-user: fix sysv
Split do_unit_cond to do_unit_zero_cond to only handle conditions
versus zero. These are the only ones that are legal for UXOR.
Simplify trans_uxor accordingly.
Rename do_unit to do_unit_addsub, since xor has been split.
Properly compute carry-out bits for add and subtract, mirroring
the code in
The return address comes from IA*Q_Next, and IASQ_Next
is always equal to IASQ_Back, not IASQ_Front.
Tested-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c
Along this path we have already skipped the insn to be
nullified, so the subsequent insn should be executed.
Cc: qemu-sta...@nongnu.org
Reported-by: Sven Schnelle
Tested-by: Sven Schnelle
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 1 +
From: Sven Schnelle
Wide mode provides two more conditions, add them.
Fixes: 59963d8fdf42 ("target/hppa: Pass d to do_unit_cond")
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Message-Id: <20240321184228.611897-1-sv...@stackframe.org>
Signed-off-by: Richard Henderson
---
Do not clobber the high bits of the address by using a 32-bit deposit.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c
Overflow indicator should include the effect of the shift step.
We had previously left ??? comments about the issue.
Tested-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 84 +++--
1 file changed, 65 insertions(+), 19
Prepare for proper indication of shladd unsigned overflow.
The UV indicator will be zero/not-zero instead of a single bit.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 12 +---
1 file changed, 5 insertions(+), 7
The carry bits for each nibble N are located in bit (N+1)*4,
so the shift by 3 was off by one. Furthermore, the carry bit
for the most significant carry bit is indeed located in bit 64,
which is located in a different storage word.
Use a double-word shift-right to reassemble into a single word
Reviewed-by: Helge Deller
Tested-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ceb739c54a..8c1a564c5d 100644
--- a/target/hppa/translate.c
+++
Split trans_diag into per-operation functions.
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 8 +++-
target/hppa/translate.c | 34 +-
2 files changed, 28 insertions(+), 14 deletions(-)
diff --git
From: Sven Schnelle
Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS")
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Message-Id: <20240321184228.611897-2-sv...@stackframe.org>
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 6 ++
1 file changed,
The call to gen_helper_read_interval_timer is
identical on both sides of the IF.
Reviewed-by: Helge Deller
Tested-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/hppa/translate.c
From: Sven Schnelle
Move it to cpu.h, so it can also be used in hppa_form_gva_psw().
Signed-off-by: Sven Schnelle
Reviewed-by: Helge Deller
Reviewed-by: Richard Henderson
Message-Id: <20240324080945.991100-2-sv...@stackframe.org>
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h
From: Helge Deller
The 32-bit PA-7300LC (PCX-L2) CPU and the 64-bit PA8700 (PCX-W2) CPU
use different diag instructions to save or restore the CPU registers
to/from the shadow registers.
Implement those per-CPU architecture diag instructions to fix those
parts of the HP ODE testcases (L2DIAG
The cond_need_ext predicate was created while we still had a
32-bit compilation mode. It now makes more sense to treat D
as an absolute indicator of a 64-bit operation.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 20
The following changes since commit 5012e522aca161be5c141596c66e5cc6082538a9:
Update version for v9.0.0-rc1 release (2024-03-26 19:46:55 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-pa-20240329
for you to fetch changes up
Call translator_io_start before write to EIRR.
Move evaluation of EIRR vs EIEM to hppa_cpu_exec_interrupt.
Exit TB after write to EIEM, but otherwise use a straight store.
Reviewed-by: Helge Deller
Tested-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/helper.h | 1 -
From: Ilya Leoshkevich
The indices of arguments passed to print_shmat() are all off-by-1,
because arg1 is the ipc() command. Fix them.
New output for linux-shmat-maps test:
3501769 shmat(4784214,0x0080,SHM_RND) = 0
Fixes: 9f7c97324c27 ("linux-user: Add strace for shmat")
From: Ilya Leoshkevich
Add a small test to prevent regressions.
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-Id: <20240325192436.561154-5-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
tests/tcg/multiarch/linux/linux-shmat-null.c | 38
Fixes: 83b4613ba83 ("disas: introduce show_opcodes")
Signed-off-by: Richard Henderson
---
disas/disas-mon.c | 1 +
disas/disas.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/disas/disas-mon.c b/disas/disas-mon.c
index 48ac492c6c..5d6d9aa02d 100644
--- a/disas/disas-mon.c
+++
Using log_pc produces the pc at the beginning of TB,
not the actual pc installed by cpu_restore_state_from_tb,
which could be any of the guest instructions within TB.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Ilya Leoshkevich
In the h != g && shmaddr == NULL && !reserved_va case, target_shmat()
incorrectly mmap()s the initial anonymous range with
MAP_FIXED_NOREPLACE, even though the earlier mmap_find_vma() has
already reserved the respective address range.
Fix by using MAP_FIXED when "mapped",
The 'sign' computation is attempting to locate the sign bit that has
been repeated, so that we can test if that bit is known zero. That
computation can be zero if there are no known sign repetitions.
Cc: qemu-sta...@nongnu.org
Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting")
The following changes since commit 5012e522aca161be5c141596c66e5cc6082538a9:
Update version for v9.0.0-rc1 release (2024-03-26 19:46:55 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240329
for you to fetch changes up
From: Ilya Leoshkevich
The indices of arguments used with semctl() are all off-by-1, because
arg1 is the ipc() command. Fix them. While at it, reuse print_semctl().
New output (for a small test program):
3540333 semctl(999,888,SEM_INFO,0x7fe5051ee9a0) = -1 errno=14 (Bad
address)
On Fri, Mar 29, 2024 at 5:48 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Max,
>
> On 29/3/24 07:31, Max Filippov wrote:
> > - target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
> >on xtensa and thus need to use tswap32
> > - target_msqid_ds::msg_*time field pairs are reversed
Alison Schofield wrote:
> On Fri, Mar 29, 2024 at 11:22:32AM -0700, Dan Williams wrote:
> > Alison Schofield wrote:
> > [..]
> > > Upon receipt of that new poison list, call memory_failture_queue()
> > > on *any* poison in a mapped space. Is that OK? Can we call
> > > memory_failure_queue() on
Also does qemu link to libarchive? The original analysis wasn't a full
reverse engineer of the payload so we don't know if it only affects sshd.
On Sat, 30 Mar 2024, 07:01 Daniel P. Berrangé, wrote:
> On Fri, Mar 29, 2024 at 06:59:30PM +0100, Paolo Bonzini wrote:
> > For more info, see
> >
>
On Fri, Mar 29, 2024 at 06:59:30PM +0100, Paolo Bonzini wrote:
> For more info, see
> https://lwn.net/ml/oss-security/20240329155126.kjjfduxw2yrlx...@awork3.anarazel.de/
> but, essentially, xz was backdoored and it seems like upstream was directly
> responsible for this.
>
> Based on this, should
On Fri, Mar 29, 2024 at 11:28:54AM +0100, Philippe Mathieu-Daudé wrote:
> Hi Zhijian,
>
> On 29/3/24 02:53, Zhijian Li (Fujitsu) wrote:
> >
> >
> > On 28/03/2024 23:01, Peter Xu wrote:
> > > On Thu, Mar 28, 2024 at 11:18:04AM -0300, Fabiano Rosas wrote:
> > > > Philippe Mathieu-Daudé writes:
>
On Fri, Mar 29, 2024 at 11:22:32AM -0700, Dan Williams wrote:
> Alison Schofield wrote:
> [..]
> > Upon receipt of that new poison list, call memory_failture_queue()
> > on *any* poison in a mapped space. Is that OK? Can we call
> > memory_failure_queue() on any and every poison report that is in
On 29.03.24 13:56, Cédric Le Goater wrote:
This allows to report more precise errors in the migration handler
dirty_bitmap_save_setup().
Suggested-by Vladimir Sementsov-Ogievskiy
Signed-off-by: Cédric Le Goater
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
Add command to sync config from vhost-user backend to the device. It
may be helpful when VHOST_USER_SLAVE_CONFIG_CHANGE_MSG failed or not
triggered interrupt to the guest or just not available (not supported
by vhost-user server).
Command result is racy if allow it during migration. Let's allow
Send a new event when guest reads virtio-pci config after
virtio_notify_config() call.
That's useful to check that guest fetched modified config, for example
after resizing disk backend.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/virtio/virtio-pci.c | 9 +
v3:
02: add r-b by Markus
03: improve commit message
04: improve documentation, merge race-fix here (which was v2:05),
rebase on master (migration_is_running() now without arguments)
05: improve documentation
Vladimir Sementsov-Ogievskiy (5):
vhost-user-blk: simplify and fix
Let's not care about what was changed and update the whole config,
reasons:
1. config->geometry should be updated together with capacity, so we fix
a bug.
2. Vhost-user protocol doesn't say anything about config change
limitation. Silent ignore of changes doesn't seem to be correct.
3.
This "hotpluggable" here is misleading. Actually we check is object a
device or not. Let's drop the word.
Suggested-by: Markus Armbruster
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Markus Armbruster
---
system/qdev-monitor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Here we just prepare for the following patch, making possible to report
GenericError as recommended.
This patch doesn't aim to prevent further use of DeviceNotFound by
future interfaces:
- find_device_state() is used in blk_by_qdev_id() and qmp_get_blk()
functions, which may lead to spread
Um maybe?
>From what I've read so far it doesn't seem the format is compromised but it
certainly seems like a concerted attempt to subvert an upstream. However a
knee-jerk jump to another format might be premature without carefully
considering if other upstreams have been targeted.
I guess zstd
On Fri, Mar 29, 2024 at 02:36:14PM +0800, Shiyang Ruan wrote:
> Currently driver only traces cxl events, poison injection (for both vmem
> and pmem type) on cxl memdev is silent. OS needs to be notified then it
> could handle poison range in time. Per CXL spec, the device error event
> could be
Alison Schofield wrote:
[..]
> Upon receipt of that new poison list, call memory_failture_queue()
> on *any* poison in a mapped space. Is that OK? Can we call
> memory_failure_queue() on any and every poison report that is in
> HPA space regardless of whether it first came to us through a GMER?
>
On Fri, Mar 29, 2024 at 02:36:12PM +0800, Shiyang Ruan wrote:
> Poison injection from debugfs is silent too. Add calling
> cxl_mem_report_poison() to make it able to do memory_failure().
Curious as to why it is silent? Will a GMER poison event occur
and trigger the path to report it via
For more info, see
https://lwn.net/ml/oss-security/20240329155126.kjjfduxw2yrlx...@awork3.anarazel.de/
but, essentially, xz was backdoored and it seems like upstream was directly
responsible for this.
Based on this, should we switch our distribution from bz2+xz to bz2+zstd or
bz2+lzip?
Thanks,
On 3/29/24 05:04, Don Porter wrote:
From: Austin Clements
The E1000 debug messages are very useful for developing drivers, so
this introduces an E1000_DEBUG environment variable that lets the
debug flags be set without recompiling QEMU.
Signed-off-by: Austin Clements
[geo...@ldpreload.com:
Add a function to change the settings of the
serial connection.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
---
hw/char/stm32l4x5_usart.c | 98 +++
hw/char/trace-events | 1 +
2 files changed, 99 insertions(+)
Add the USART to the SoC and connect it to the other implemented devices.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
---
docs/system/arm/b-l475e-iot01a.rst | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 82
Test:
- read/write from/to the usart registers
- send/receive a character/string over the serial port
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build| 4 +-
tests/qtest/stm32l4x5_usart-test.c | 325 +
2 files
Add the basic infrastructure (register read/write, type...)
to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART
of the STM32L4x5 to deduplicate code and enable the
implementation of different behaviors depending on the type.
Signed-off-by: Arnaud Minier
Implement the ability to read and write characters to the
usart using the serial port.
The character transmission is based on the
cmsdk-apb-uart implementation.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
---
hw/char/stm32l4x5_usart.c | 140
This patch adds the STM32L4x5 USART
(Universal Synchronous/Asynchronous Receiver/Transmitter)
device and is part of a series implementing the
STM32L4x5 with a few peripherals.
It implements the necessary functionalities to receive/send
characters over the serial port, which are useful to
On Fri, Mar 29, 2024 at 02:36:08PM +0800, Shiyang Ruan wrote:
> Changes:
> RFCv1 -> RFCv2:
> 1. update commit message of PATCH 1
> 2. use memory_failure_queue() instead of MCE
> 3. also report poison in debugfs when injecting poison
> 4. correct DPA->HPA logic:
> find memdev's endpoint
There is a bug when setting the RSS options in virtio_net that can break
the whole machine, getting the kernel into an infinite loop.
Running the following command in any QEMU virtual machine with virtionet
will reproduce this problem:
# ethtool -X eth0 hfunc toeplitz
This is how the
Hi Paolo,
On Fri, Mar 29, 2024 at 12:10:17PM +0100, Paolo Bonzini wrote:
> Date: Fri, 29 Mar 2024 12:10:17 +0100
> From: Paolo Bonzini
> Subject: Re: [RFC] util/error-report: Add "error: " prefix for error-level
> report
>
> On Fri, Mar 29, 2024 at 10:37 AM wrote:
> > > This was done in the
Hi all,
I am a CS professor (and first time contributor) and have been using
qemu in my courses for over a decade, especially a course that asks
students to write major pieces of an OS kernel from starter code.
I have some patches, originally from Austin Clements at MIT, that I
have found useful
From: Austin Clements
The E1000 debug messages are very useful for developing drivers, so
this introduces an E1000_DEBUG environment variable that lets the
debug flags be set without recompiling QEMU.
Signed-off-by: Austin Clements
[geo...@ldpreload.com: Rebased on top of 2.9.0]
Signed-off-by:
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-common-ssh.c | 50 +++
qga/commands-common-ssh.h | 10
qga/commands-posix-ssh.c | 47 +---
qga/meson.build | 1 +
4 files changed, 62 insertions(+),
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-windows-ssh.c | 789 +
qga/commands-windows-ssh.h | 26 ++
qga/meson.build| 5 +-
qga/qapi-schema.json | 17 +-
4 files changed, 826 insertions(+), 11 deletions(-)
create mode
From: aidaleuc
This patch aims to implement guest-ssh-add-authorized-keys,
guest-ssh-remove-authorized-keys, and guest-ssh-get-authorized-keys
for Windows. This PR is based on Microsoft's OpenSSH implementation
https://github.com/PowerShell/Win32-OpenSSH. The guest agents
will support
Hello Zhenzhong,
On 3/28/24 04:06, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v1 01/11] Introduce a common abstract struct
HostIOMMUDevice
Hello Zhenzhong,
On 3/19/24 12:58, Duan, Zhenzhong wrote:
Hi Cédric,
-Original
Change the board revision number and RAM size to 1Gb on 32-bit hosts.
On these systems, RAM has a 2047 MB limit and this breaks the tests.
Fixes: 7785e8ea2204 ("hw/arm: Introduce Raspberry PI 4 machine")
Signed-off-by: Cédric Le Goater
---
hw/arm/raspi4b.c | 4
1 file changed, 4
Successed two stage translation, but failed pmp check can cause guest
page fault instead of regular page fault.
In case of execution ld instuction in VS mode we can
face situation when two stages of translation was passed successfully,
and if PMP check was failed first_stage_error variable going
Hi,
The KVM/QEMU community call is at:
https://meet.jit.si/kvmcallmeeting
@
2/4/2024 14:00 UTC
Are there any agenda items for the sync-up?
Alex maintains the invite on our Linaro project calendar here:
Hi Markus,
On 26/3/24 14:28, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
Each target use a common template for qmp_query_cpu_definitions().
Extract it as generic_query_cpu_definitions(), keeping the
target-specific implementations as the following SysemuCPUOps
handlers:
-
On Thu, 28 Mar 2024 07:40:14 -0500, Eric Blake wrote:
> On Mon, Mar 25, 2024 at 05:18:50PM +0800, zhuyangyang via wrote:
> > If g_main_loop_run()/aio_poll() is called in the coroutine context,
> > the pending coroutine may be woken up repeatedly, and the co_queue_wakeup
> > may be disordered.
> >
On Thu, Mar 28, 2024 at 11:07 AM Zhao Liu wrote:
>
> Hi Paolo,
>
> Just meet typos when compiling ;-)
Thank you very much! Fixed both.
Paolo
> On Mon, Mar 25, 2024 at 03:14:20PM +0100, Paolo Bonzini wrote:
> > Date: Mon, 25 Mar 2024 15:14:20 +0100
> > From: Paolo Bonzini
> > Subject: [PATCH
On 29/3/24 12:39, Artem Chernyshev wrote:
In xen_evtchn_soft_reset() variable flush_kvm_routes can
be used before being initialized.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Oleg Sviridov
Signed-off-by: Artem Chernyshev
---
hw/i386/kvm/xen_evtchn.c |
On 29/3/24 11:56, Cédric Le Goater wrote:
This allows to report more precise errors in the migration handler
dirty_bitmap_save_setup().
Suggested-by Vladimir Sementsov-Ogievskiy
Signed-off-by: Cédric Le Goater
---
To apply on top of :
Hi Cédric, Thomas,
On 29/3/24 10:27, Cédric Le Goater wrote:
The test mangles the GPIO address and the pin number in the
qtest_add_data_func data parameter. Doing so, it assumes that the host
pointer size is always 64-bit, which breaks on 32-bit :
../tests/qtest/stm32l4x5_gpio-test.c: In
Hi Max,
On 29/3/24 07:31, Max Filippov wrote:
- target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
on xtensa and thus need to use tswap32
- target_msqid_ds::msg_*time field pairs are reversed on big-endian
xtensa
Please split in 2 distinct patches.
Both issues
In xen_evtchn_soft_reset() variable flush_kvm_routes can
be used before being initialized.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Oleg Sviridov
Signed-off-by: Artem Chernyshev
---
hw/i386/kvm/xen_evtchn.c | 2 +-
1 file changed, 1 insertion(+), 1
I am trying to write a custom NVMe driver and I tested it with QEMU
NVMe emulation on Fedora 39.
I have not tried to set shadow buffers, even though the controller
reports such support.
What I see is the following:
1. Only the first command in the Admin queue generates interrupt and
completes
Please ignore. The issue was on my side.
On Fri, Mar 29, 2024 at 1:07 PM Constantine Gavrilov
wrote:
>
> I am trying to write a custom NVMe driver and I tested it with QEMU
> NVMe emulation on Fedora 39.
> I have not tried to set shadow buffers, even though the controller
> reports such support.
On 29/3/24 05:34, Harsh Prateek Bora wrote:
Check for flag bit in H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE need to use
bitwise NOT operator to ensure no other flag bits are set.
Reported by Coverity as CID 1540008, 1540009.
Reported-by: Peter Maydell
Signed-off by: Harsh Prateek Bora
---
The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
https://github.com/T-head-Semi/thead-extension-spec/pull/46
An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMaee is not
On 29.03.24 13:53, Cédric Le Goater wrote:
Hello Vladimir,
On 3/29/24 10:32, Vladimir Sementsov-Ogievskiy wrote:
On 20.03.24 09:49, Cédric Le Goater wrote:
diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirty-bitmap.c
index
There was an issue with Qemu build with "--disable-system".
The traces could be generated and the build fails.
The traces were 'cut out' for previous patches, and overall,
the 'system' source set should be used like in pre-'eBPF blob' patches.
Signed-off-by: Andrew Melnychenko
---
On Fri, Mar 29, 2024 at 10:37 AM wrote:
> > This was done in the context of inheriting the original error_report()
> > interface without the prefix style. And it was also useful to have a
> > means of error handling, such as exit(), when error occurs, so that the
> > error message - the most
This allows to report more precise errors in the migration handler
dirty_bitmap_save_setup().
Suggested-by Vladimir Sementsov-Ogievskiy
Signed-off-by: Cédric Le Goater
---
To apply on top of :
https://lore.kernel.org/qemu-devel/20240320064911.545001-1-...@redhat.com/
Hello Vladimir,
On 3/29/24 10:32, Vladimir Sementsov-Ogievskiy wrote:
On 20.03.24 09:49, Cédric Le Goater wrote:
diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirty-bitmap.c
index
2708abf3d762de774ed294d3fdb8e56690d2974c..542a8c297b329abc30d1b3a205d29340fa59a961
100644
---
On Fri, Mar 29, 2024 at 03:20:59PM +0800, Jason Wang wrote:
> On Fri, Mar 29, 2024 at 3:07 PM Chen, Jiqian wrote:
> >
> > On 2024/3/28 20:36, Michael S. Tsirkin wrote:
> > +}
> > +
> > static void virtio_pci_bus_reset_hold(Object *obj)
> > {
> > PCIDevice *dev =
On Fri, Mar 29, 2024 at 4:00 PM Chen, Jiqian wrote:
>
> On 2024/3/29 15:20, Jason Wang wrote:
> > On Fri, Mar 29, 2024 at 3:07 PM Chen, Jiqian wrote:
> >>
> >> On 2024/3/28 20:36, Michael S. Tsirkin wrote:
> >> +}
> >> +
> >> static void virtio_pci_bus_reset_hold(Object *obj)
>
Hi Zhijian,
On 29/3/24 02:53, Zhijian Li (Fujitsu) wrote:
On 28/03/2024 23:01, Peter Xu wrote:
On Thu, Mar 28, 2024 at 11:18:04AM -0300, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
The whole RDMA subsystem was deprecated in commit e9a54265f5
("hw/rdma: Deprecate the pvrdma device
On 28/3/24 16:39, Thomas Huth wrote:
On 28/03/2024 16.12, Mark Cave-Ayland wrote:
On 27/03/2024 16:54, Philippe Mathieu-Daudé wrote:
Per Daniel suggestion [*]:
> isapc could arguably be restricted to just 32-bit CPU models,
> because we should not need it to support any feature that
On 28/3/24 19:45, BALATON Zoltan wrote:
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
acpi_setup() caller knows about the machine state, so pass
it as argument to avoid a qdev_get_machine() call.
We already resolved X86_MACHINE(pcms) as 'x86ms' so use the
latter.
Signed-off-by: Philippe
Am 28. März 2024 14:09:52 UTC schrieb Mark Cave-Ayland
:
>On 27/03/2024 07:09, Gerd Hoffmann wrote:
>
>> On Tue, Mar 26, 2024 at 01:30:48PM +, Mark Cave-Ayland wrote:
>>> Heh I've actually been using isapc over the past couple of weeks to fire up
>>> some old programs in a Windows 3 VM :)
On 08.03.24 18:51, Fiona Ebner wrote:
Useful to make discard-source work in the context of backup fleecing
when the fleecing image has a larger granularity than the backup
target.
Backup/block-copy will use at least this granularity for copy operations
and in particular, discard requests to the
On 08.03.24 18:51, Fiona Ebner wrote:
Useful to make discard-source work in the context of backup fleecing
when the fleecing image has a larger granularity than the backup
target.
Copy-before-write operations will use at least this granularity and in
particular, discard requests to the source
From: Tim Wiederhake
The commit 642258c6c7 ("kvm: add kvmclock to its second bit") gave the
old and new kvmclocks with the same name "kvmclock", to facilitate user
to set/unset the feature bits for both 2 kvmclock features together.
This could work because:
* QEMU side:
-
From: Zhao Liu
MSR_KVM_SYSTEM_TIME and MSR_KVM_WALL_CLOCK are attached with the (old)
kvmclock feature (KVM_FEATURE_CLOCKSOURCE).
So, just save/load them only when kvmclock (KVM_FEATURE_CLOCKSOURCE) is
enabled.
Signed-off-by: Zhao Liu
---
target/i386/kvm/kvm.c | 12
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