[PATCH] Fixes rtl8139 driver for old kernels.

Old linux kernel rtl8139 drivers (ex. debian 2.1) uses outb to set the rx mode for RxConfig. Unfortunatelly qemu does not support outb for RxConfig. Signed-off-by: Hans --- hw/net/rtl8139.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/net/rtl8139.c

[PATCH] mips64el-softmmu: Enable MTTCG

y TARGET_NEED_FDT=y --- base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 change-id: 20240511-mips_mttcg-47a6b19074b3 Best regards, -- Jiaxun Yang

[PATCH v11 04/10] virtio-gpu: Don't require udmabuf when blobs and virgl are enabled

The udmabuf usage is mandatory when virgl is disabled and blobs feature enabled in the Qemu machine configuration. If virgl and blobs are enabled, then udmabuf requirement is optional. Since udmabuf isn't widely supported by a popular Linux distros today, let's relax the udmabuf requirement for

[PATCH v11 02/10] virtio-gpu: Use pkgconfig version to decide which virgl features are available

New virglrerenderer features were stabilized with release of v1.0.0. Presence of symbols in virglrenderer.h doesn't guarantee ABI compatibility with pre-release development versions of libvirglerender. Use virglrenderer version to decide reliably which virgl features are available. Signed-off-by:

[PATCH v11 00/10] Support blob memory and venus on qemu

Hello, This series enables Vulkan Venus context support on virtio-gpu. All virglrender and almost all Linux kernel prerequisite changes needed by Venus are already in upstream. For kernel there is a pending KVM patchset that fixes mapping of compound pages needed for DRM drivers using TTM [1],

[PATCH v11 06/10] virtio-gpu: Support blob scanout using dmabuf fd

From: Robert Beckett Support displaying blob resources by handling SET_SCANOUT_BLOB command. Signed-by: Antonio Caggiano Signed-off-by: Robert Beckett Signed-off-by: Huang Rui Reviewed-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko --- hw/display/virtio-gpu-virgl.c | 109

[PATCH v11 08/10] virtio-gpu: Handle resource blob commands

From: Antonio Caggiano Support BLOB resources creation, mapping and unmapping by calling the new stable virglrenderer 0.10 interface. Only enabled when available and via the blob config. E.g. -device virtio-vga-gl,blob=true Signed-off-by: Antonio Caggiano Signed-off-by: Xenia Ragiadakou

[PATCH v11 07/10] virtio-gpu: Support suspension of commands processing

Check whether command processing has been finished; otherwise, stop processing commands and retry the command again next time. This allows us to support asynchronous execution of non-fenced commands needed for unmapping host blobs safely. Suggested-by: Akihiko Odaki Signed-off-by: Dmitry

[PATCH v11 10/10] virtio-gpu: Support Venus context

From: Antonio Caggiano Request Venus when initializing VirGL and if venus=true flag is set for virtio-gpu-gl device. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui Signed-off-by: Dmitry Osipenko --- hw/display/virtio-gpu-gl.c | 2 ++ hw/display/virtio-gpu-virgl.c | 22

[PATCH v11 05/10] virtio-gpu: Add virgl resource management

From: Huang Rui In a preparation to adding host blobs support to virtio-gpu, add virgl resource management that allows to retrieve resource based on its ID and virgl resource wrapper on top of simple resource that will be contain fields specific to virgl. Signed-off-by: Huang Rui Reviewed-by:

[PATCH v11 03/10] virtio-gpu: Support context-init feature with virglrenderer

From: Huang Rui Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init feature flags. Expose this feature and support creating virglrenderer context with flags using context_id if libvirglrenderer is new enough. Originally-by: Antonio Caggiano Signed-off-by: Huang Rui

[PATCH v11 09/10] virtio-gpu: Register capsets dynamically

From: Pierre-Eric Pelloux-Prayer virtio_gpu_virgl_get_num_capsets will return "num_capsets", but we can't assume that capset_index 1 is always VIRGL2 once we'll support more capsets, like Venus and DRM capsets. Register capsets dynamically to avoid that problem. Signed-off-by: Pierre-Eric

[PATCH v11 01/10] virtio-gpu: Unrealize GL device

Even though GL GPU doesn't support hotplugging today, free virgl resources when GL device is unrealized. For consistency. Signed-off-by: Dmitry Osipenko --- hw/display/virtio-gpu-gl.c | 11 +++ hw/display/virtio-gpu-virgl.c | 9 + include/hw/virtio/virtio-gpu.h | 1 + 3

Re: [PATCH RESEND] target/riscv/cpu.c: fix Zvkb extension config

Note: This patch should also backport to stable-v8.2. > On May 11, 2024, at 19:26, Yangyu Chen wrote: > > This code has a typo that writes zvkb to zvkg, causing users can't > enable zvkb through the config. This patch gets this fixed. > > Signed-off-by: Yangyu Chen > Fixes: ea61ef7097d0

Re: [PATCH RESEND] target/riscv/cpu.c: fix Zvkb extension config

Reviewed-by: Max Chou Max On 2024/5/11 7:26 PM, Yangyu Chen wrote: This code has a typo that writes zvkb to zvkg, causing users can't enable zvkb through the config. This patch gets this fixed. Signed-off-by: Yangyu Chen Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to

Re: [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

On 2024/5/10 14:58, Fea.Wang wrote: Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 ++ 2 files

Re: [PATCH 2/5] target/riscv: Support the version for ss1p13

On 2024/5/10 14:58, Fea.Wang wrote: Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files

Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

On 2024/5/11 18:10, Alexey Baturo wrote: From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++

Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

On 2024/5/11 18:10, Alexey Baturo wrote: From: Alexey Baturo Hi, It looks like Pointer Masking spec has reached v1.0 and been frozen, rebasing on riscv-to-apply.next branch and resubmitting patches. Hi, any change from v0.8 to v1.0? Regards, Weiwei Li Thanks. [v8]: Rebasing patches

Re: [PATCH RESEND] target/riscv/cpu.c: fix Zvkb extension config

On 2024/5/11 19:26, Yangyu Chen wrote: This code has a typo that writes zvkb to zvkg, causing users can't enable zvkb through the config. This patch gets this fixed. Signed-off-by: Yangyu Chen Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")

Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

On 2024/5/10 14:58, Fea.Wang wrote: From: Jim Shu Public the conversion function of priv_spec and string in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h

[PATCH] target/riscv/cpu.c: fix Zvkb extension config

This code has a typo that writes zvkb to zvkg, causing users can't enable zvkb through the config. This patch gets this fixed. Signed-off-by: Yangyu Chen Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions") --- target/riscv/cpu.c | 2 +- 1 file changed, 1

RE: [PATCH v6 5/7] migration/multifd: implement initialization of qpl compression

> -Original Message- > From: Fabiano Rosas > Sent: Saturday, May 11, 2024 4:45 AM > To: Liu, Yuan1 ; pet...@redhat.com > Cc: qemu-devel@nongnu.org; Liu, Yuan1 ; Zou, Nanhai > > Subject: Re: [PATCH v6 5/7] migration/multifd: implement initialization of > qpl compression > > Yuan Liu

RE: [PATCH v6 5/7] migration/multifd: implement initialization of qpl compression

> -Original Message- > From: Fabiano Rosas > Sent: Saturday, May 11, 2024 4:53 AM > To: Liu, Yuan1 ; pet...@redhat.com > Cc: qemu-devel@nongnu.org; Liu, Yuan1 ; Zou, Nanhai > > Subject: Re: [PATCH v6 5/7] migration/multifd: implement initialization of > qpl compression > > Yuan Liu

[PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state

A misalignment for sve_vl, plus add a bit more space on the left for the ZA[n] field name. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- risu_reginfo_aarch64.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git

[PATCH 11/17] aarch64: Add support for ZA storage

Require NVL == SVL on startup, to make it easier to manage reginfo. Most of the time PSTATE.SM would be active with PSTATE.ZA anyway, for any non-trivial SME testing. Extend saved storage only when PSTATE.ZA is active. Use a carefully reserved uint16_t for saving SVCR. Reviewed-by: Peter Maydell

[PATCH 06/17] ppc64: Clean register values in reginfo_init

Smash the stack and thread pointers to deadbeef, as is common for the other architectures. This allows us to drop these special cases within reginfo_is_eq and reginfo_dump_mismatch. Do not copy the unused special registers that are packed into gregs[]. Most of these are related to system

[PATCH 15/17] risu: Allow use of ELF test files

By using elf files, we make it easier to disassemble the test file, to match comparison failures to code. Signed-off-by: Richard Henderson --- risu.c | 53 + 1 file changed, 53 insertions(+) diff --git a/risu.c b/risu.c index c28b4a5..e3845f6

[PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq

The functions results are more naturally boolean. Signed-off-by: Richard Henderson --- risu_reginfo_aarch64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 55a9ef6..6323eef 100644 --- a/risu_reginfo_aarch64.c +++

[PATCH 03/17] Standardize reginfo_dump_mismatch printing

Hoist the "master vs apprentice" label to apprentice(), since we will want different labels for dumping. Remove all of the "mismatch" text from reginfo_dump_mismatch -- just print "vs". Signed-off-by: Richard Henderson --- risu.h | 4 ++-- risu.c | 1 +

[PATCH 12/17] aarch64: Trivial SME test

Signed-off-by: Richard Henderson --- test_sme_aarch64.s | 63 ++ 1 file changed, 63 insertions(+) create mode 100644 test_sme_aarch64.s diff --git a/test_sme_aarch64.s b/test_sme_aarch64.s new file mode 100644 index 000..acd08d4 --- /dev/null +++

[PATCH 05/17] Remove return value from reginfo_dump

No uses actually checked the error indication. Even if we wanted to check ferror on the stream, we should do that generically rather than per arch. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- risu.h | 4 ++-- risu_reginfo_aarch64.c | 8 +++-

[PATCH 08/17] ppc64: Simplify reginfo_is_eq

Since we now only copy into reginfo exactly what we want to compare, and since we zero all unused padding and reserved space, we need not enumerate each field for comparison, but defer to memcmp. Signed-off-by: Richard Henderson --- risu_reginfo_ppc64.c | 31 +-- 1

[PATCH 00/17] RISU misc updates

Some of these have been sitting on a branch for a couple of years. Except perhaps the first, which I assume to be some sort of odd build error from the time, they still seem reasonable. There are some updates for SME1, but not yet the ZT register for SME2. I'll get to that later after I've done

[PATCH 09/17] ppc64: Clean up reginfo_dump

Dump only the registers that we copied in reginfo_init. Improve the formatting and layout of what we do dump. Signed-off-by: Richard Henderson --- risu_reginfo_ppc64.c | 51 ++-- 1 file changed, 21 insertions(+), 30 deletions(-) diff --git

[PATCH 17/17] Build elf test cases instead of raw binaries

Signed-off-by: Richard Henderson --- Makefile | 19 ++- test.ld| 12 test_aarch64.s | 4 ++-- test_arm.s | 16 +++- test_i386.S| 4 +++- 5 files changed, 38 insertions(+), 17 deletions(-) create mode 100644 test.ld diff --git

[PATCH 16/17] configure: Enable loongarch64

Signed-off-by: Richard Henderson --- configure | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 2f7c580..39275a2 100755 --- a/configure +++ b/configure @@ -54,6 +54,8 @@ guess_arch() { ARCH="arm" elif check_define __i386__ ||

[PATCH 02/17] Fix load_image error check for mmap

mmap does not return null on failure, but MAP_FAILED. Signed-off-by: Richard Henderson --- risu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/risu.c b/risu.c index 36fc82a..6b6295c 100644 --- a/risu.c +++ b/risu.c @@ -362,10 +362,9 @@ static void load_image(const

[PATCH 13/17] Use bool for reginfo_is_eq

The function result is more naturally boolean. Signed-off-by: Richard Henderson --- risu.h | 4 ++-- risu_reginfo_aarch64.c | 4 ++-- risu_reginfo_arm.c | 4 ++-- risu_reginfo_i386.c| 4 ++-- risu_reginfo_loongarch64.c | 4 ++-- risu_reginfo_m68k.c

[PATCH 04/17] Add --fulldump and --diffdup options

These allow the inspection of the trace files. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- risu.c | 117 + 1 file changed, 102 insertions(+), 15 deletions(-) diff --git a/risu.c b/risu.c index 9c31b8c..c28b4a5 100644

[PATCH 07/17] ppc64: Compare all bits of CCR

There are 32 bits in this register, and they are all valid comparision destinations. Signed-off-by: Richard Henderson --- risu_reginfo_ppc64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 67ea3ce..109b87b 100644 ---

[PATCH 01/17] ppc64: Fix include order

Signed-off-by: Richard Henderson --- risu_ppc64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/risu_ppc64.c b/risu_ppc64.c index 9df8d58..62cf6aa 100644 --- a/risu_ppc64.c +++ b/risu_ppc64.c @@ -11,9 +11,8 @@ * based on Peter Maydell's risu_arm.c

[PATCH RESEND] target/riscv/cpu.c: fix Zvkb extension config

This code has a typo that writes zvkb to zvkg, causing users can't enable zvkb through the config. This patch gets this fixed. Signed-off-by: Yangyu Chen Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions") Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c

Re: [PATCH 1/1] tests/fp/meson: don't build fp-bench test if fenv.h is missing

On Sat, May 11, 2024 at 12:25 PM Richard Henderson wrote: > > On 5/11/24 12:11, Dario Binacchi wrote: > > Gentle ping. > > Gentle reminder that I strongly suspect that your buildroot is corrupt. > There *should* be a present. I don't think so. In fact, the patch has already been merged into

Re: hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT

On Thu, 9 May 2024 at 19:17, Cord Amfmgm wrote: > > > > On Thu, May 9, 2024 at 12:48 PM Peter Maydell > wrote: >> >> On Wed, 8 May 2024 at 16:29, Cord Amfmgm wrote: >> > On Wed, May 8, 2024 at 3:45 AM Thomas Huth wrote: >> >> >> >> Your Signed-off-by line does not match the From: line ...

Re: [PATCH 1/1] tests/fp/meson: don't build fp-bench test if fenv.h is missing

On 5/11/24 12:11, Dario Binacchi wrote: Gentle ping. Gentle reminder that I strongly suspect that your buildroot is corrupt. There *should* be a present. r~ Thanks, Dario On Wed, May 1, 2024 at 4:17 PM Dario Binacchi wrote: Hello Richard, On Wed, May 1, 2024 at 3:31 PM Richard

[PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git

[PATCH v9 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h

[PATCH v9 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alistair Francis

[PATCH v9 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e350e9bd8..b3b3a6275f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@

[PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 5 target/riscv/cpu_helper.c | 58 +++ 2 files changed, 63 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

Re: [PATCH 1/1] tests/fp/meson: don't build fp-bench test if fenv.h is missing

Gentle ping. Thanks, Dario On Wed, May 1, 2024 at 4:17 PM Dario Binacchi wrote: > > Hello Richard, > > On Wed, May 1, 2024 at 3:31 PM Richard Henderson > wrote: > > > > On 5/1/24 05:18, Dario Binacchi wrote: > > > Hello Richard, > > > > > > On Tue, Apr 30, 2024 at 8:15 PM Richard Henderson > >

[PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

From: Alexey Baturo Hi, It looks like Pointer Masking spec has reached v1.0 and been frozen, rebasing on riscv-to-apply.next branch and resubmitting patches. Thanks. [v8]: Rebasing patches on current qemu branch and resubmitting them. [v7]: I'm terribly sorry, but previous rebase went

[PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

Re: [PATCH 3/4] virtio-gpu: use a VMState variant for the scanout field

Hi Peter On Fri, May 10, 2024 at 9:33 PM Peter Xu wrote: > > Hi, Marc-André, > > On Fri, May 10, 2024 at 12:39:34PM +0400, Marc-André Lureau wrote: > > Since we don't have per VMSD version information on the wire, nested > > struct versioning is quite limited and cumbersome. I am not sure it > >