On Feb 11 17:27, Alex Bennée wrote:
> Aaron Lindsay writes:
> > On Feb 05 15:03, Alex Bennée wrote:
> >> Aaron Lindsay writes:
> >> > Assuming you're right that TCG is detecting "a io_readx/io_writex when
> >> > ->can_do_io is not true", c
On Feb 05 15:03, Alex Bennée wrote:
> Aaron Lindsay writes:
> > Assuming you're right that TCG is detecting "a io_readx/io_writex when
> > ->can_do_io is not true", could we detect this case when it occurs and
> > omit the instruction callbacks for the re-transla
On Feb 05 15:03, Alex Bennée wrote:
> I'll see what Richard thinks. I must admit I thought can_do_io was only
> an issue for -icount modes but I think the real picture is slightly more
> confused than that.
I am using -icount. I apologize for not including that originally - I
didn't realize it
On Feb 05 11:19, Alex Bennée wrote:
> Aaron Lindsay writes:
>
> > For the below output, I've got a plugin which registers a callback via
> > `qemu_plugin_register_vcpu_insn_exec_cb` for each instruction executed.
> > I've enabled `-d in_asm` and added prints in
On Jan 29 22:23, Aaron Lindsay wrote:
> I appear to be seeing that if I register a callback for an instruction
> via `qemu_plugin_register_vcpu_insn_exec_cb` I receive a callback even
> if the instruction faults.
I was wrong about what I was seeing - I made some false assumpti
As feature flags are added or removed, the meanings of bits in the
`features` field can change between QEMU versions, causing migration
failures. Additionally, migrating the field is not useful because it is
a constant function of the CPU being used.
Signed-off-by: Aaron Lindsay
Suggested
On Feb 03 15:26, Peter Maydell wrote:
> On Wed, 3 Feb 2021 at 15:11, Dr. David Alan Gilbert
> wrote:
> > It's interesting that on x86 we've got a longterm request to *add* cpu
> > features to the stream to detect screwups caused by using mismatched
> > CPUs; so it's not necessarily a bad idea to
On Feb 03 10:01, Peter Maydell wrote:
> On Wed, 3 Feb 2021 at 04:01, Aaron Lindsay
> wrote:
> > Note that I'm using qemu-system-aarch64 with -loadvm.
>
> You don't say what machine type and command line you're using. Strictly,
> Strictly speaking, the intended guarantee
Hello,
I'm attempting to restore an AArch64 snapshot taken on QEMU 4.1.0 on
QEMU 5.2.0, using system mode. My previous impression, possibly from
https://wiki.qemu.org/Features/Migration/Troubleshooting#Basics was that
this ought to work:
> Note that QEMU supports migrating forward between QEMU
On Jan 29 22:23, Aaron Lindsay wrote:
> 1. Is this considered a bug or a "feature"?
> 2.a. If a bug, is there a good way to detect this from inside the
>tcg/plugin infrastructure and avoid calling the callback for the
>faulting execution of the instruction
Hello,
I appear to be seeing that if I register a callback for an instruction
via `qemu_plugin_register_vcpu_insn_exec_cb` I receive a callback even
if the instruction faults. For example, if an instruction attempts to
load memory from a page which isn't currently mapped by the OS, I
receive two
On Jan 07 16:49, Alex Bennée wrote:
>
> Aaron Lindsay writes:
>
> > On Dec 08 14:44, Aaron Lindsay wrote:
> >> On Dec 08 17:56, Alex Bennée wrote:
> >> > Aaron Lindsay writes:
> >> > > On Dec 08 12:17, Alex Bennée wrote:
> >> > &g
On Dec 08 14:44, Aaron Lindsay wrote:
> On Dec 08 17:56, Alex Bennée wrote:
> > Aaron Lindsay writes:
> > > On Dec 08 12:17, Alex Bennée wrote:
> > >> Aaron Lindsay writes:
> > >> Memory is a little trickier because you can't know at any point if a
On Dec 08 17:56, Alex Bennée wrote:
> Aaron Lindsay writes:
> > On Dec 08 12:17, Alex Bennée wrote:
> >> For registers I think there needs to be some re-factoring of QEMU's
> >> internals to do it cleanly. Currently we have each front-end providing
> >
On Dec 08 17:56, Alex Bennée wrote:
> Aaron Lindsay writes:
> > On Dec 08 12:17, Alex Bennée wrote:
> >> Aaron Lindsay writes:
> >> Memory is a little trickier because you can't know at any point if a
> >> given virtual address is actually mapped to real
On Dec 08 12:17, Alex Bennée wrote:
> Aaron Lindsay writes:
>
> > I'm trying to migrate to using the new plugin interface. I see the
> > following in include/qemu/qemu-plugin.h:
> >
> >> enum qemu_plugin_cb_flags {
> >> QEMU_PLUGIN_CB_NO_REGS,
I'm trying to migrate to using the new plugin interface. I see the
following in include/qemu/qemu-plugin.h:
> enum qemu_plugin_cb_flags {
> QEMU_PLUGIN_CB_NO_REGS, /* callback does not access the CPU's regs */
> QEMU_PLUGIN_CB_R_REGS, /* callback reads the CPU's regs */
>
On Aug 24 17:33, Peter Maydell wrote:
> On Fri, 18 Jan 2019 at 14:58, Peter Maydell wrote:
> >
> > From: Aaron Lindsay
> >
> > Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only
> > return 'true' if the specified counter is enabled and n
This check was backwards when introduced in commit
033614c47de78409ad3fb39bb7bd1483b71c6789:
target/arm: Filter cycle counter based on PMCCFILTR_EL0
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c
-by: Aaron Lindsay
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index dc9c29f998..c69a2baf1d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2269,13 +2269,13 @@ static const ARMCPRegInfo
On Feb 25 17:08, Peter Maydell wrote:
> On Fri, 1 Feb 2019 at 16:07, Peter Maydell wrote:
> >
> > From: Aaron Lindsay OS
> >
> > Whenever we notice that a counter overflow has occurred, send an
> > interrupt. This is made more reliable with the addition of
On Oct 17 14:16, Alex Bennée wrote:
> It's quite common to have a mini comment inside braces to acknowledge
> we know it's empty. Expand the inline detection to allow closing
> braces before the end of line.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Aaron Lindsay
On Oct 18 16:54, Alex Bennée wrote:
>
> Aaron Lindsay OS writes:
>
> > On Oct 17 14:15, Alex Bennée wrote:
> >> +const char *target_name;
> >> +/* is this a full system emulation? */
> >> +bool system_emulation;
> >
> &g
On Oct 17 14:16, Alex Bennée wrote:
> Having the plugins grab stdout and spew stuff there is a bit ugly and
> certainly makes the tests look ugly. Provide a hook back into QEMU
> which can be redirected as needed.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Aaron Lindsay
On Oct 17 14:15, Alex Bennée wrote:
> This provides a limited amount of info to plugins about the guest
> system that will allow them to make some additional decisions on
> setup.
>
> Signed-off-by: Alex Bennée
>
> ---
> v6
> - split and move to pre example plugins
> - checkpatch fixes
>
On Sep 06 20:31, Alex Bennée wrote:
> Aaron Lindsay OS writes:
>
> > One thing I would find useful is the ability to access register values
> > during an execution-time callback. I think the easiest way to do that
> > generically would be to expose them via the
On Sep 06 20:52, Alex Bennée wrote:
>
> Markus Armbruster writes:
> > Please advise why TCG plugins don't undermine the GPL. Any proposal to
> > add a plugin interface needs to do that.
>
> I'm not sure what we can say about this apart from "ask your lawyer".
> I'm certainly not proposing we
On Aug 12 16:02, Peter Maydell wrote:
> On Mon, 12 Aug 2019 at 15:46, Aaron Lindsay OS via Qemu-arm
> wrote:
> >
> > Treat EM_AARCH64 as a valid value when checking the ELF's machine-type
> > header.
> >
> > Signed-off-by: Aaron Lindsay
> > ---
> &
Treat EM_AARCH64 as a valid value when checking the ELF's machine-type
header.
Signed-off-by: Aaron Lindsay
---
include/hw/elf_ops.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
index 690f9238c8..f12faa90a1 100644
--- a/include/hw
One thing I would find useful is the ability to access register values
during an execution-time callback. I think the easiest way to do that
generically would be to expose them via the gdb functionality (like
Pavel's earlier patchset did [1]), though that (currently) limits you to
the
On Jul 31 17:07, Alex Bennée wrote:
> + * Attempt to measure the amount of vectorisation that has been done
> + * on some code by counting classes of instruction. This is very much
> + * ARM specific.
I suspect some of my plugins will also be architecture-specific. Does it
make sense to have a
On Jul 31 17:06, Alex Bennée wrote:
> We need to keep a local per-cpu copy of the data as other threads may
> be running. We use a automatically growing array and re-use the space
> for subsequent queries.
[...]
> +bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
> +
On Jul 31 17:06, Alex Bennée wrote:
> Now we do all our checking and use a common EXCP_SEMIHOST for
> semihosting operations we can make helper code a lot simpler.
>
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - fix re-base conflicts
> - hoist EXCP_SEMIHOST check
> - comment cleanups
>
On Jul 01 16:00, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > - a way for a plugin to reset any instrumentation decisions made in the
> > past (essentially calls `tb_flush(cpu);` under the covers). We found
> > this critical for plugins which undergo state changes du
On Jun 28 21:52, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > To make sure I understand - you're implying that one such query will
> > return the PA from the guest's perspective, right?
>
> Yes - although it will be two queries:
>
> struct qemu_plugin_hwaddr *
On Jun 28 18:11, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > On Jun 14 18:11, Alex Bennée wrote:
> >> From: "Emilio G. Cota"
> >>
> >> Here the trickiest feature is passing the host address to
> >> memory callbacks that reques
On Jun 14 18:11, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Here the trickiest feature is passing the host address to
> memory callbacks that request it. Perhaps it would be more
> appropriate to pass a "physical" address to plugins, but since
> in QEMU host addr ~= guest physical, I'm
On Mar 22 17:23, Andrew Jones wrote:
> These functions are not used outside helper.c
>
> Signed-off-by: Andrew Jones
I'm late to the party, but:
Reviewed-by: Aaron Lindsay
> ---
> target/arm/cpu.h| 11 ---
> target/arm/helper.c | 4 ++--
> 2 files changed
gt; overflow")
> Signed-off-by: Andrew Jones
Reviewed-by: Aaron Lindsay
> ---
> target/arm/helper.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c8d3c213b6b7..fc73488f6cc0 100644
> --- a/target/a
On Mar 22 17:23, Andrew Jones wrote:
> cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
> them in ID_DFR0. Let's allow them to function. This also enables
> the pmu cpu property to work with these cpu types, i.e. we can
> now do '-cpu cortex-a15,pmu=off' to remove the pmu.
I'm a
This was introduced by
commit bf8d09694ccc07487cd73d7562081fdaec3370c8
target/arm: Don't clear supported PMU events when initializing PMCEID1
and identified by Coverity (CID 1398645).
Signed-off-by: Aaron Lindsay
Reported-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file changed
On Feb 19 14:33, Peter Maydell wrote:
> On Tue, 19 Feb 2019 at 14:23, Aaron Lindsay OS
> wrote:
> > I registered for a Coverity account and am awaiting approval for adding
> > me to the QEMU project so I can test this myself (let me know if this
> > isn't t
On Feb 14 17:55, Peter Maydell wrote:
> On Mon, 28 Jan 2019 at 18:11, Peter Maydell wrote:
> >
> > From: Aaron Lindsay OS
> >
> > A bug was introduced during a respin of:
> >
> > commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
> > t
This bug was introduced in:
commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
Signed-off-by: Aaron Lindsay
Reported-by: Laurent Desnogues
---
target/arm/helper.c | 8
1 file changed, 4 insertions(+), 4 deletions
On Feb 04 20:22, Laurent Desnogues wrote:
> Hello,
>
> On Tue, Dec 11, 2018 at 4:25 PM Aaron Lindsay
> wrote:
> >
> > Add arrays to hold the registers, the definitions themselves, access
> > functions, and logic to reset counters when PMCR.P is set. Update
> >
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 61 +
1
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/cpu.c| 12
target/arm/cpu.h
Most of this patchset implementing the PMU has been merged already, but
the interrupt-on-overflow behavior had some additional review comments.
This most recent version fixes a type promotion issue and adds Richard's
Reviewed-by's.
Aaron Lindsay (2):
target/arm: Send interrupts on PMU counter
On Jan 23 15:37, Richard Henderson wrote:
> On 1/23/19 1:32 PM, Aaron Lindsay OS wrote:
> > +uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
> > + INT64_MIN : INT32_MIN;
>
> With type promotion,
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12
target/arm/cpu.h| 10 +++
target/arm
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 61 +
1 file changed, 51 insertions
rg/archive/html/qemu-devel/2019-01/msg05996.html
Aaron Lindsay (2):
target/arm: Send interrupts on PMU counter overflow
target/arm: Add a timer to predict PMU counter overflow
target/arm/cpu.c| 12
target/arm/cpu.h| 10
target/arm/help
On Jan 18 14:13, Peter Maydell wrote:
> On Tue, 11 Dec 2018 at 15:20, Aaron Lindsay
> wrote:
> >
> > The ARM PMU implementation currently contains a basic cycle counter, but
> > it is often useful to gather counts of other events, filter them based
> > on exec
-by: Aaron Lindsay
---
target/arm/cpu.c| 3 +--
target/arm/cpu.h| 11 +--
target/arm/helper.c | 27 ---
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7e1f3dd637..d6da3f4fed 100644
--- a/target/arm
On Jan 18 07:26, Richard Henderson wrote:
> On 12/12/18 2:20 AM, Aaron Lindsay wrote:
> > Setup a QEMUTimer to get a callback when we expect counters to next
> > overflow and trigger an interrupt at that time.
> >
> > Signed-off-by: Aaron Lindsay
>
Ping, just in case this got buried over the holidays...
-Aaron
On Dec 11 10:20, Aaron Lindsay wrote:
> The ARM PMU implementation currently contains a basic cycle counter, but
> it is often useful to gather counts of other events, filter them based
> on execution mode, and/or be
On Dec 14 12:50, Emilio G. Cota wrote:
> On Fri, Dec 14, 2018 at 12:08:22 -0500, Emilio G. Cota wrote:
> > On Fri, Dec 14, 2018 at 15:57:32 +0000, Aaron Lindsay wrote:
> (snip)
> > > I added a function to the user-facing plugin API in my own version of
> > > Pavel'
On Dec 14 12:08, Emilio G. Cota wrote:
> On Fri, Dec 14, 2018 at 15:57:32 +0000, Aaron Lindsay wrote:
> > Emilio,
> >
> > First, thanks for putting this together - I think everyone doing this
> > sort of thing will benefit if we're able to agree on one upstream plugin
On Dec 14 10:57, Aaron Lindsay wrote:
> One thing I'd like to see is support for unregistering callbacks once
> they are registered.
By the way, I'm willing to work on this if we agree it sounds reasonable
and fits in with the rest of your implementation.
-Aaron
Emilio,
First, thanks for putting this together - I think everyone doing this
sort of thing will benefit if we're able to agree on one upstream plugin
interface.
One thing I'd like to see is support for unregistering callbacks once
they are registered. For instance, you can imagine that a plugin
Setup a QEMUTimer to get a callback when we expect counters to next
overflow and trigger an interrupt at that time.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12 +
target/arm/cpu.h| 8 +++
target/arm/helper.c | 126
The instruction event is only enabled when icount is used, cycles are
always supported. Always defining get_cycle_count (but altering its
behavior depending on CONFIG_USER_ONLY) allows us to remove some
CONFIG_USER_ONLY #defines throughout the rest of the code.
Signed-off-by: Aaron Lindsay
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/helper.c | 10 +-
1 file changed, 5 insertions(+), 5
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index af09f757df..881d49c662 100644
--- a/target/arm
are supported at runtime, generate it dynamically.
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/cpu.c| 19 +--
target/arm/cpu.h| 10
target/arm/cpu64.c | 4
target/arm/helper.c | 57 +
4 files
Add arrays to hold the registers, the definitions themselves, access
functions, and logic to reset counters when PMCR.P is set. Update
filtering code to support counters other than PMCCNTR. Support migration
with raw read/write functions.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/cpu.h| 4 ++--
target/arm/helper.c | 19 +--
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2a64c1d858..ed3ec81d16 100644
--- a/target/arm/cpu.h
Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only
return 'true' if the specified counter is enabled and neither prohibited
or filtered.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c
This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/cpu.h | 9 +
1
Add an array for PMOVSSET so we only define it for v7ve+ platforms
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 28
1 file changed, 28 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0aff261528
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ddb47813d2..0aff261528 100644
register value and the last underlying cycle count - this
ensures time isn't lost and will also allow us to access the 'old'
architectural register value in order to detect overflows in later
patches.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target
In some cases it may be helpful to modify state before saving it for
migration, and then modify the state back after it has been saved. The
existing pre_save function provides half of this functionality. This
patch adds a post_save function to provide the second half.
Signed-off-by: Aaron Lindsay
the state is saved/restored. By doing this and adding
raw read/write functions for the affected registers, we avoid
migration-related inconsistencies.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/helper.c | 6 --
target/arm/machine.c | 24
timer's migration is
handled
* Added a check against implementing PMCEID[23] if ID_DFR0.PerfMon ==
0xf
* Added TRACEFILT to the ID_DFR0 field definitions
[1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg00805.html
Aaron Lindsay (14):
migration: Add post_save function
On Dec 06 16:03, Peter Maydell wrote:
> On Wed, 5 Dec 2018 at 13:44, Aaron Lindsay
> wrote:
> >
> > Setup a QEMUTimer to get a callback when we expect counters to next
> > overflow and trigger an interrupt at that time.
> >
> > Signed-off-by: Aaron Linds
On Dec 05 08:43, Aaron Lindsay wrote:
> Signed-off-by: Aaron Lindsay
> ---
> target/arm/cpu.h| 4 ++--
> target/arm/helper.c | 18 --
> 2 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> inde
Setup a QEMUTimer to get a callback when we expect counters to next
overflow and trigger an interrupt at that time.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12 +
target/arm/cpu.h| 7 +++
target/arm/helper.c | 126
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 724c2f1d69..3906b6c7a4 100644
--- a/target/arm
The instruction event is only enabled when icount is used, cycles are
always supported. Always defining get_cycle_count (but altering its
behavior depending on CONFIG_USER_ONLY) allows us to remove some
CONFIG_USER_ONLY #defines throughout the rest of the code.
Signed-off-by: Aaron Lindsay
are supported at runtime, generate it dynamically.
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/cpu.c| 19 +--
target/arm/cpu.h| 10
target/arm/cpu64.c | 4
target/arm/helper.c | 57 +
4 files
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.h| 4 ++--
target/arm/helper.c | 18 --
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 304e6e47b3..4216fe22db 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/helper.c | 10 +-
1 file changed, 5 insertions(+), 5
Add an array for PMOVSSET so we only define it for v7ve+ platforms
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 28
1 file changed, 28 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0aff261528
This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.h | 8
1 file changed, 8 insertions
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ddb47813d2..0aff261528 100644
Add arrays to hold the registers, the definitions themselves, access
functions, and logic to reset counters when PMCR.P is set. Update
filtering code to support counters other than PMCCNTR. Support migration
with raw read/write functions.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
the state is saved/restored. By doing this and adding
raw read/write functions for the affected registers, we avoid
migration-related inconsistencies.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target/arm/helper.c | 6 --
target/arm/machine.c | 24
Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only
return 'true' if the specified counter is enabled and neither prohibited
or filtered.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c
Aaron Lindsay (14):
migration: Add post_save function to VMStateDescription
target/arm: Reorganize PMCCNTR accesses
target/arm: Swap PMU values before/after migrations
target/arm: Filter cycle counter based on PMCCFILTR_EL0
target/arm: Allow AArch32 access for PMCCFILTR
target/arm
register value and the last underlying cycle count - this
ensures time isn't lost and will also allow us to access the 'old'
architectural register value in order to detect overflows in later
patches.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
---
target
In some cases it may be helpful to modify state before saving it for
migration, and then modify the state back after it has been saved. The
existing pre_save function provides half of this functionality. This
patch adds a post_save function to provide the second half.
Signed-off-by: Aaron Lindsay
On Dec 03 16:57, Richard Henderson wrote:
> On 12/3/18 4:19 PM, Peter Maydell wrote:
> > On Mon, 3 Dec 2018 at 20:45, Aaron Lindsay
> > wrote:
> >>
> >> On Nov 30 16:10, Peter Maydell wrote:
> >>> PMCEID2 and PMCEID3 are only defined from ARMv
On Nov 30 16:10, Peter Maydell wrote:
> On Tue, 20 Nov 2018 at 21:26, Aaron Lindsay
> wrote:
> >
> > Signed-off-by: Aaron Lindsay
> > ---
> > target/arm/cpu.h| 4 ++--
> > target/arm/helper.c | 12 ++--
> > 2 files changed, 12 insert
On Nov 30 16:14, Peter Maydell wrote:
> On Tue, 20 Nov 2018 at 21:26, Aaron Lindsay
> wrote:
> > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > index 50de58e4a2..32c3397948 100644
> > --- a/target/arm/cpu.h
> > +++ b/target/arm/cpu.h
> > @@ -993,6 +993,
On Nov 30 10:19, Richard Henderson wrote:
> On 11/30/18 9:56 AM, Aaron Lindsay wrote:
> > On Nov 30 09:13, Richard Henderson wrote:
> >> On 11/20/18 1:26 PM, Aaron Lindsay wrote:
> >>> Setup a QEMUTimer to get a callback when we expect counters to next
> >
On Nov 30 09:13, Richard Henderson wrote:
> On 11/20/18 1:26 PM, Aaron Lindsay wrote:
> > Setup a QEMUTimer to get a callback when we expect counters to next
> > overflow and trigger an interrupt at that time.
> >
> > Signed-off-by: Aaron Lindsay
>
Add arrays to hold the registers, the definitions themselves, access
functions, and logic to reset counters when PMCR.P is set. Update
filtering code to support counters other than PMCCNTR. Support migration
with raw read/write functions.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
The instruction event is only enabled when icount is used, cycles are
always supported. Always defining get_cycle_count (but altering its
behavior depending on CONFIG_USER_ONLY) allows us to remove some
CONFIG_USER_ONLY #defines throughout the rest of the code.
Signed-off-by: Aaron Lindsay
Setup a QEMUTimer to get a callback when we expect counters to next
overflow and trigger an interrupt at that time.
Signed-off-by: Aaron Lindsay
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12 +
target/arm/cpu.h| 7 +++
target/arm/helper.c | 126
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