[Qemu-devel] [PATCH v4 15/21] target/arm: Add array for supported PMU events, generate PMCEID[01]

are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c| 20 +--- target/arm/cpu.h| 10 ++ target/arm/cpu64.c | 2 -- target/arm/helper.c | 37 + 4

[Qemu-devel] [PATCH v4 06/21] target/arm: Support multiple EL change hooks

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c | 21 - target/arm/cpu.h | 20 ++-- target/arm/internals.h | 7 --- 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.c b/target/arm

[Qemu-devel] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes

It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/he

[Qemu-devel] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses

register value and the last underlying cycle count - this ensure time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.h

[Qemu-devel] [PATCH v4 17/21] target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay <al

[Qemu-devel] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N

This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- target/arm/helper.c | 31 ++- 1 file changed, 22 insertions(+), 9 deletions(-)

[Qemu-devel] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b14fdab..485004e 100644 ---

[Qemu-devel] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide

This is a bug fix to ensure 64-bit reads of these registers don't read adjacent data. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.h| 4 ++-- target/arm/helper.c | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/

[Qemu-devel] [PATCH v4 02/21] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0

They share the same underlying state Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c i

[Qemu-devel] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState

This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter M

[Qemu-devel] [PATCH v4 00/21] More fully implement ARM PMUv3

logically group changes * Clarify and otherwise improve a few comments * There are also a number of less significant changes scattered around Thanks, Aaron Aaron Lindsay (21): target/arm: Check PMCNTEN for whether PMCCNTR is enabled target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 target/arm

Re: [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0

On Apr 17 16:37, Peter Maydell wrote: > On 17 April 2018 at 16:21, Aaron Lindsay <alind...@codeaurora.org> wrote: > > On Apr 12 13:36, Aaron Lindsay wrote: > >> On Apr 12 18:15, Peter Maydell wrote: > >> > On 16 March 2018 at 20:31, Aaron Lindsay <alind.

Re: [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0

On Apr 12 13:36, Aaron Lindsay wrote: > On Apr 12 18:15, Peter Maydell wrote: > > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > > index b0ef727..9c3b5ef 100644 > > > ---

Re: [Qemu-devel] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions

On Apr 12 18:17, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- > > target/arm/cpu.c | 3 +++ > > target/arm/cpu.h | 1 + > > 2 file

Re: [Qemu-devel] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes

On Apr 12 17:41, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > It was shifted to the left one bit too few. > > > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- > > target/arm/hel

Re: [Qemu-devel] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync

On Apr 12 17:18, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > pmccntr_read and pmccntr_write contained duplicate code that was already > > being handled by pmccntr_sync. Split pmccntr_sync into pmccntr_op_start >

Re: [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3

On Apr 12 18:32, Peter Maydell wrote: > On 16 March 2018 at 20:30, Aaron Lindsay <alind...@codeaurora.org> wrote: > > The ARM PMU implementation currently contains a basic cycle counter, but it > > is > > often useful to gather counts of other events and filter them

Re: [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0

On Apr 12 18:15, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > The pmu_counter_filtered and pmu_op_start/finish functions are generic > > (as opposed to PMCCNTR-specific) to allow for the implementation of > > other

[Qemu-devel] [PATCH v3] RFC: target/arm: Send interrupts on PMU counter overflow

On Mar 16 16:30, Aaron Lindsay wrote: > I aim to eventually add raising interrupts on counter overflow, but that is > not > covered by this patchset. I think I have a reasonable grasp of the mechanics > of > *how* to raise them, but am curious if anyone has thoughts on how to de

Re: [Qemu-devel] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO

On Apr 12 17:53, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > During code generation, surround CPSR writes and exception returns which > > call the EL change hooks with gen_io_start/end. The immediate need is >

Re: [Qemu-devel] [PATCH v3 09/22] target/arm: Add pre-EL change hooks

On Apr 12 17:49, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > Because the design of the PMU requires that the counter values be > > converted between their delta and guest-visible forms for mode > > filtering, an a

Re: [Qemu-devel] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0

On Apr 12 17:10, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > They share the same underlying state > > > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- > > target/arm/helper.c

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01]

On Mar 20 02:03, Philippe Mathieu-Daudé wrote: > On 03/19/2018 09:35 PM, Aaron Lindsay wrote: > > On Mar 18 23:35, Philippe Mathieu-Daudé wrote: > >> Hi Aaron, > >> > >> On 03/16/2018 09:30 PM, Aaron Lindsay wrote: > >>> A53 advertises AR

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 08/22] target/arm: Support multiple EL change hooks

On Mar 18 23:41, Philippe Mathieu-Daudé wrote: > On 03/16/2018 09:31 PM, Aaron Lindsay wrote: > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- > > target/arm/cpu.c | 15 ++- > > target/arm/cpu.h | 23 --

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01]

On Mar 18 23:35, Philippe Mathieu-Daudé wrote: > Hi Aaron, > > On 03/16/2018 09:30 PM, Aaron Lindsay wrote: > > A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]. > > pmceid[01] are already being initialized to zero for both A15 and A57. > > >

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events

On Mar 18 23:48, Philippe Mathieu-Daudé wrote: > On 03/16/2018 09:31 PM, Aaron Lindsay wrote: > > The instruction event is only enabled when icount is used, cycles are > > always supported. Always defining get_cycle_count (but altering its > > behavior depending on CONFIG

Re: [Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide

Phil, On Mar 19 00:14, Philippe Mathieu-Daudé wrote: > Hi Aaron, > > On 03/16/2018 09:31 PM, Aaron Lindsay wrote: > > This is a bug fix to ensure 64-bit reads of this register don't read > > adjacent data. > > > > Signed-off-by: Aaron Lindsay <alind...@cod

Re: [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3

My apologies for the below style issues - I've already fixed them up for v4... -Aaron On Mar 16 13:58, no-re...@patchew.org wrote: > Hi, > > This series seems to have some coding style problems. See output below for > more information: > > Type: series > Message-id:

[Qemu-devel] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay <al

[Qemu-devel] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0d032c..e544f1d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -765,6 +765,7 @@

[Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0

The pmu_counter_filtered and pmu_op_start/finish functions are generic (as opposed to PMCCNTR-specific) to allow for the implementation of other events. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c| 3 ++ target/arm/cpu.h

[Qemu-devel] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes

It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 50eaed7..0102357 100644 --- a/target/arm/helper.c

[Qemu-devel] [PATCH v3 19/22] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Add arrays to hold the registers, the definitions themselves, access functions, and add logic to reset counters when PMCR.P is set. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.h| 7 +- target/arm/helper.c

[Qemu-devel] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO

During code generation, surround CPSR writes and exception returns which call the EL change hooks with gen_io_start/end. The immediate need is for the PMU to access the clock and icount during EL change to support mode filtering. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> ---

[Qemu-devel] [PATCH v3 21/22] target/arm: PMU: Set PMCR.N to 4

This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 del

[Qemu-devel] [PATCH v3 22/22] target/arm: Implement PMSWINC

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 44 ++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 06e2e2c..4f8d11c 100644 --- a/target/arm/helper.c

[Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET

Adding an array for v7VE+ CP registers was necessary so that PMOVSSET wasn't defined for all v7 processors. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/

[Qemu-devel] [PATCH v3 09/22] target/arm: Add pre-EL change hooks

Because the design of the PMU requires that the counter values be converted between their delta and guest-visible forms for mode filtering, an additional hook which occurs before the EL is changed is necessary. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm

[Qemu-devel] [PATCH v3 18/22] target/arm: Add array for supported PMU events, generate PMCEID[01]

This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay <alind...@codeaurora.

[Qemu-devel] [PATCH v3 17/22] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- target/arm/helper.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f5e800e..2073d56 100644

[Qemu-devel] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N

This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 24 +++- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6

[Qemu-devel] [PATCH v3 08/22] target/arm: Support multiple EL change hooks

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c | 15 ++- target/arm/cpu.h | 23 --- target/arm/internals.h | 7 --- 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.c b/target/arm

[Qemu-devel] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState

This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- hw/intc/arm_gicv3_c

[Qemu-devel] [PATCH v3 13/22] target/arm: Allow AArch32 access for PMCCFILTR

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 95b09d6..d4f06e6 100644 --- a/target/arm/helper.c +++ b/targ

[Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide

This is a bug fix to ensure 64-bit reads of this register don't read adjacent data. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c3b5ef..fb2f983

[Qemu-devel] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync

pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Split pmccntr_sync into pmccntr_op_start and pmccntr_op_finish, passing the clock value between the two, to avoid losing time between the two calls. Signed-off-by: Aaron Lindsay <al

[Qemu-devel] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0

They share the same underlying state Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e48982..5634561 100644 --- a/target/arm/helper.c +++ b/

[Qemu-devel] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 022d8c5..072cbbf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1524,7 +1524,7 @@ stati

[Qemu-devel] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01]

A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]. pmceid[01] are already being initialized to zero for both A15 and A57. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu

[Qemu-devel] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 09893e3..5e48982 100644 ---

[Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3

+ (added patch 15, update to 16) Thanks for any feedback, Aaron Aaron Lindsay (22): target/arm: A53: Initialize PMCEID[01] target/arm: A15 PMCEID0 initialization style nit target/arm: Check PMCNTEN for whether PMCCNTR is enabled target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 target

[Qemu-devel] [PATCH] build: Don't force preserving permissions on config-devices.mak.old

Ideally you would only build on a filesystem with proper support, but I haven't been able to find a reason why preserving exact permissions is important in this case. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[Qemu-devel] [PATCH] build: Fix dtc-checkout race condition in Makefile

module path 'dtc' failed This patch fixes this race condition by forcing the 'dtc/%' rule which caused 'dtc' to be non-empty to wait on '.git-submodule-status'. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --gi

Re: [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3

On Oct 17 16:09, Peter Maydell wrote: > On 30 September 2017 at 03:08, Aaron Lindsay <alind...@codeaurora.org> wrote: > > The ARM PMU implementation currently contains a basic cycle counter, but it > > is > > often useful to gather counts of other events and filter

Re: [Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0

On Oct 17 15:57, Peter Maydell wrote: > On 30 September 2017 at 03:08, Aaron Lindsay <alind...@codeaurora.org> wrote: > > The pmu_counter_filtered and pmu_sync functions are generic (as opposed > > to PMCCNTR-specific) to allow for the implementation of other events. > >

Re: [Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET

On Oct 17 15:19, Peter Maydell wrote: > On 30 September 2017 at 03:08, Aaron Lindsay <alind...@codeaurora.org> wrote: > > Also modify it to be stored as a uint64_t > > > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- > > target/arm/c

Re: [Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N

On Oct 17 14:41, Peter Maydell wrote: > On 30 September 2017 at 03:08, Aaron Lindsay <alind...@codeaurora.org> wrote: > > This is in preparation for enabling counters other than PMCCNTR > > > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> >

Re: [Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync

On Oct 17 14:25, Peter Maydell wrote: > On 30 September 2017 at 03:08, Aaron Lindsay <alind...@codeaurora.org> wrote: > > pmccntr_read and pmccntr_write contained duplicate code that was already > > being handled by pmccntr_sync. This also moves the calls to get

Re: [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled

On Oct 17 13:49, Peter Maydell wrote: > On 30 September 2017 at 03:08, Aaron Lindsay <alind...@codeaurora.org> wrote: > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- > > target/arm/helper.c | 2 +- > > 1 file changed, 1 insertion(+), 1

Re: [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0]

On Oct 09 19:19, Peter Maydell wrote: > On 19 April 2017 at 18:41, Aaron Lindsay <alind...@codeaurora.org> wrote: > > A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01] > > > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > --- >

Re: [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3

On Oct 09 19:27, Peter Maydell wrote: > On 9 October 2017 at 15:46, Aaron Lindsay <alind...@codeaurora.org> wrote: > > Unfortunately I'm not sure who to add other than the current recipients, > > but I'm eager for feedback and would love to work this into something > >

Re: [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3

29 22:08, Aaron Lindsay wrote: > The ARM PMU implementation currently contains a basic cycle counter, but it is > often useful to gather counts of other events and filter them based on > execution mode. These patches flesh out the implementations of various PMU > registers including

[Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4

This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

[Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are always supported. Note: Setting can_do_io=1 should not be done here. It is ugly and wrong, but I am not sure of the proper way to handle this (See 'target/arm: Filter cycle counter based on PMCCFILTR_EL0') Signed-off-by: Aaron

[Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Add arrays to hold the registers, the definitions themselves, access functions, and add logic to reset counters when PMCR.P is set. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.h| 7 +- target/arm/helper.c

[Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01]

This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay <alind...@codeaurora.

[Qemu-devel] [PATCH 13/13] target/arm: Implement PMSWINC

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 40 ++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a15b932..2c51f92 100644 --- a/target/arm/helper.c

[Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0

mechanism for handling this? Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c | 4 +++ target/arm/cpu.h | 15 +++ target/arm/helper.c| 73 +++--- target/arm/kvm64.c | 2 ++ target/arm/machine.c

[Qemu-devel] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9c01269..5d07f72 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -

[Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR

Also fix the existing bitmask for writes. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e8189b8..530fc7c

[Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET

Also modify it to be stored as a uint64_t Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.h| 2 +- target/arm/helper.c | 27 --- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h

[Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N

This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 24 +++- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3

[Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync

pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. This also moves the calls to get the clock inside the 'if' statement so they are not executed if not needed. Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.

[Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3

n't seem like the right way to handle this. I would like to eventually add sending interrupts on counter overflow. Suggestions for the best direction to handle this are most welcome. Thanks for any feedback, Aaron Aaron Lindsay (13): target/arm: A53: Initialize PMCEID[0] target/arm: Ch

[Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled

Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8cb7a94..391 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -964,7 +964,7 @@

[Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0]

A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01] Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0

Re: [Qemu-devel] [PULL 08/24] tcg: drop global lock during TCG code execution

On Feb 27 14:39, Alex Bennée wrote: > > Laurent Desnogues writes: > > > Hello, > > > > On Fri, Feb 24, 2017 at 12:20 PM, Alex Bennée > > wrote: > >> From: Jan Kiszka > >> > >> This finally allows TCG to benefit from

Re: [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1

Wei, Peter, On Feb 10 18:07, Peter Maydell wrote: > From: Wei Huang > > This patch adds access support for PMINTENSET_EL1. > > Signed-off-by: Wei Huang > Reviewed-by: Peter Maydell > Message-id:

[Qemu-devel] [PATCH] avx2 configure: Disable if static build

{ (gdb) bt #0 buffer_find_nonzero_offset_ifunc () at ./util/cutils.c:333 #1 0x00939c58 in __libc_start_main () #2 0x00419337 in _start () Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> --- configure | 17 ++--- 1 file chang

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 16:05, Dr. David Alan Gilbert wrote: > * Aaron Lindsay (alind...@codeaurora.org) wrote: > > On Jul 14 14:33, Dr. David Alan Gilbert wrote: > > > * Aaron Lindsay (alind...@codeaurora.org) wrote: > > > > I'm configuring with: > > >

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 15:35, Peter Maydell wrote: > On 14 July 2016 at 15:27, Aaron Lindsay <alind...@codeaurora.org> wrote: > > On Jul 14 14:23, Peter Maydell wrote: > >> On 14 July 2016 at 14:15, Paolo Bonzini <pbonz...@redhat.com> wrote: > >> > On 14/07/20

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 14:23, Peter Maydell wrote: > On 14 July 2016 at 14:15, Paolo Bonzini <pbonz...@redhat.com> wrote: > > On 14/07/2016 15:13, Aaron Lindsay wrote: > >> I'm configuring with: > >> # ./configure \ > >> --static \ > >> --dis

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 14:33, Dr. David Alan Gilbert wrote: > * Aaron Lindsay (alind...@codeaurora.org) wrote: > > I'm configuring with: > > # ./configure \ > > --static \ > > --disable-gtk \ > > --target-list=aarch64-softmmu > > Does it work if you configu

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jun 10 12:16, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > Use the avx2 primitives during the test, thus making sure that the > compiler and assembler could actually use avx2. > > This also detects the failure case on gcc 4.8.x with

Re: [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers

On Feb 09 15:11, Alistair Francis wrote: > On Tue, Feb 9, 2016 at 9:19 AM, Peter Maydell <peter.mayd...@linaro.org> > wrote: > > On 6 February 2016 at 00:55, Alistair Francis > > <alistair.fran...@xilinx.com> wrote: > >> Signed-off-by: Aaron Lindsay &l

Re: [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers

On Feb 04 10:52, Alistair Francis wrote: > On Thu, Feb 4, 2016 at 5:39 AM, Aaron Lindsay <alind...@codeaurora.org> wrote: > > Please add my > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > > to all three. > > Ok, I wasn't sure what yo

Re: [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers

Alistair, On Feb 03 16:34, Alistair Francis wrote: > This patch set is based on the patch sent by Christopher Covington and > written by Aaron Lindsay which was sent as an RFC (Implement remaining > PMU functionality). These patches look like a good start to improving the PMU suppor

<    1   2   3   4