[PATCH v3 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ

cannot exactly capture the period of frequencies that do not cleanly divide NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an equally inaccurate scaling factor for scaling time to ticks so at least a self-consistent inverse relationship holds. Signed-off-by: Andrew Jeffery Reviewed

[PATCH v3 1/4] target/arm: Remove redundant scaling of nexttick

The corner-case codepath was adjusting nexttick such that overflow wouldn't occur when timer_mod() scaled the value back up. Remove a use of GTIMER_SCALE and avoid unnecessary operations by calling timer_mod_ns() directly. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed

[PATCH v3 0/4] Expose GT CNTFRQ as a CPU property to support AST2600

ilure from partial renaming of gt_cntfrq_period_ns() * Add tags from Cedric and Richard Please review. Andrew Andrew Jeffery (4): target/arm: Remove redundant scaling of nexttick target/arm: Abstract the generic timer frequency target/arm: Prepare generic timer for per-platform CNTFRQ

[PATCH v3 2/4] target/arm: Abstract the generic timer frequency

-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- v3: * Uninline gt_cntfrq_period_ns() * Rename gt_cntfrq to gt_cntfrq_hz target/arm/cpu.c| 8 target/arm/cpu.h| 5 + target/arm/helper.c | 10 +++--- 3 files changed, 20 insertions

[PATCH v2 0/2] hw/arm: ast2600: Wire up eMMC controller

pointed out by Cedric. v1 can be found here: https://patchwork.ozlabs.org/cover/1206845/ Please review! Andrew Andrew Jeffery (2): hw/sd: Configure number of slots exposed by the ASPEED SDHCI model hw/arm: ast2600: Wire up the eMMC controller hw/arm/aspeed.c | 27

[PATCH v2 2/2] hw/arm: ast2600: Wire up the eMMC controller

Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery --- v2: * Extract instantiation of SD cards to helper

[PATCH v2 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model

that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2

Re: [PATCH 0/2] hw/arm: ast2600: Wire up eMMC controller

On Tue, 10 Dec 2019, at 19:23, Cédric Le Goater wrote: > On 10/12/2019 01:52, Andrew Jeffery wrote: > > Hello, > > > > The AST2600 has an additional SDHCI intended for use as an eMMC boot source. > > Have you also considered booting the QEMU Aspeed AST2600 mach

Re: [PATCH 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model

On Tue, 10 Dec 2019, at 19:26, Cédric Le Goater wrote: > On 10/12/2019 01:52, Andrew Jeffery wrote: > > The AST2600 includes a second cut-down version of the SD/MMC controller > > found in the AST2500, named the eMMC controller. It's cut down in the > > sense that it o

Re: [PATCH 2/2] hw/arm: ast2600: Wire up the eMMC controller

On Tue, 10 Dec 2019, at 23:22, Cédric Le Goater wrote: > On 10/12/2019 01:52, Andrew Jeffery wrote: > > Initialise another SDHCI model instance for the AST2600's eMMC > > controller and use the SDHCI's num_slots value introduced previously to > > determine whether we sho

[PATCH 2/2] hw/arm: ast2600: Wire up the eMMC controller

Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed.c | 13 + hw

[PATCH 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model

that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 3

[PATCH 0/2] hw/arm: ast2600: Wire up eMMC controller

Hello, The AST2600 has an additional SDHCI intended for use as an eMMC boot source. These two patches rework the existing ASPEED SDHCI model to accommodate the single-slot nature of the eMMC controller and wire it into the AST2600 SoC. Please review! Andrew Andrew Jeffery (2): hw/sd

Re: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency

On Wed, 4 Dec 2019, at 03:57, Philippe Mathieu-Daudé wrote: > On 12/3/19 1:48 PM, Andrew Jeffery wrote: > > On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daudé wrote: > >> On 12/3/19 5:14 AM, Andrew Jeffery wrote: > >>> Prepare for SoCs such as the ASPEED AST

Re: [PATCH v2 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ

On Tue, 3 Dec 2019, at 16:49, Philippe Mathieu-Daudé wrote: > On 12/3/19 5:14 AM, Andrew Jeffery wrote: > > The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On > > recent firmwares this is at 1125MHz, which is considerably quicker than > > the assumed 6

Re: [PATCH v2 2/4] target/arm: Abstract the generic timer frequency

On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daudé wrote: > On 12/3/19 5:14 AM, Andrew Jeffery wrote: > > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures > > CNTFRQ to values significantly larger than the static 62.5MHz value > > currently deri

[PATCH v2 2/4] target/arm: Abstract the generic timer frequency

-by: Andrew Jeffery Reviewed-by: Richard Henderson --- target/arm/cpu.c| 2 ++ target/arm/cpu.h| 10 ++ target/arm/helper.c | 10 +++--- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..5698a74061bb 100644

[PATCH v2 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ

cannot exactly capture the period of frequencies that do not cleanly divide NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an equally inaccurate scaling factor for scaling time to ticks so at least a self-consistent inverse relationship holds. Signed-off-by: Andrew Jeffery Reviewed

[PATCH v2 4/4] ast2600: Configure CNTFRQ at 1125MHz

This matches the configuration set by u-boot on the AST2600. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index

[PATCH v2 0/4] Expose GT CNTFRQ as a CPU property to support AST2600

rd Please review. Andrew Andrew Jeffery (4): target/arm: Remove redundant scaling of nexttick target/arm: Abstract the generic timer frequency target/arm: Prepare generic timer for per-platform CNTFRQ ast2600: Configure CNTFRQ at 1125MHz hw/arm/aspeed_ast2600.c | 3 +++ target

[PATCH v2 1/4] target/arm: Remove redundant scaling of nexttick

The corner-case codepath was adjusting nexttick such that overflow wouldn't occur when timer_mod() scaled the value back up. Remove a use of GTIMER_SCALE and avoid unnecessary operations by calling timer_mod_ns() directly. Signed-off-by: Andrew Jeffery Reviewed-by: Richard Henderson Reviewed

Re: [PATCH 2/4] target/arm: Abstract the generic timer frequency

On Tue, 3 Dec 2019, at 04:42, Peter Maydell wrote: > On Thu, 28 Nov 2019 at 05:44, Andrew Jeffery wrote: > > > > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures > > CNTFRQ to values significantly larger than the static 62.5MHz value > > currentl

Re: [PATCH 2/4] target/arm: Abstract the generic timer frequency

On Thu, 28 Nov 2019, at 19:16, Cédric Le Goater wrote: > On 28/11/2019 06:45, Andrew Jeffery wrote: > > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures > > CNTFRQ to values significantly larger than the static 62.5MHz value > > currently deri

[PATCH 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ

cannot exactly capture the period of frequencies that do not cleanly divide NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an equally inaccurate scaling factor for scaling time to ticks so at least an self-consistent inverse relationship holds. Signed-off-by: Andrew Jeffery

[PATCH 0/4] Expose GT CNTFRQ as a CPU property to support AST2600

-coded generic timer rate of 62.5MHz and so we see "sticky" behaviour in the guest. Please review. Andrew Andrew Jeffery (4): target/arm: Remove redundant scaling of nexttick target/arm: Abstract the generic timer frequency target/arm: Prepare generic timer for per-platform CNTFRQ

[PATCH 2/4] target/arm: Abstract the generic timer frequency

-by: Andrew Jeffery --- target/arm/cpu.c| 2 ++ target/arm/cpu.h| 10 ++ target/arm/helper.c | 10 +++--- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..5698a74061bb 100644 --- a/target/arm/cpu.c +++ b/target/arm

[PATCH 4/4] ast2600: Configure CNTFRQ at 1125MHz

This matches the configuration set by u-boot on the AST2600. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed_ast2600.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681f..5aecc3b3caec 100644 --- a/hw/arm/aspeed_ast2600.c

[PATCH 1/4] target/arm: Remove redundant scaling of nexttick

The corner-case codepath was adjusting nexttick such that overflow wouldn't occur when timer_mod() scaled the value back up. Remove a use of GTIMER_SCALE and avoid unnecessary operations by calling timer_mod_ns() directly. Signed-off-by: Andrew Jeffery --- target/arm/helper.c | 5 +++-- 1 file

Re: [Qemu-devel] [PATCH v5] target-arm: Make the counter tick relative to cntfrq

On Wed, 18 Sep 2019, at 04:55, Richard Henderson wrote: > On 9/17/19 12:14 PM, Peter Maydell wrote: > >> +static Property arm_cpu_gt_cntfrq_property = > >> +DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq, > >> + (1000 * 1000 * 1000) / GTIMER_SCALE); > >

Re: [PATCH v5] target-arm: Make the counter tick relative to cntfrq

On Wed, 18 Sep 2019, at 01:44, Peter Maydell wrote: > On Thu, 12 Sep 2019 at 07:56, Andrew Jeffery wrote: > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index 507026c9154b..09975704d47f 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helpe

Re: [PATCH 03/21] hw: aspeed_scu: Add AST2600 support

On Thu, 19 Sep 2019, at 15:19, Cédric Le Goater wrote: > From: Joel Stanley > > The SCU controller on the AST2600 SoC has extra registers. Increase > the number of regs of the model and introduce a new field in the class > to customize the MemoryRegion operations depending on the SoC model. >

Re: [Qemu-devel] [PATCH 00/21] aspeed: Add support for the AST2600 SoC

On Fri, 20 Sep 2019, at 06:26, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20190919055002.6729-1-...@kaod.org/ > > > > Hi, > > This series failed the docker-quick@centos7 build test. Please find the > testing commands and > their output below. If you have Docker

[Qemu-devel] [PATCH v5] target-arm: Make the counter tick relative to cntfrq

-off-by: Andrew Jeffery --- v5: Remove unrelated submodule updates that snuck into v4 v4: https://patchwork.ozlabs.org/patch/1161340/ Fix configuration for cores without a generic timer v3: https://patchwork.ozlabs.org/patch/1160634/ Peter - I think this addresses most of your feedback. I still

Re: [Qemu-devel] [PATCH v4] target-arm: Make the counter tick relative to cntfrq

On Thu, 12 Sep 2019, at 15:52, Cédric Le Goater wrote: > On 12/09/2019 05:25, Andrew Jeffery wrote: > > Allow machines to configure CNTFRQ via a property if the ARM core > > supports the generic timer. This is necessary on e.g. the ASPEED AST2600 > > SoC where the gener

[Qemu-devel] [PATCH v4] target-arm: Make the counter tick relative to cntfrq

-off-by: Andrew Jeffery --- v4: Fix configuration for cores without a generic timer v3: https://patchwork.ozlabs.org/patch/1160634/ Peter - I think this addresses most of your feedback. I still reach into the QEMUTimer to fetch out scale when adjusting the nexttick calculation, but we no longer need

Re: [Qemu-devel] [PATCH v3] target-arm: Make the counter tick relative to cntfrq

On Wed, 11 Sep 2019, at 15:40, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20190911034302.29108-1-and...@aj.id.au/ > > > > Hi, > > This series failed the docker-quick@centos7 build test. Please find the > testing commands and > their output below. If you have Docker

[Qemu-devel] [PATCH v3] target-arm: Make the counter tick relative to cntfrq

which is used during realize() to configure the QEMUTimers that back the generic timers. Beyond that the firmware can to do whatever it sees fit with the CNTFRQ register though changes to the value will not be reflected in the timers' rate. Signed-off-by: Andrew Jeffery --- Peter - I think

Re: [Qemu-devel] [PATCH v2] target-arm: Make the counter tick relative to cntfrq

On Thu, 29 Aug 2019, at 11:08, Andrew Jeffery wrote: > > > On Wed, 28 Aug 2019, at 01:39, Peter Maydell wrote: > > On Fri, 9 Aug 2019 at 06:43, Andrew Jeffery wrote: > > > > > > The use of GTIMER_SCALE assumes the clock feeding the generic timer i

Re: [Qemu-devel] [PATCH v2] target-arm: Make the counter tick relative to cntfrq

On Wed, 28 Aug 2019, at 01:39, Peter Maydell wrote: > On Fri, 9 Aug 2019 at 06:43, Andrew Jeffery wrote: > > > > The use of GTIMER_SCALE assumes the clock feeding the generic timer is > > 62.5MHz for all platforms. This is untrue in general, for example the > > ASPEE

Re: [Qemu-devel] [PATCH v9 01/11] hw/arm: simplify arm_load_dtb

gor Mammedov > > Signed-off-by: Tao Xu > > Reviewed-by: Alistair Francis > > Alistair > > > --- > > > > No changes in v9 > > --- > > hw/arm/aspeed.c | 5 + For the ASPEED machines: Acked-by: Andrew Jeffery

[Qemu-devel] [PATCH v2] target-arm: Make the counter tick relative to cntfrq

as the guest timer subsystems account for the difference between delay time and the counter value. Signed-off-by: Andrew Jeffery --- v2: 1. Removed the user-mode change that broke v1 2. Rearranged the implementation as a consequence of 1. target/arm/helper.c | 51

Re: [Qemu-devel] [PATCH] target-arm: Make the counter tick relative to cntfrq

On Fri, 9 Aug 2019, at 13:36, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20190809031321.14760-1-and...@aj.id.au/ > > > > Hi, > > This series failed build test on s390x host. Please find the details below. > > === TEST SCRIPT BEGIN === > #!/bin/bash > # Testing

[Qemu-devel] [PATCH] target-arm: Make the counter tick relative to cntfrq

as the guest timer subsystems account for the difference between delay time and the counter value. Signed-off-by: Andrew Jeffery --- The timer rate assumptions seemed unusual, so I'm not sure if this patch is way off-base or not. However it does make the AST2600 u-boot and kernel behave correctly. target

Re: [Qemu-devel] [PATCH 1/2] hw/gpio: Add basic Aspeed GPIO model

On Mon, 15 Jul 2019, at 12:06, Rashmica Gupta wrote: > Sorry for the late reply! I agree with most of your feedback and will > send out > a v2 shortly with those changes. I have a few replies below > > [snip] > > > > +static const struct AspeedGPIO gpios[0x1f0] = { > > > +/* Set ABCD */ >

Re: [Qemu-devel] [PATCH 1/2] hw/gpio: Add basic Aspeed GPIO model

On Tue, 18 Jun 2019, at 18:52, Rashmica Gupta wrote: > Add in details for GPIO controller for AST 2400 and 2500 > > Signed-off-by: Rashmica Gupta > --- > hw/gpio/Makefile.objs | 1 + > hw/gpio/aspeed_gpio.c | 869 ++ >

Re: [Qemu-devel] [PATCH v2 11/21] aspeed/timer: Ensure positive muldiv delta

ff-by: Christian Svensson > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery > --- > hw/timer/aspeed_timer.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c > index 6501fa0768e7..1f0f1886

Re: [Qemu-devel] [PATCH qemu] aspeed: Add support for the swift-bmc board

On Tue, 4 Jun 2019, at 09:07, Joel Stanley wrote: > On Mon, 3 Jun 2019 at 19:11, Adriana Kobylak wrote: > > > > From: Adriana Kobylak > > > > The Swift board is an OpenPOWER system hosting POWER processors. > > Add support for their BMC including the I2C devices as found on HW. > > > >

Re: [Qemu-devel] [PATCH] arm: aspeed: Set SDRAM size

Stanley Reviewed-by: Andrew Jeffery > --- > hw/arm/aspeed.c | 6 ++ > include/hw/arm/aspeed.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 1c23ebd99252..3f3d4162b3c5 100644 > --- a/hw/arm/aspeed.c

Re: [Qemu-devel] [PATCH 2/3] aspeed: add a per SoC mapping for the memory space

quot; layout concept is more distracting than having soc-specific, complete layouts described. There's no reason why they're common beyond coincidence (i.e. it's at ASPEED's whim). I think this is fine. Reviewed-by: Andrew Jeffery > > This is fine for now. > > Reviewed-by: Joel Stanley >

Re: [Qemu-devel] [PATCH 3/3] aspeed: use sysbus_init_child_obj() to initialize children

On Fri, 12 Apr 2019, at 01:40, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery > --- > hw/arm/aspeed_soc.c | 50 ++--- > 1 file changed, 20 insertions(+), 30 deletions(-) > > diff --git a/hw/

Re: [Qemu-devel] [PATCH 1/3] aspeed: add a per SoC mapping for the interrupt space

On Fri, 12 Apr 2019, at 02:13, Philippe Mathieu-Daudé wrote: > Hi Cédric, > > On 4/11/19 6:10 PM, Cédric Le Goater wrote: > > This will simplify the definition of new SoCs, like the AST2600 which > > should use a different CPU and a different IRQ number layout. > > > > Signed-off-by: Cédric

Re: [Qemu-devel] Maintainers, please tell us how to boot your machines!

//lists.gnu.org/archive/html/qemu-devel/2019-03/msg03881.html > > > > * Maybe identify a few machines we don't know how to boot anymore. > > > > Thanks in advance for your help! > > > > > > > > Machines with at least one maintainer: > > >

Re: [Qemu-devel] [PATCH] ftgmac100: implement the new MDIO interface on Aspeed SoC

eature Register (MAC40) controls which MDC/MDIO > interface is active. > > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery > --- > hw/net/ftgmac100.c | 80 +++--- > 1 file changed, 68 insertions(+), 12 deletions(-) > &g

Re: [Qemu-devel] [PATCH] gitdm: Add other IBMers

On Wed, 2 Jan 2019, at 21:36, Joel Stanley wrote: > Here are some IBMers who use their personal addresses when submitting > patches. > > Signed-off-by: Joel Stanley For the addition of my address: Acked-by: Andrew Jeffery > --- > contrib/gitdm/group-map-ibm | 5 + &g

Re: [Qemu-devel] [RFC PATCH 1/1] memory: Support unaligned accesses on aligned-only models

On Thu, 20 Sep 2018, at 21:43, Cédric Le Goater wrote: > Andrew, > > On 07/14/2017 08:20 AM, Andrew Jeffery wrote: > > Hi Paolo, > > > > Thanks for taking a look! > > > > On Thu, 2017-07-13 at 14:05 +0200, Paolo Bonzini wrote: > >> On 30/06/2017 0

Re: [Qemu-devel] [PATCH] aspeed: Implement write-1-{set, clear} for AST2500 strapping

On Fri, 13 Jul 2018, at 01:28, Peter Maydell wrote: > On 9 July 2018 at 15:35, Andrew Jeffery wrote: > > The AST2500 SoC family changes the runtime behaviour of the hardware > > strapping register (SCU70) to write-1-set/write-1-clear, with > > write-1-clear implemented o

[Qemu-devel] [PATCH] aspeed: Implement write-1-{set, clear} for AST2500 strapping

dify-write semantics. Signed-off-by: Andrew Jeffery --- hw/misc/aspeed_scu.c | 19 +-- include/hw/misc/aspeed_scu.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 5e6d5744eeca..9051767cbbcd 100644 ---

Re: [Qemu-devel] [PATCH] MAINTAINERS: Add ASPEED BMCs

; > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -644,6 +644,17 @@ M: Subbaraya Sundeep > > S: Maintained > > F: hw/arm/msf2-som.c > > > > +ASPEED BMCs > > +M: Cédric Le Goater > > +R: Andrew Jeffery > > +R: Joel Stanley > &g

Re: [Qemu-devel] [PATCH 3/3] aspeed/smc: rename aspeed_smc_flash_send_addr() to aspeed_smc_flash_setup()

On Tue, 12 Jun 2018, at 16:27, Cédric Le Goater wrote: > Also handle the fake transfers for dummy bytes in this setup > routine. It will be useful when we activate MMIO execution. > > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery > --- > hw/ssi

Re: [Qemu-devel] [PATCH 2/3] aspeed/smc: fix HW strapping

On Tue, 12 Jun 2018, at 16:27, Cédric Le Goater wrote: > Only the flash type is strapped by HW. The 4BYTE mode is set by > firmware when the flash device is detected. > > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery > --- > hw/ssi/aspeed_smc.c | 8 +--- &g

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/3] aspeed/smc: fix dummy cycles count when in dual IO mode

On Tue, 12 Jun 2018, at 16:27, Cédric Le Goater wrote: > When configured in dual I/O mode, address and data are sent in dual > mode, including the dummy byte cycles in between. Adapt the count to > the IO setting. > > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery

Re: [Qemu-devel] [PATCH v2 3/3] aspeed/timer: use the APB frequency from the SCU

quency for all SoCs by linking the Timer model to > the SCU model. The APB frequency driving the timers is now the one > configured for the SoC. > > Signed-off-by: Cédric Le Goater > Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery > --- > include/hw/timer/aspeed_timer.

Re: [Qemu-devel] [PATCH v2 2/3] aspeed: initialize the SCU controller first

On Fri, 22 Jun 2018, at 17:26, Cédric Le Goater wrote: > The System Control Unit should be initialized first as it drives all > the configuration of the SoC and other device models. > > Signed-off-by: Cédric Le Goater > Reviewed-by: Joel Stanley Acked-by: Andrew Jeffery

Re: [Qemu-devel] [PATCH v2 1/3] aspeed/scu: introduce clock frequencies

to drive > the Aspeed timer model. > > Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery > --- > include/hw/misc/aspeed_scu.h | 70 ++-- > hw/misc/aspeed_scu.c | 106 > +++ > 2 files c

Re: [Qemu-devel] [PATCH] Fix ast2500 protection register emulation

gisters as ordinary memory writes, writing the inverse of the magic > value resulted in subsequent reads returning that value, leading to > u-boot spinning forever. > > Signed-off-by: Hugo Landau <hlan...@devever.net> Acked-by: Andrew Jeffery <and...@aj.id.au> >

Re: [Qemu-devel] [PATCH v2 2/2] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

001e631000-1e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2 > > Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> > Reviewed-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- > include/hw

Re: [Qemu-devel] [PATCH v2 1/2] hw/arm/aspeed: directly map the serial device to the system address space

85020-1e78503f (prio 0, i/o): aspeed.wdt > > Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- > hw/arm/aspeed_soc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git

Re: [Qemu-devel] [PATCH 1/2] hw/arm/aspeed: directly map the serial device to the system address space

On Thu, 2018-02-08 at 14:40 -0300, Philippe Mathieu-Daudé wrote: > On 02/08/2018 02:30 PM, Peter Maydell wrote: > > On 8 February 2018 at 17:22, Philippe Mathieu-Daudé wrote: > > > Signed-off-by: Philippe Mathieu-Daudé > > > --- > > > hw/arm/aspeed_soc.c | 2 +-

Re: [Qemu-devel] [PATCH v2] hw/arm/aspeed: Unlock SCU when running kernel

On Mon, 2017-11-13 at 23:58 +1030, Joel Stanley wrote: > The ASPEED hardware contains a lock register for the SCU that disables > any writes to the SCU when it is locked. The machine comes up with the > lock enabled, but on all known hardware u-boot will unlock it and leave > it unlocked when

Re: [Qemu-devel] [PATCH v2 1/6] aspeed: add support for the witherspoon-bmc board

On Wed, 2017-10-11 at 09:28 +0200, Cédric Le Goater wrote: > On 10/11/2017 05:49 AM, Andrew Jeffery wrote: > > On Tue, 2017-10-10 at 15:30 +0200, Cédric Le Goater wrote: > > > On 10/09/2017 02:04 AM, Andrew Jeffery wrote: > > > > On Wed, 2017-09-20 at 09:01

Re: [Qemu-devel] [PATCH v2 1/6] aspeed: add support for the witherspoon-bmc board

On Tue, 2017-10-10 at 15:30 +0200, Cédric Le Goater wrote: > On 10/09/2017 02:04 AM, Andrew Jeffery wrote: > > On Wed, 2017-09-20 at 09:01 +0200, Cédric Le Goater wrote: > > > The Witherspoon boards are OpenPOWER system hosting POWER9 Processors. > > > Let's add supp

Re: [Qemu-devel] [PATCH v2 6/6] aspeed: add the pc9552 chips to the witherspoon machine

On Wed, 2017-09-20 at 09:01 +0200, Cédric Le Goater wrote: > The pca9552 LED blinkers on the Witherspoon machine are used for leds > but also as GPIOs to control fans and GPUs. >  > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id

Re: [Qemu-devel] [PATCH v2 4/6] aspeed: Add EEPROM I2C devices

On Wed, 2017-09-20 at 09:01 +0200, Cédric Le Goater wrote: > The Aspeed boards have at least one EEPROM to hold the Vital Product > Data (VPD). >  > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  > Changes

Re: [Qemu-devel] [PATCH v2 2/6] aspeed: add an I2C RTC device to all machines

eatures we need. >  > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed.c | 19 +++ >  1 file changed, 19 insertions(+) >  > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > ind

Re: [Qemu-devel] [PATCH v2 1/6] aspeed: add support for the witherspoon-bmc board

init(machine, _boards[WITHERSPOON_BMC]); > +} > + > +static void witherspoon_bmc_class_init(ObjectClass *oc, void *data) > +{ > +MachineClass *mc = MACHINE_CLASS(oc); > + > +mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; > +mc->init = witherspoon_bm

Re: [Qemu-devel] [PATCH v2] watchdog/aspeed: fix variable type to store reload value

by ULL ] > Signed-off-by: Cédric Le Goater <c...@kaod.org> Acked-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/watchdog/wdt_aspeed.c | 4 ++-- >  1 file changed, 2 insertions(+), 2 deletions(-) >  > diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspee

Re: [Qemu-devel] [PATCH for 2.11 v2 1/2] watchdog: wdt_aspeed: Add support for the reset width register

On Wed, Aug 9, 2017, at 18:28, Cédric Le Goater wrote: > On 08/09/2017 08:28 AM, Andrew Jeffery wrote: > > The reset width register controls how the pulse on the SoC's WDTRST{1,2} > > pins behaves. A pulse is emitted if the external reset bit is set in > > WDT

Re: [Qemu-devel] [PATCH for 2.11 v2 2/2] ARM: aspeed_soc: Propagate silicon-rev to watchdog

Ugh, disregard this one; I changed the subject and reissued `git format-patch`, which naturally doesn't overwrite any existing patch in the output directory and so the old one got sent as well. Andrew On Wed, 2017-08-09 at 15:58 +0930, Andrew Jeffery wrote: > This is required to config

[Qemu-devel] [PATCH for 2.11 v2 2/2] aspeed_soc: Propagate silicon-rev to watchdog

This is required to configure differences in behaviour between the AST2400 and AST2500 watchdog IPs. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 303484

[Qemu-devel] [PATCH for 2.11 v2 1/2] watchdog: wdt_aspeed: Add support for the reset width register

needs some special handling in the write path. As some of the capabilities depend on the SoC version a silicon-rev property is introduced, which is used to guard version-specific behaviour. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/watchdog/wdt_aspeed.c

[Qemu-devel] [PATCH for 2.11 v2 2/2] ARM: aspeed_soc: Propagate silicon-rev to watchdog

This is required to configure differences in behaviour between the AST2400 and AST2500 watchdog IPs. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/arm/aspeed_soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 303484

[Qemu-devel] [PATCH for 2.11 v2 0/2] wdt_aspeed: Support reset width patterns

/796039/ Andrew Jeffery (2): watchdog: wdt_aspeed: Add support for the reset width register aspeed_soc: Propagate silicon-rev to watchdog hw/arm/aspeed_soc.c | 2 + hw/watchdog/wdt_aspeed.c | 93 +++- include/hw/watchdog/wdt_aspeed.h | 2

Re: [Qemu-devel] [PATCH] watchdog: wdt_aspeed: Add support for the reset width register

On Tue, 2017-08-01 at 09:21 +0200, Cédric Le Goater wrote: > On 08/01/2017 03:04 AM, Andrew Jeffery wrote: > > The reset width register controls how the pulse on the SoC's WDTRST{1,2} > > pins behaves. A pulse is emitted if the external reset bit is set in > > WDT_CTRL. WDT

Re: [Qemu-devel] [Qemu-arm] [PATCH] watchdog: wdt_aspeed: Add support for the reset width register

Hi Phil, On Tue, 2017-08-01 at 00:23 -0300, Philippe Mathieu-Daudé wrote: > Hi Andrew, > > On 07/31/2017 10:04 PM, Andrew Jeffery wrote: > > The reset width register controls how the pulse on the SoC's WDTRST{1,2} > > pins behaves. A pulse is emitted if the exte

[Qemu-devel] [PATCH] watchdog: wdt_aspeed: Add support for the reset width register

special handling in the write path. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- I understand that we're in stabilisation mode, but I thought I'd send this out to provoke any feedback. Happy to resend after the 2.10 release if required. hw/watchdog/wdt_aspeed.

Re: [Qemu-devel] [RFC PATCH 1/1] memory: Support unaligned accesses on aligned-only models

Hi Paolo, Thanks for taking a look! On Thu, 2017-07-13 at 14:05 +0200, Paolo Bonzini wrote: > On 30/06/2017 05:00, Andrew Jeffery wrote: > > This RFC patch stems from a discussion on a patch for an ADC model[1] where > > it > > was pointed out that I should be able to

[Qemu-devel] [RFC PATCH 1/1] memory: Support unaligned accesses on aligned-only models

Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Hello, This RFC patch stems from a discussion on a patch for an ADC model[1] where it was pointed out that I should be able to use the .impl member of MemoryRegionOps to constrain how my read() and write() callbacks where invoked. I

Re: [Qemu-devel] [PATCH] timer/aspeed: fix timer enablement when a reload is not set

On Fri, 2017-06-09 at 07:40 +0200, Cédric Le Goater wrote: > On 06/09/2017 04:26 AM, Andrew Jeffery wrote: > > On Tue, 2017-06-06 at 10:55 +0200, Cédric Le Goater wrote: > > > When a timer is enabled before a reload value is set, the controller > > > waits for a re

Re: [Qemu-devel] [PATCH] timer/aspeed: fix timer enablement when a reload is not set

t: > @@ -268,7 +289,7 @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool > enable) >  trace_aspeed_timer_ctrl_enable(t->id, enable); >  if (enable) { >  t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > -timer_mod(>timer, calculate_next(t)); > +aspeed_timer_mod(t); >  } else { >  timer_del(>timer); >  } Reviewed-by: Andrew Jeffery <and...@aj.id.au> signature.asc Description: This is a digitally signed message part

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model

On Wed, 2017-05-24 at 02:15 -0300, Philippe Mathieu-Daudé wrote: > Hi Andrew, > > On 05/22/2017 02:14 AM, Andrew Jeffery wrote: > > On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote: > > > In ASPEED SoC chip, all register access have following rule. > > > Most o

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model

e-mail and any > attachments without copying or disclosing the contents. Thank you. > > -Original Message- > > From: Andrew Jeffery [mailto:and...@aj.id.au]  > Sent: Monday, May 22, 2017 8:24 AM > > To: Philippe Mathieu-Daudé <f4...@amsat.org>; qemu-...@n

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model

Hi Phil, On Sat, 2017-05-20 at 00:21 -0300, Philippe Mathieu-Daudé wrote: > Hi Andrew, > > On 05/19/2017 09:26 PM, Andrew Jeffery wrote: > > This model implements enough behaviour to do basic functionality tests > > such as device initialisation and read out o

Re: [Qemu-devel] [PATCH 0/2] hw/adc: Implement a basic Aspeed ADC model

On Fri, 2017-05-19 at 17:51 -0700, no-re...@patchew.org wrote: > In file included from /tmp/qemu-test/src/hw/adc/aspeed_adc.c:15:0: > /tmp/qemu-test/src/hw/adc/aspeed_adc.c: In function 'aspeed_adc_read': > /tmp/qemu-test/src/hw/adc/aspeed_adc.c:106:34: error: format '%lx' expects > argument of

[Qemu-devel] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model

This model implements enough behaviour to do basic functionality tests such as device initialisation and read out of dummy sample values. The sample value generation strategy is similar to the STM ADC already in the tree. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/adc/Makefil

[Qemu-devel] [PATCH 2/2] hw/arm: Integrate ADC model into Aspeed SoC

Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/arm/aspeed_soc.c | 15 +++ include/hw/arm/aspeed_soc.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5c667d2c35b6..11f9588720d2 100644 --- a/hw/arm/aspeed

[Qemu-devel] [PATCH 0/2] hw/adc: Implement a basic Aspeed ADC model

to the SDK kernel which spins on the initialisation bit, never making forward progress in the absence of the ADC model. Tested with both Aspeed's SDK kernel and upstream Linux. Cheers, Andrew Andrew Jeffery (2): hw/adc: Add basic Aspeed ADC model hw/arm: Integrate ADC model into Aspeed SoC

Re: [Qemu-devel] [PATCH v4 8/8] arm: Add an RX8900 RTC to the ASpeed board

by: Chris Smart <ch...@distroguy.com> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed.c | 29 + >  1 file changed, 29 insertions(+) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 40c1383..ef63fd0 100644 > ---

Re: [Qemu-devel] [PATCH v4 7/8] tests: Test all implemented RX8900 functionality

Hi Alastair, Again, small comments below. On Thu, 2016-12-15 at 16:48 +1100, Alastair D'Silva wrote: > > From: Alastair D'Silva > > > Signed-off-by: Alastair D'Silva > --- >  tests/Makefile.include |   2 + >  tests/rx8900-test.c| 882 >

Re: [Qemu-devel] [PATCH v4 6/8] hw/timer: Add Epson RX8900 RTC support

Hi Alastair, I have some mostly minor comments below. On Thu, 2016-12-15 at 16:48 +1100, Alastair D'Silva wrote: > > From: Alastair D'Silva > > This patch adds support for the Epson RX8900 I2C RTC. > > The following chip features are implemented: >  - RTC (wallclock

Re: [Qemu-devel] [PATCH for-2.9 28/30] aspeed: add a watchdog controller

On Tue, 2016-11-29 at 16:44 +0100, Cédric Le Goater wrote: > This enables reboot of a guest from U-Boot and Linux. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> > Reviewed-by: Joel Stanley <j...@jms.id.au> Reviewed-by: Andrew Jeffery <and...@aj.id.au>

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