ARM_CPU_TYPE_NAME("cortex-a57"),
> --
> 2.26.2
>
So this filters the cpus out of KVM only builds, which seems
reasonable to do. Of course, if the build is for both KVM and
TCG, then the cpus won't be filtered out and we'll have to rely
on the runtime checks to error out if one where to try a 32-bit
cpu with KVM. But that's fine too, so
Reviewed-by: Andrew Jones
Thanks,
drew
-a53"),
> ARM_CPU_TYPE_NAME("cortex-a57"),
> ARM_CPU_TYPE_NAME("cortex-a72"),
> +#endif /* TARGET_AARCH64 */
> ARM_CPU_TYPE_NAME("host"),
> ARM_CPU_TYPE_NAME("max"),
> };
> --
> 2.26.2
>
Reviewed-by: Andrew Jones
On Fri, Feb 05, 2021 at 03:43:42PM +0100, Philippe Mathieu-Daudé wrote:
> The Virt machine is restricted to a subset of the CPU provided
> by QEMU. Instead of having the user run '--cpu help' and try
> each CPUs until finding a match, display the list from start:
>
> $ qemu-system-aarch64 -M
FIX);
> +
> +error_report("mach-virt: CPU type %.*s not supported",
> + len, machine->cpu_type);
> exit(1);
> }
>
> --
> 2.26.2
>
Reviewed-by: Andrew Jones
On Fri, Feb 05, 2021 at 03:43:40PM +0100, Philippe Mathieu-Daudé wrote:
> Only the Virt and Versal machines are supported under KVM.
> Restrict the other ones to TCG.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/cdrom-test.c | 5 -
> 1 file changed, 4 insertions(+), 1
rt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
> +{ "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
>kernel_aarch64 },
> { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
>
> --
> 2.26.2
>
>
Reviewed-by: Andrew Jones
On Fri, Feb 05, 2021 at 03:43:37PM +0100, Philippe Mathieu-Daudé wrote:
> Support for ARMv7 has been dropped in commit 82bf7ae84ce
> ("target/arm: Remove KVM support for 32-bit Arm hosts"),
> no need to check for Cortex A15 host cpu anymore.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
g we would
prefer to work. But, as that appears to be a different bug, regarding this
patch
Reviewed-by: Andrew Jones
Tested-by: Andrew Jones
Thanks,
drew
On Wed, Feb 03, 2021 at 10:45:47AM -0500, Aaron Lindsay wrote:
> On Feb 03 13:44, Andrew Jones wrote:
> > On Wed, Feb 03, 2021 at 10:52:59AM +, Peter Maydell wrote:
> > > On Wed, 3 Feb 2021 at 10:49, Dr. David Alan Gilbert
> > > wrote:
> > > &
On Wed, Feb 03, 2021 at 10:52:59AM +, Peter Maydell wrote:
> On Wed, 3 Feb 2021 at 10:49, Dr. David Alan Gilbert
> wrote:
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Wed, 3 Feb 2021 at 10:28, Dr. David Alan Gilbert
> > > wrote:
> > > >
> > > > * Philippe
On Fri, Jan 22, 2021 at 10:09:35AM +, Peter Maydell wrote:
> On Fri, 22 Jan 2021 at 08:29, Andrew Jones wrote:
> >
> > On Wed, Jan 20, 2021 at 12:27:48PM +0300, Maxim Uvarov wrote:
> > > Add secure pl061 for reset/power down machine from
> > > the secure worl
On Wed, Jan 20, 2021 at 12:27:48PM +0300, Maxim Uvarov wrote:
> Add secure pl061 for reset/power down machine from
> the secure world (Arm Trusted Firmware). Connect it
> with gpio-pwr driver.
>
> Signed-off-by: Maxim Uvarov
> ---
> hw/arm/Kconfig| 1 +
> hw/arm/virt.c | 47
", "okay");
> +}
nit: The above if-block could/should have waited until the next patch to
be added.
> g_free(nodename);
> +
> +/* Child gpio devices */
> +if (gpio == VIRT_GPIO) {
Same nit as above, the next patch is where we should start conditionally
doing stuff based on the gpio type.
> +create_gpio_keys(vms, pl061_dev, phandle);
> +}
> }
>
> static void create_virtio_devices(const VirtMachineState *vms)
> @@ -1990,7 +2012,7 @@ static void machvirt_init(MachineState *machine)
> if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
> vms->acpi_dev = create_acpi_ged(vms);
> } else {
> -create_gpio(vms);
> +create_gpio_devices(vms, VIRT_GPIO, sysmem);
> }
>
> /* connect powerdown request */
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
Thanks,
drew
rget/riscv/arch_dump.c
>
I gave my r-b on the last review and the only change in this version
is the suggestion I made. Anyway, here's my r-b again
Reviewed-by: Andrew Jones
Thanks,
drew
On Thu, Jan 14, 2021 at 05:50:29PM +0300, Maxim Uvarov wrote:
> v6: - 64k align gpio memory region (Andrew Jones)
> - adjusted memory region to map this address in the corresponding atf
> patch
> v5: - removed vms flag, added fdt (Andrew Jones)
> - added patch3 to
mc flag.
>
> Regards,
> Maxim.
>
> On Tue, 12 Jan 2021 at 19:28, Andrew Jones wrote:
> >
> > On Tue, Jan 12, 2021 at 11:25:30AM -0500, Andrew Jones wrote:
> > > On Tue, Jan 12, 2021 at 04:00:23PM +, Peter Maydell wrote:
> > > > On Tue, 12 Jan 2021 at
On Tue, Jan 12, 2021 at 11:25:30AM -0500, Andrew Jones wrote:
> On Tue, Jan 12, 2021 at 04:00:23PM +, Peter Maydell wrote:
> > On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote:
> > >
> > > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote:
> > >
On Tue, Jan 12, 2021 at 04:00:23PM +, Peter Maydell wrote:
> On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote:
> >
> > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote:
> > > Add secure pl061 for reset/power down machine from
> > > the secure worl
On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote:
> Add secure pl061 for reset/power down machine from
> the secure world (Arm Trusted Firmware). Connect it
> with gpio-pwr driver.
>
> Signed-off-by: Maxim Uvarov
> ---
> hw/arm/Kconfig| 1 +
> hw/arm/virt.c | 40
tion defined algorithm.
>
> We need two intermediate booleans to control the state while
> parsing properties lest we clobber ID_AA64ISAR1 into an invalid
> intermediate state.
>
> Tested-by: Mark Rutland
> Reviewed-by: Andrew Jones
> Signed-off-by: Richard Henderson
> -
t riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
> int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 24b24c69c5..d7259561e7 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -368,6 +368,7 @@
> #define MSTATUS_MIE 0x0008
> #define MSTATUS_UPIE0x0010
> #define MSTATUS_SPIE0x0020
> +#define MSTATUS_UBE 0x0040
> #define MSTATUS_MPIE0x0080
> #define MSTATUS_SPP 0x0100
> #define MSTATUS_MPP 0x1800
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 14a5c62dac..88ab850682 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -26,6 +26,7 @@ riscv_ss.add(files(
>
> riscv_softmmu_ss = ss.source_set()
> riscv_softmmu_ss.add(files(
> + 'arch_dump.c',
>'pmp.c',
>'monitor.c',
>'machine.c'
> --
> 2.19.1
>
>
Besides the missing build-bug question,
Reviewed-by: Andrew Jones
Thanks,
drew
> +/* Make sure start and size are qemu_real_host_page_size aligned */
> +assert(QEMU_IS_ALIGNED(start | size, psize));
> +
> /*
> * We need to extend either the start or the size or both to
> * satisfy the KVM interface requirement. Firstly, do the start
> --
> 2.23.0
>
>
Reviewed-by: Andrew Jones
On Tue, Dec 15, 2020 at 12:55:50PM +0100, Andrew Jones wrote:
> On Tue, Dec 15, 2020 at 03:19:48PM +0800, Keqian Zhu wrote:
> > The parameters start and size are transfered from QEMU memory
> > emulation layer. It can promise that they are TARGET_PAGE_SIZE
> > aligne
On Tue, Dec 15, 2020 at 06:20:48PM +, David Edmondson wrote:
> On Tuesday, 2020-12-15 at 18:48:15 +01, Andrew Jones wrote:
>
> > virt machine's 'smp_cpus' and machine->smp.cpus must always have the
> > same value. And, anywhere we have virt machine state we have machin
On Fri, Nov 20, 2020 at 01:43:19PM +0100, Andrew Jones wrote:
> On Tue, Nov 17, 2020 at 06:27:54PM +0800, Ying Fang wrote:
> >
> >
> > On 11/9/2020 6:45 PM, Salil Mehta wrote:
> > > Hi Fangying,
> > > A trivial thing. This patch looks bit of a noise
",
avoid passing them in function parameters, preferring instead to get
them from the state.
No functional change intended.
Signed-off-by: Andrew Jones
---
hw/arm/virt-acpi-build.c | 9 +
hw/arm/virt.c| 24 +++-
include/hw/arm/virt.h| 3 +--
3 fi
On Tue, Dec 15, 2020 at 03:19:48PM +0800, Keqian Zhu wrote:
> The parameters start and size are transfered from QEMU memory
> emulation layer. It can promise that they are TARGET_PAGE_SIZE
> aligned. However, KVM needs they are qemu_real_page_size aligned.
>
> Though no caller breaks this aligned
>> TARGET_PAGE_BITS),
> +hwaddr bitmap_size = ALIGN(mem->memory_size / qemu_real_host_page_size,
> /*HOST_LONG_BITS*/ 64) / 8;
> mem->dirty_bmap = g_malloc0(bitmap_size);
> }
> --
> 2.23.0
>
>
Besides the commit message
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Nov 25, 2020 at 09:45:19AM +0100, David Hildenbrand wrote:
> On 25.11.20 09:38, Andrew Jones wrote:
> > On Tue, Nov 24, 2020 at 08:17:35PM +0100, David Hildenbrand wrote:
> >> On 24.11.20 19:11, Jonathan Cameron wrote:
> >>> On Mon, 9 Nov 2020 20:47:09 +0100
On Tue, Nov 24, 2020 at 08:17:35PM +0100, David Hildenbrand wrote:
> On 24.11.20 19:11, Jonathan Cameron wrote:
> > On Mon, 9 Nov 2020 20:47:09 +0100
> > David Hildenbrand wrote:
> >
> > +CC Eric based on similar query in other branch of the thread.
> >
> >> On 05.11.20 18:43, Jonathan Cameron
On Tue, Nov 17, 2020 at 06:27:54PM +0800, Ying Fang wrote:
>
>
> On 11/9/2020 6:45 PM, Salil Mehta wrote:
> > Hi Fangying,
> > A trivial thing. This patch looks bit of a noise in this patch-set. Better
> > to send it as a separate patch-set and get it accepted.
> >
> Hmm, this patch looks like
On Thu, Nov 19, 2020 at 03:45:40PM +, Peter Maydell wrote:
> On Thu, 19 Nov 2020 at 15:39, Steven Price wrote:
> > This series adds support for Arm's Memory Tagging Extension (MTE) to
> > KVM, allowing KVM guests to make use of it. This builds on the existing
> > user space support already in
On Wed, Nov 18, 2020 at 04:50:01PM +, Catalin Marinas wrote:
> On Wed, Nov 18, 2020 at 04:01:20PM +, Steven Price wrote:
> > On 17/11/2020 16:07, Catalin Marinas wrote:
> > > On Mon, Oct 26, 2020 at 03:57:27PM +, Steven Price wrote:
> > > > diff --git a/arch/arm64/kvm/mmu.c
On Wed, Nov 11, 2020 at 04:00:25PM +, Peter Maydell wrote:
> On Wed, 11 Nov 2020 at 15:05, Miroslav Rezanina wrote:
> >
> > - Original Message -
> > > From: "Andrew Jones"
> > > To: qemu-devel@nongnu.org, qemu-...@nongnu.org
&g
The removal of the selection of A15MPCORE from ARM_VIRT also
removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore
peripherals")
Reported-by: Miroslav Rezanina
Signed-off-by: Andrew Jones
---
hw/a
ha...@gmail.com; alistair.fran...@wdc.com;
> > Zhanghailiang ; Salil Mehta
> >
> > Subject: [RFC PATCH v3 03/13] hw/arm/virt: Replace smp_parse with one that
> > prefers cores
> >
> > From: Andrew Jones
> >
> > The virt machine type has never used the CP
On Wed, Nov 04, 2020 at 11:11:53AM +0100, Philippe Mathieu-Daudé wrote:
> On 11/4/20 11:03 AM, Andrew Jones wrote:
> > On Tue, Oct 27, 2020 at 11:44:38AM +, Peter Maydell wrote:
> >> The armv7m systick timer is a 24-bit decrementing, wrap-on-zero,
> >> clear-on
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
changed armv7m_systick to build on ptimers. Make sure we have ptimers
in the build when building armv7m_systick.
Signed-off-by: Andrew Jones
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --gi
On Tue, Oct 27, 2020 at 11:44:38AM +, Peter Maydell wrote:
> The armv7m systick timer is a 24-bit decrementing, wrap-on-zero,
> clear-on-write counter. Our current implementation has various
> bugs and dubious workarounds in it (for instance see
> https://bugs.launchpad.net/qemu/+bug/1872237).
On Tue, Oct 20, 2020 at 09:14:35PM +0800, Ying Fang wrote:
> Add the processor hierarchy node structures to build ACPI information
> for CPU topology. Three helpers are introduced:
>
> (1) build_socket_hierarchy for socket description structure
> (2) build_processor_hierarchy for processor
e enabled.
>
> Signed-off-by: Andrew Jones
I guess my s-o-b is here because this is a rework of
https://github.com/rhdrjones/qemu/commit/b18d7a889f424b8a8679c43d7f4804fdeeeaf3fd
I think it changed enough you could just drop my authorship. A
based-on comment in the commit message would be m
On Tue, Oct 20, 2020 at 09:14:32PM +0800, Ying Fang wrote:
> Add 5.2 machine types for arm/i440fx/q35/s390x/spapr.
^ 5.3
Thanks,
drew
>
> Signed-off-by: Ying Fang
> ---
> hw/arm/virt.c | 9 -
> hw/core/machine.c | 3 +++
> hw/i386/pc.c | 3
On Tue, Oct 20, 2020 at 09:14:36PM +0800, Ying Fang wrote:
> Add the Processor Properties Topology Table (PPTT) to present CPU topology
> information to the guest.
>
> Signed-off-by: Andrew Jones
I don't know why I have an s-o-b here. I guess it's because this code
looks near
On Tue, Oct 20, 2020 at 09:14:35PM +0800, Ying Fang wrote:
> Add the processor hierarchy node structures to build ACPI information
> for CPU topology. Three helpers are introduced:
>
> (1) build_socket_hierarchy for socket description structure
> (2) build_processor_hierarchy for processor
On Mon, Oct 26, 2020 at 01:22:19PM -0400, Eduardo Habkost wrote:
> I've been trying to clean up the qdev property code (to bridge
> the gaps between qdev and QOM, and between QOM and QAPI), and
> I've noticed that TYPE_ARM_CPU is the only remaining user of
> qdev_property_add_static().
>
>
On Tue, Oct 20, 2020 at 10:52:11AM +0800, Ying Fang wrote:
>
>
> On 10/16/2020 6:07 PM, Andrew Jones wrote:
> > On Fri, Oct 16, 2020 at 05:40:02PM +0800, Ying Fang wrote:
> > >
> > >
> > > On 10/15/2020 3:59 PM, Andrew Jones wrote:
> > > &g
On Mon, Oct 19, 2020 at 03:58:40PM +0100, Dave Martin wrote:
> On Mon, Oct 19, 2020 at 03:18:11PM +0100, Peter Maydell wrote:
> > On Mon, 19 Oct 2020 at 14:40, Andrew Jones wrote:
> > >
> > > On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote:
> &
On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote:
> On Mon, 19 Oct 2020 at 12:32, Dave Martin wrote:
> > I'm not quite sure about Peter's assessment here.
> >
> > I agree with the inconsistency identified here: we always enumerate all
> > unallocated ID regs, but we enumerate
On Thu, Oct 15, 2020 at 03:57:02PM +0100, Peter Maydell wrote:
> On Thu, 15 Oct 2020 at 15:41, Andrew Jones wrote:
> > The reporter states neither the source nor destination hardware supports
> > SVE. My guess is that what's happening is the reserved ID register
> &g
On Fri, Oct 16, 2020 at 05:40:02PM +0800, Ying Fang wrote:
>
>
> On 10/15/2020 3:59 PM, Andrew Jones wrote:
> > On Thu, Oct 15, 2020 at 10:07:16AM +0800, Ying Fang wrote:
> > >
> > >
> > > On 10/14/2020 2:08 AM, Andrew Jones wrote:
> > > >
On Thu, Oct 15, 2020 at 02:52:34PM +0100, Marc Zyngier wrote:
> On 2020-10-15 14:35, Andrew Jones wrote:
> > On Thu, Oct 15, 2020 at 12:26:10PM +0100, Marc Zyngier wrote:
> > > Hi
> > >
> > > Please don't use my arm.com address anymore, nobody reads it...
&
On Thu, Oct 15, 2020 at 12:26:10PM +0100, Marc Zyngier wrote:
> Hi
>
> Please don't use my arm.com address anymore, nobody reads it...
>
> On 2020-10-15 05:06, 张东旭 wrote:
> > I'm so sorry for disturbing you.
> >
> > When I apply this kernel patch：KVM: arm64/sve: System register
> > context
On Thu, Oct 15, 2020 at 12:06:39PM +0800, 张东旭 wrote:
> I'm so sorry for disturbing you.When I apply this kernel patch：KVM:
> arm64/sve: System register context switch and access
>
On Thu, Oct 15, 2020 at 10:07:16AM +0800, Ying Fang wrote:
>
>
> On 10/14/2020 2:08 AM, Andrew Jones wrote:
> > On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
> > > Cc valentin
> > >
> > > > -Original Message-
> > >
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
> Cc valentin
>
> > -Original Message-
> > From: Qemu-devel
> > [mailto:qemu-devel-bounces+prime.zeng=hisilicon@nongnu.org]
> > On Behalf Of Ying Fang
> > Sent: Thursday, September 17, 2020 11:20 AM
> > To:
Hi Peter,
Thanks for fixing this up and applying!
drew
On Thu, Oct 08, 2020 at 09:39:59PM +0100, Peter Maydell wrote:
> On Thu, 1 Oct 2020 at 07:17, Andrew Jones wrote:
> >
> > We add the kvm-steal-time CPU property and implement it for machvirt.
> > A tiny bit of refa
On Fri, Oct 02, 2020 at 04:38:11PM +0100, Steven Price wrote:
> On 02/10/2020 15:36, Andrew Jones wrote:
> > On Fri, Sep 25, 2020 at 10:36:05AM +0100, Steven Price wrote:
> > > Version 3 of adding MTE support for KVM guests. See the previous (v2)
> > > posting for backg
On Fri, Oct 02, 2020 at 04:30:47PM +0100, Steven Price wrote:
> On 02/10/2020 15:30, Andrew Jones wrote:
> > On Fri, Sep 25, 2020 at 10:36:07AM +0100, Steven Price wrote:
> > > + if (system_supports_mte() && kvm->arch.mte_enabled && pfn_valid(pfn)) {
&
On Fri, Sep 25, 2020 at 10:36:05AM +0100, Steven Price wrote:
> Version 3 of adding MTE support for KVM guests. See the previous (v2)
> posting for background:
>
> https://lore.kernel.org/r/20200904160018.29481-1-steven.price%40arm.com
>
> These patches add support to KVM to enable MTE within a
const struct sys_reg_desc *rd)
> {
> + if (vcpu->kvm->arch.mte_enabled)
> + return 0;
> +
> return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
> }
>
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index f6d86033c4fa..87678ed82ab4 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -1035,6 +1035,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_LAST_CPU 184
> #define KVM_CAP_SMALLER_MAXPHYADDR 185
> #define KVM_CAP_S390_DIAG318 186
> +#define KVM_CAP_ARM_MTE 188
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
> --
> 2.20.1
>
>
Besides the helper suggestion nit
Reviewed-by: Andrew Jones
SYS_ERXMISC0_EL1), trap_raz_wi },
> { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
>
> - { SYS_DESC(SYS_TFSR_EL1), access_mte_regs },
> - { SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs },
> + { SYS_DESC(SYS_TFSR_EL1), access_mte_regs, reset_unknown, TFSR_EL1,
> .visibility = mte_visibility },
> + { SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs, reset_unknown, TFSRE0_EL1,
> .visibility = mte_visibility },
>
> { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
> { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
> --
> 2.20.1
>
>
Reviewed-by: Andrew Jones
We add the kvm-steal-time CPU property and implement it for machvirt.
A tiny bit of refactoring was also done to allow pmu and pvtime to
use the same vcpu device helper functions.
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
docs/system/arm/cpu-features.rst | 11 ++
hw/arm
arm-cpu-features got dropped from the AArch64 tests during the meson
conversion shuffle.
Signed-off-by: Andrew Jones
---
tests/qtest/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 874b5be62be2
We'll add more to this new function in coming patches so we also
state the gic must be created and call it below create_gic().
No functional change intended.
Reviewed-by: Eric Auger
Reviewed-by: Peter Maydell
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 43
Update against Linux 5.9-rc7.
Cc: Paolo Bonzini
Signed-off-by: Andrew Jones
---
linux-headers/linux/kvm.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 6683e2e1b0a0..43580c767c33 100644
--- a/linux-headers
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 524eafe22df8..92ab0fd094dc 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -521,21 +521,12
interface. This feature is only available for 64-bit guests
per the Arm PVTIME specification (DEN0057A).
This series provides the QEMU support of this feature. It will
be enabled by default for 5.2 machine types and later, but may
be disabled with a new CPU property "kvm-steal-time".
T
/put_virtual_time(), as they aren't
necessary at all - the only caller is in kvm.c
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
target/arm/kvm_arm.h | 51 +++-
1 file changed, 32 insertions(+), 19 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target
On Wed, Sep 23, 2020 at 05:10:31PM +0100, Stefan Hajnoczi wrote:
> clang's C11 atomic_fetch_*() functions only take a C11 atomic type
> pointer argument. QEMU uses direct types (int, etc) and this causes a
> compiler error when a QEMU code calls these functions in a source file
> that also
On Tue, Sep 29, 2020 at 04:47:33PM +0200, Andrew Jones wrote:
>
> Hi Peter, Eric, and other interested parties,
>
> Here's a gentle ping for reviewers.
Thanks for the review Eric! I'll send a Linux header update patch and a
rebase of this series with R-b's.
drew
>
&
Hi Peter, Eric, and other interested parties,
Here's a gentle ping for reviewers.
Thanks,
drew
On Wed, Sep 16, 2020 at 11:26:15AM +0200, Andrew Jones wrote:
> Previous posting:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg727588.html
>
> v3:
> - Rebased: 5
On Fri, Sep 18, 2020 at 12:25:19AM +, Salil Mehta wrote:
>
> > From: Qemu-arm [mailto:qemu-arm-bounces+salil.mehta=huawei@nongnu.org]
> > On Behalf Of Andrew Jones
> > Sent: Thursday, September 17, 2020 9:13 AM
> > To: fangying
> > Cc: peter.
On Thu, Sep 17, 2020 at 09:19:34PM +0800, Ying Fang wrote:
>
>
> On 9/17/2020 6:59 PM, Andrew Jones wrote:
> > On Thu, Sep 17, 2020 at 09:53:35AM +0200, Andrew Jones wrote:
> > > On Thu, Sep 17, 2020 at 11:20:23AM +0800, Ying Fang wrote:
> > > > MPI
On Thu, Sep 17, 2020 at 09:53:35AM +0200, Andrew Jones wrote:
> On Thu, Sep 17, 2020 at 11:20:23AM +0800, Ying Fang wrote:
> > MPIDR helps to provide an additional PE identification in a multiprocessor
> > system. This patch adds support for setting MPIDR from userspace, so
On Thu, Sep 17, 2020 at 11:20:30AM +0800, Ying Fang wrote:
> Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus.
> A classic three level cache topology is used here. The default cache
> capacity is given and userspace can overwrite these values.
Doesn't TCG already have
On Thu, Sep 17, 2020 at 11:20:29AM +0800, Ying Fang wrote:
> Add the Processor Properties Topology Table (PPTT) to present CPU topology
> information to the guest.
>
> Signed-off-by: Andrew Jones
> Signed-off-by: Ying Fang
> ---
> hw/arm/v
On Thu, Sep 17, 2020 at 11:20:28AM +0800, Ying Fang wrote:
> Add the processor hierarchy node structures to build ACPI information
> for CPU topology. Three helpers are introduced:
>
> (1) build_socket_hierarchy for socket description structure
> (2) build_processor_hierarchy for processor
On Thu, Sep 17, 2020 at 11:20:25AM +0800, Ying Fang wrote:
> From: Andrew Jones
>
> qemu_fdt_add_path works like qemu_fdt_add_subnode, except it
> also recursively adds any missing parent nodes.
>
> Cc: Peter Crosthwaite
> Cc: Alexander Graf
> Sig
On Thu, Sep 17, 2020 at 11:20:27AM +0800, Ying Fang wrote:
> When building ACPI tables regarding CPUs we should always build
> them for the number of possible CPUs, not the number of present
> CPUs. We then ensure only the present CPUs are enabled.
>
> Signed-off-by: Andrew Jone
On Thu, Sep 17, 2020 at 11:20:24AM +0800, Ying Fang wrote:
> MPIDR helps to provide an additional PE identification in a multiprocessor
> system. This patch adds support for setting MPIDR from userspace, so that
> MPIDR is consistent with CPU topology configured.
>
> Signed-off-by: Ying Fang
>
On Thu, Sep 17, 2020 at 11:20:26AM +0800, Ying Fang wrote:
> From: Andrew Jones
>
> Support devicetree CPU topology descriptions.
>
> Signed-off-by: Andrew Jones
There's a new version of this patch on the refresh branch.
https://github.com/rhdrjones/qemu/commits/virt-cpu-t
On Thu, Sep 17, 2020 at 11:20:23AM +0800, Ying Fang wrote:
> MPIDR helps to provide an additional PE identification in a multiprocessor
> system. This patch adds support for setting MPIDR from userspace, so that
> MPIDR is consistent with CPU topology configured.
>
> Signed-off-by: Ying Fang
>
We add the kvm-steal-time CPU property and implement it for machvirt.
A tiny bit of refactoring was also done to allow pmu and pvtime to
use the same vcpu device helper functions.
Signed-off-by: Andrew Jones
---
docs/system/arm/cpu-features.rst | 11 ++
hw/arm/virt.c| 43
---
linux-headers/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index a28c3667370b..924672cca1f1 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1031,6 +1031,7 @@ struct kvm_ppc_resize_hpt {
-off-by: Andrew Jones
---
hw/arm/virt.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2cba21fe3ad9..6797eb397a7a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -521,21 +521,12 @@ static void
We'll add more to this new function in coming patches so we also
state the gic must be created and call it below create_gic().
No functional change intended.
Reviewed-by: Eric Auger
Reviewed-by: Peter Maydell
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 43
/put_virtual_time(), as they aren't
necessary at all - the only caller is in kvm.c
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
target/arm/kvm_arm.h | 51 +++-
1 file changed, 32 insertions(+), 19 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target
e disabled with a new CPU property "kvm-steal-time".
Thanks,
drew
Andrew Jones (5):
target/arm/kvm: Make uncalled stubs explicitly unreachable
hw/arm/virt: Move post cpu realize check into its own function
hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
DO NOT MERGE: HACK: Ad
Hi Paolo,
I noticed that 'make check-qtest-aarch64' no longer runs the
arm-cpu-feature test. I simply did
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 874b5be62be2..db169a53b530 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -146,7 +146,8 @@
On Tue, Sep 15, 2020 at 03:03:49PM +0800, Haibo Xu wrote:
> On Tue, 15 Sep 2020 at 14:22, Andrew Jones wrote:
> >
> > On Tue, Sep 15, 2020 at 03:11:43AM +, Haibo Xu wrote:
> > > From: Andrew Jones
> > >
> > > We'll add more to this new functio
.c | 1 +
> target/arm/cpu.h | 2 ++
> target/arm/cpu64.c | 10 +++---
> target/arm/kvm64.c | 12
> 4 files changed, 22 insertions(+), 3 deletions(-)
Reviewed-by: Andrew Jones
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 786cc6134c..
On Tue, Sep 15, 2020 at 03:11:43AM +, Haibo Xu wrote:
> From: Andrew Jones
>
> We'll add more to this new function in coming patches so we also
> state the gic must be created and call it below create_gic().
>
> No functional change intended.
>
> Signed-off-by:
On Tue, Sep 15, 2020 at 03:11:39AM +, Haibo Xu wrote:
> Adds a spe=[on/off] option to enable/disable vSPE support in
> guest vCPU.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Haibo Xu
> ---
> target/arm/cpu.c | 6 ++
> target/arm/cpu.h | 13 ++
On Thu, Sep 10, 2020 at 05:17:17PM +0100, Peter Maydell wrote:
> On Thu, 10 Sep 2020 at 16:06, Derrick McKee wrote:
> >
> > Hi,
> >
> > As of commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a compiled with the
> > default configuration, softmmu-aarch64 issues an illegal instruction fault
> > when
On Thu, Sep 10, 2020 at 10:21:04AM +0100, Steven Price wrote:
> On 10/09/2020 07:29, Andrew Jones wrote:
> > But if userspace created the memslots with memory already set with
> > PROT_MTE, then this wouldn't be necessary, right? And, as long as
> > there's still a way
On Thu, Sep 10, 2020 at 02:27:48PM +0100, Dr. David Alan Gilbert wrote:
> * Andrew Jones (drjo...@redhat.com) wrote:
> > On Wed, Sep 09, 2020 at 06:45:33PM -0700, Richard Henderson wrote:
> > > On 9/9/20 8:25 AM, Andrew Jones wrote:
> > > >> * Provide a KVM-sp
On Thu, Sep 10, 2020 at 10:21:07AM +0100, Steven Price wrote:
> > We either need a KVM cap or a new CPU feature probing interface to avoid
> > making userspace try features one at a time. It's too bad that VCPU_INIT
> > doesn't clear all offending features from the feature set when returning
> >
On Thu, Sep 10, 2020 at 08:38:54AM +0200, Andrew Jones wrote:
> On Wed, Sep 09, 2020 at 04:53:02PM +0100, Peter Maydell wrote:
> > On Wed, 9 Sep 2020 at 16:48, Andrew Jones wrote:
> > > We either need a KVM cap or a new CPU feature probing interface to avoid
> > > ma
On Wed, Sep 09, 2020 at 04:53:02PM +0100, Peter Maydell wrote:
> On Wed, 9 Sep 2020 at 16:48, Andrew Jones wrote:
> > We either need a KVM cap or a new CPU feature probing interface to avoid
> > making userspace try features one at a time. It's too bad that VCPU_INIT
> &
On Wed, Sep 09, 2020 at 05:04:15PM +0100, Steven Price wrote:
> On 09/09/2020 16:25, Andrew Jones wrote:
> > On Fri, Sep 04, 2020 at 05:00:16PM +0100, Steven Price wrote:
> > > 2. Automatically promotes (normal host) memory given to the guest to be
> > > tag
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