Re: [PATCH 0/3] Assorted fixes for PMU

On Tue, May 14, 2024 at 2:16 AM Peter Maydell wrote: > > On Mon, 29 Apr 2024 at 20:29, Atish Patra wrote: > > > > This series contains few miscallenous fixes related to hpmcounters > > and related code. The first patch fixes an issue with cycle/instret > &

Re: [PATCH 0/3] Assorted fixes for PMU

On Tue, May 14, 2024 at 3:18 AM Alistair Francis wrote: > > On Tue, May 14, 2024 at 5:15 PM Atish Kumar Patra wrote: > > > > On Mon, May 13, 2024 at 11:29 PM Alistair Francis > > wrote: > > > > > > On Tue, Apr 30, 2024 at 5:29 AM Atish Patra wrote

[PATCH 0/3] Assorted fixes for PMU

This series contains few miscallenous fixes related to hpmcounters and related code. The first patch fixes an issue with cycle/instret counters overcouting while the remaining two are more for specification compliance. Signed-off-by: Atish Patra --- Atish Patra (3): target/riscv: Save

[PATCH 1/3] target/riscv: Save counter values during countinhibit update

the counter is stopped. Thus, save the value of the counter during the inhibit update operation and return that value during the read if corresponding bit in mcountihibit is set. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 - target/riscv/csr.c | 32

[PATCH 3/3] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PATCH 2/3] target/riscv: Enforce WARL behavior for scounteren/hcounteren

scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra --- target/riscv/csr.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git

Re: [PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

On 3/19/24 21:54, Alistair Francis wrote: On Thu, Mar 7, 2024 at 7:26 PM Atish Patra wrote: On 3/4/24 22:47, LIU Zhiwei wrote: On 2024/2/29 2:51, Atish Patra wrote: Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode

Re: [PATCH v5 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

On 3/4/24 23:01, LIU Zhiwei wrote: On 2024/2/29 2:51, Atish Patra wrote: From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue ---   target/riscv/cpu.c | 2 ++   target/riscv

Re: [PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

On 3/4/24 22:47, LIU Zhiwei wrote: On 2024/2/29 2:51, Atish Patra wrote: Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode switch. This patch implements that for both cycle/instret and mhpmcounters. The first one requires

[PATCH v5 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35

[PATCH v5 0/5] Add ISA extension smcntrpmf support

d Kevin's personal email address. [1] https://github.com/riscv/riscv-smcntrpmf [2] https://github.com/atishp04/qemu/tree/smcntrpmf_v5 Atish Patra (2): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Implement privilege mode filtering for cycle/instret Kaiwen Xue (3):

[PATCH v5 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h| 11 + target/riscv/cpu_bits.h | 5

[PATCH v5 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c

[PATCH v5 4/5] target/riscv: Add cycle & instret privilege mode filtering support

-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 88 ++ 1 file changed, 88 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a3d979c4c72c..ff9bac537593 100644 --- a/target/riscv

Re: [PATCH] target/riscv: Add missing include guard in pmu.h

State *env, uint64_t value,     uint32_t ctr_idx); + +#endif /* RISCV_PMU_H */ Oops. Thanks for the fix. Reviewed-by: Atish Patra

Re: [PATCH RFC 0/8] Add Counter delegation ISA extension support

like he is okay with the series now (no further questions).  Let me respin both the series.     One more thing:     On 2/16/24 21:01, Atish Patra wrote: > This series adds the counter delegation extension support. The counter > delegation ISA extension(Smcdeleg

[PATCH RFC 4/8] target/riscv: Support generic CSR indirect access

. Co-developed-by: Atish Patra Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu_bits.h | 28 +++- target/riscv/csr.c | 146 +++- 2 files changed, 169 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target

[PATCH RFC 3/8] target/riscv: Enable S*stateen bits for AIA

in the CSR accessor functions. Signed-off-by: Atish Patra --- target/riscv/csr.c | 89 +- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1af0c8890a2b..89a1325a02a5 100644 --- a/target/riscv/csr.c

[PATCH RFC 5/8] target/riscv: Add smcdeleg/ssccfg properties

From: Kaiwen Xue This adds the properties of smcdeleg/ssccfg. Implementation will be in future patches. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 4 target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b

[PATCH RFC 7/8] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv

[PATCH RFC 1/8] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 4 target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 6 insertions

[PATCH RFC 6/8] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++- target/riscv/machine.c | 1 + 3

[PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 147 + 1 file changed

[PATCH RFC 8/8] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Signed

[PATCH RFC 0/8] Add Counter delegation ISA extension support

m/atishp04/opensbi/tree/counter_delegation_v1 The Linux kernel patches can be found here: https://github.com/atishp04/linux/tree/counter_delegation_rfc [1] https://github.com/riscv/riscv-indirect-csr-access [2] https://github.com/riscv/riscv-smcdeleg-ssccfg Atish Patra (1): target/riscv: Enable S*st

[PATCH v4 4/5] target/riscv: Add cycle & instret privilege mode filtering support

-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 80 ++ 1 file changed, 80 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 283468bbc652..3bd4aa22374f 100644 --- a/target/riscv

[PATCH v4 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h| 11 + target/riscv/cpu_helper.c | 9

[PATCH v4 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c

[PATCH v4 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35

[PATCH v4 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PATCH v4 0/5] Add ISA extension smcntrpmf support

qemu/tree/smcntrpmf_v3 Atish Patra (2): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Implement privilege mode filtering for cycle/instret Kaiwen Xue (3): target/riscv: Add cycle & instret privilege mode filtering properties target/riscv: Add cycle & instr

[PATCH v3 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35 insertions(+) diff --git a/target/riscv/cpu.h

[PATCH v3 4/5] target/riscv: Add cycle & instret privilege mode filtering support

-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 80 ++ 1 file changed, 80 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 283468bbc652..3bd4aa22374f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c

[PATCH v3 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c

[PATCH v3 0/5] Add ISA extension smcntrpmf support

tering for both icount and host ticks mode. 1. Addressed comments in v1. 2. Added Kevin's personal email address. [1] https://github.com/riscv/riscv-smcntrpmf [2] https://github.com/atishp04/qemu/tree/smcntrpmf_v3 Atish Patra (2): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target

[PATCH v3 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h| 11 + target/riscv/cpu_helper.c | 9

[PATCH v3 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[v2 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git

[v2 4/5] target/riscv: Add cycle & instret privilege mode filtering support

-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 1 + target/riscv/csr.c | 83 ++ 2 files changed, 84 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 54395f95b299..d24f7ff8b55b 100644 --- a/target/riscv/cpu.c

[v2 0/5] Add ISA extension smcntrpmf support

tps://github.com/riscv/riscv-smcntrpmf [2] https://github.com/atishp04/qemu/tree/smcntrpmf_v1 Atish Patra (2): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Implement privilege mode filtering for cycle/instret Kaiwen Xue (3): target/riscv: Add cycle & instret privile

[v2 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Signed-off-by: Atish Patra --- target/riscv/

[v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 - target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 3 files changed, 35 insertions

[v2 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Signed-off-by: Atish Patra --- target/riscv/cpu.h| 11 + target/riscv/cpu_helper.c | 9 +++- target/riscv/csr.c| 95

[v2 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Signed-off-by: Atish Patra --- target/riscv/cpu.h| 11 + target/riscv/cpu_helper.c | 9 +++- target/riscv/csr.c| 95

[v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 - target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 3 files changed, 35 insertions

[v2 0/5] Add ISA extension smcntrpmf support

tps://github.com/riscv/riscv-smcntrpmf [2] https://github.com/atishp04/qemu/tree/smcntrpmf_v1 Atish Patra (2): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Implement privilege mode filtering for cycle/instret Kaiwen Xue (3): target/riscv: Add cycle & instret privile

[v2 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Signed-off-by: Atish Patra --- target/riscv/

[v2 4/5] target/riscv: Add cycle & instret privilege mode filtering support

-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 1 + target/riscv/csr.c | 83 ++ 2 files changed, 84 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 54395f95b299..d24f7ff8b55b 100644 --- a/target/riscv/cpu.c

[v2 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini wrote: > > Queued, thanks. > I didn't realize it was already queued. Gmail threads failed me this time. @Paolo Bonzini : Can you please drop this one as this will break as soon as the host riscv system has the latest kernel ? I have provided more

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

On Thu, Sep 7, 2023 at 8:33 PM LIU Zhiwei wrote: > > From: LIU Zhiwei > > Signed-off-by: LIU Zhiwei > --- > include/qemu/timer.h | 19 +++ > 1 file changed, 19 insertions(+) > > diff --git a/include/qemu/timer.h b/include/qemu/timer.h > index 9a91cb1248..105767c195 100644 > ---

Re: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

> +/* WARL register - disable unavailable counters */ > +env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | > COUNTEREN_TM | > + COUNTEREN_IR); > return RISCV_EXCP_NONE; > } > > -- > 2.41.0 > > LGTM. Reviewed-by: Atish Patra -- Regards, Atish

Re: Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type)

On Fri, Jul 14, 2023 at 5:29 AM Conor Dooley wrote: > > On Fri, Jul 14, 2023 at 11:19:34AM +0100, Conor Dooley wrote: > > On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup Patel wrote: > > > > > > > OpenSBI v1.3 > > > > >_ _ > > > > > / __ \

[PATCH v3] hw/riscv: virt: Remove the redundant ipi-id property

/ Signed-off-by: Atish Patra --- Changes from v2->v3: 1. Fix the compilation issue by removing the other usage of VIRT_IRQCHIP_IPI_MSI --- --- hw/riscv/virt.c | 4 include/hw/riscv/virt.h | 1 - 2 files changed, 5 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c in

Re: [PATCH] riscv: Add RISCVCPUConfig.satp_mode to set sv48, sv57, etc.

+ > +uint8_t satp_mode; > +char *satp_mode_str; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5c9a7ee287..d26b830f1a 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1109,10 +1109,12 @@ static RISCVException read_mstatus(CPURISCVState > *env, int csrno, > > static int validate_vm(CPURISCVState *env, target_ulong vm) > { > +vm &= 0xf; > + > if (riscv_cpu_mxl(env) == MXL_RV32) { > -return valid_vm_1_10_32[vm & 0xf]; > +return valid_vm_1_10_32[vm] && (vm <= > RISCV_CPU(env_cpu(env))->cfg.satp_mode); > } else { > -return valid_vm_1_10_64[vm & 0xf]; > +return valid_vm_1_10_64[vm] && (vm <= > RISCV_CPU(env_cpu(env))->cfg.satp_mode); > } > } > > -- > 2.37.2 > > LGTM. Reviewed-by: Atish Patra -- Regards, Atish

[PATCH v2] hw/riscv: virt: Remove the redundant ipi-id property

/ Signed-off-by: Atish Patra --- hw/riscv/virt.c | 2 -- include/hw/riscv/virt.h | 1 - 2 files changed, 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a5bc7353b412..0bc0964e42a8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -546,8 +546,6 @@ static void

[PATCH] hw/riscv: virt: Remove the redundant ipi-id property

The imsic DT binding has changed and no longer require an ipi-id. The latest IMSIC driver dynamically allocates ipi id if slow-ipi is not defined. Get rid of the unused dt property which may lead to confusion. Signed-off-by: Atish Patra --- hw/riscv/virt.c | 2 -- include/hw/riscv

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

On Wed, Mar 16, 2022 at 1:01 AM Anup Patel wrote: > > On Wed, Feb 16, 2022 at 9:18 PM Christoph Muellner > wrote: > > > > The RISC-V base cache management operation ISA extension has been > > ratified. This patch adds support for the defined instructions. > > > > The cmo.prefetch instructions

[PATCH v14 5/5] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30

[PATCH v14 2/5] target/riscv: Simplify counter predicate function

Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 110 - 1 file changed, 9 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 888ddfc4dd4b..2151e280a868 100644 --- a/target/riscv

[PATCH v14 3/5] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off

[PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c| 16 + target/riscv/pmu.c | 57 ++ target/riscv/pmu.h | 1 + 3 files changed, 74 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ff8c0df5cd47

[PATCH v10 3/3] target/riscv: Add vstimecmp support

vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra

[PATCH v14 0/5] Improve PMU support

/blob/master/riscv-sbi.adoc [2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/qemu/tree/riscv_pmu_v14 Atish Patra (5): target/riscv: Add sscofpmf extension support target/riscv: Simplify counter predicate function target/riscv: Add

[PATCH v14 1/5] target/riscv: Add sscofpmf extension support

. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 ++ target/riscv/csr.c | 166 +- target/riscv/machine.c

[PATCH v10 0/3] Implement Sstc extension

t. [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view [2] https://github.com/atishp04/linux/tree/sstc_v8 Atish Patra (3): hw/intc: Move mtimer/mtimecmp to aclint target/riscv: Add stimecmp support target/riscv: Add vstimecmp support hw/intc/riscv_aclint.c | 48 +++--- hw/timer/i

[PATCH v10 1/3] hw/intc: Move mtimer/mtimecmp to aclint

Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- hw/intc/riscv_aclint.c | 48 -- hw/timer/ibex_timer.c | 18 + include/hw/intc/riscv_aclint.h | 2 ++ include/hw/timer/ibex_timer.h | 2 ++ target/riscv/cpu.h | 2

[PATCH v10 2/3] target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 9 target/riscv/cpu.h

[PATCH v13 6/6] target/riscv: Remove additional priv version check for mcountinhibit

With .min_priv_version, additiona priv version check is uncessary for mcountinhibit read/write functions. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 8 1 file changed, 8 deletions(-) diff

[PATCH v13 4/6] hw/riscv: virt: Add PMU DT node to the device tree

Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c| 16 + target/riscv/pmu.c | 57 ++ target/riscv/pmu.h | 1 + 3 files changed, 74 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c1e8e0fcaf22

[PATCH v13 1/6] target/riscv: Add sscofpmf extension support

. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 166 ++- target/riscv

[PATCH v13 3/6] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off

[PATCH v13 0/6] Improve PMU support

j5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/qemu/tree/riscv_pmu_v13 Atish Patra (6): target/riscv: Add sscofpmf extension support target/riscv: Simplify counter predicate function target/riscv: Add few cache related PMU events hw/riscv: virt: Add PMU DT node to the device tree target/

[PATCH v13 5/6] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30

[PATCH v13 2/6] target/riscv: Simplify counter predicate function

Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 110 - 1 file changed, 9 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 886695221956..397803d07727 100644 --- a/target/riscv

Re: [PATCH v12 0/6] Improve PMU support

On Tue, Aug 2, 2022 at 4:33 PM Atish Patra wrote: > > The latest version of the SBI specification includes a Performance Monitoring > Unit(PMU) extension[1] which allows the supervisor to start/stop/configure > various PMU events. The Sscofpmf ('Ss' for Privileged arch and > S

[PATCH v9 0/3] Implement Sstc extension

Changes from v1->v2: 1. Rebased on the latest upstream commit. 2. Replaced PATCH 1 with another patch where mtimer/timecmp is moved from CPU to ACLINT. 3. Added ACLINT migration support. [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view [2] https://github.com/atishp04/lin

[PATCH v9 2/3] target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 9 target/riscv/cpu.h

[PATCH v9 1/3] hw/intc: Move mtimer/mtimecmp to aclint

Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- hw/intc/riscv_aclint.c | 41 -- hw/timer/ibex_timer.c | 18 ++- include/hw/intc/riscv_aclint.h | 2 ++ include/hw/timer/ibex_timer.h | 2 ++ target/riscv/cpu.h

[PATCH v9 3/3] target/riscv: Add vstimecmp support

vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra

[PATCH v8 3/3] target/riscv: Add vstimecmp support

vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Signed-off-by: Atish Patra --- target/riscv/cpu.h

[PATCH v8 2/3] target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 9 target/riscv/cpu.h | 5 ++ target/riscv

[PATCH v8 1/3] hw/intc: Move mtimer/mtimecmp to aclint

Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- hw/intc/riscv_aclint.c | 41 -- hw/timer/ibex_timer.c | 18 ++- include/hw/intc/riscv_aclint.h | 2 ++ include/hw/timer/ibex_timer.h | 2 ++ target/riscv/cpu.h

[PATCH v8 0/3] Implement Sstc extension

e mtimer/timecmp is moved from CPU to ACLINT. 3. Added ACLINT migration support. [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view [2] https://github.com/atishp04/linux/tree/sstc_v8 Atish Patra (3): hw/intc: Move mtimer/mtimecmp to aclint target/riscv: Add stimecmp su

[PATCH v7 3/3] target/riscv: Add vstimecmp support

vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Signed-off-by: Atish Patra --- target/riscv/cpu.h

[PATCH v7 2/3] target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 + target/riscv/cpu.h | 5 ++ target/riscv

[PATCH v7 0/3] Implement Sstc extension

CDR82MOBaSX/view [2] https://github.com/atishp04/linux/tree/sstc_v7 Atish Patra (3): hw/intc: Move mtimer/mtimecmp to aclint target/riscv: Add stimecmp support target/riscv: Add vstimecmp support hw/intc/riscv_aclint.c | 41 +--- hw/timer/ibex_timer.c | 18 ++-- include/hw

[PATCH v7 1/3] hw/intc: Move mtimer/mtimecmp to aclint

Signed-off-by: Atish Patra --- hw/intc/riscv_aclint.c | 41 -- hw/timer/ibex_timer.c | 18 ++- include/hw/intc/riscv_aclint.h | 2 ++ include/hw/timer/ibex_timer.h | 2 ++ target/riscv/cpu.h | 2 -- target/riscv

Re: [PATCH v5 0/1] target/riscv: Add Zihintpause support

On Sun, Jul 24, 2022 at 9:39 PM Alistair Francis wrote: > > On Mon, Jul 25, 2022 at 1:48 PM Dao Lu wrote: > > > > This patch adds RISC-V Zihintpause support. The extension is set to be > > enabled > > by default and opcode has been added to insn32.decode. > > > > Added trans_pause to exit the

[PATCH v12 5/6] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30

[PATCH v12 3/6] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off

[PATCH v12 4/6] hw/riscv: virt: Add PMU DT node to the device tree

Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c| 16 + target/riscv/pmu.c | 57 ++ target/riscv/pmu.h | 1 + 3 files changed, 74 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f2ce5663a4c7

[PATCH v12 6/6] target/riscv: Remove additional priv version check for mcountinhibit

With .min_priv_version, additiona priv version check is uncessary for mcountinhibit read/write functions. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Atish Patra --- target/riscv/csr.c | 8 1 file changed, 8 deletions(-) diff --git a/target/riscv/csr.c b

[PATCH v12 1/6] target/riscv: Add sscofpmf extension support

. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 166 ++- target/riscv/machine.c | 1 + target/riscv/pmu.c

[PATCH v12 2/6] target/riscv: Simplify counter predicate function

Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 110 - 1 file changed, 9 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9b45c49ab45f..6690b72ea0e7 100644 --- a/target/riscv

[PATCH v12 0/6] Improve PMU support

support. 3. A generic counter management framework. [1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/qemu/tree/riscv_pmu_v12 Atish Patra (6): target/riscv: Ad

[PATCH v11 5/6] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30 deletions(-) diff --git

[PATCH v11 1/6] target/riscv: Add sscofpmf extension support

. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 11 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 166 ++- target/riscv/machine.c | 1 + target/riscv/pmu.c

[PATCH v11 4/6] hw/riscv: virt: Add PMU DT node to the device tree

Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c| 28 +++ target/riscv/cpu.c | 1 + target/riscv/pmu.c | 57 ++ target/riscv/pmu.h | 1 + 4 files changed, 87 insertions(+) diff --git a/hw/riscv/virt.c b

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