et>
> ---
> linux-user/signal.c | 23 +++
> 1 file changed, 23 insertions(+)
With my limited knowledge of linux-user:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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entire region consumed via ctx->pc so that it's immediately available
> + in the disassembly dump. */
> +ctx->pc = pc_end;
> +return 1;
> }
> +#endif
>
> void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
> {
> @@ -1
On 2017-07-14 14:22, Richard Henderson wrote:
> On 07/14/2017 11:01 AM, Aurelien Jarno wrote:
> > > +if (parallel_cpus) {
> > > +int mask = 0;
> > > +#if !defined(CONFIG_ATOMIC64)
> > > +mask = -8;
> > > +#elif !defined(CONFIG_ATO
On 2017-07-14 14:23, Richard Henderson wrote:
> On 07/14/2017 11:08 AM, Aurelien Jarno wrote:
> > On 2017-07-11 17:18, Thomas Huth wrote:
> > > On 10.07.2017 22:45, Richard Henderson wrote:
> > > > Signed-off-by: Richard Henderson <r...@twiddle.net>
> &g
390x/mem_helper.c | 310
> +
> target/s390x/translate.c | 51
> target/s390x/insn-data.def | 13 ++
> 4 files changed, 380 insertions(+)
>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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gt;
> I think you should add such a check for even-numbered registers here.
Actually it should not be done here, but at translation time in
translate.c.
There are a few places where the register number is checked to be even
and later loaded into a temp. I guess that can be replaced by generators
instead?
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+++
> target/s390x/insn-data.def | 13 ++
> 4 files changed, 372 insertions(+)
>
Besides the check for even r1 and r3, this now looks good.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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ov = helper_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra);
> +#endif
Not a problem with the patch itself, but how complicated would it be to
make helper_atomic_cmpxchgl_be_mmu (just like the o version) available
also in user mode? That would make less #ifdef in the backends.
The remaining of the patch looks all good to me.
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rget/s390x/insn-data.def | 2 ++
> 4 files changed, 57 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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es changed, 23 insertions(+), 15 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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_decode_opc(DisasContext * ctx)
> return;
> case 0xf07d: /* fsrra FRn */
> CHECK_FPU_ENABLED
> +CHECK_FPSCR_PR_0
> +gen_helper_fsrra_FT(FREG(B11_8), cpu_env, FREG(B11_8));
> break;
> case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
> CHECK_FPU_ENABLED
Otherwise it looks fine.
--
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On 2017-07-06 16:21, Richard Henderson wrote:
> Both frchg and fschg require PR == 0, otherwise undefined_operation.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Aurelien Jar
On 2017-07-06 16:21, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
On 2017-07-06 16:21, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 64
> +++---
> 1 file changed, 29 insertions(+), 35 deletions(-)
Reviewed-by: Aurelien Jarno
On 2017-07-06 16:21, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 57
> +++---
> 1 file changed, 31 insertions(+), 26 deletions(-)
Reviewed-by: Aurelien Jarno
0 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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--
> 1 file changed, 13 insertions(+), 9 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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On 2017-07-06 16:21, Richard Henderson wrote:
> We do not need to emit N copies of raising an exception.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 14 --
> 1 file changed, 4 insertions(+), 10 deletions(-)
Rev
On 2017-07-06 16:21, Richard Henderson wrote:
> We do not need to emit N copies of raising an exception.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
---
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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+}
> +tcg_gen_mov_i32(REG(B11_8), addr);
> + tcg_temp_free(addr);
> +}
> return;
> case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
> CHECK_FPU_ENABLED
--
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file changed, 15 insertions(+), 11 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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On 2017-07-06 16:20, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno G
On 2017-07-06 16:20, Richard Henderson wrote:
> Compute which register bank to use once at the start of translation.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Rev
On 2017-07-06 16:20, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/translate.c | 26 +-
> 1 file changed, 13 insertions(+), 13 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net
arget/sh4/translate.c | 125
> -
> 1 file changed, 52 insertions(+), 73 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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0 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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sh4/cpu.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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slate.c | 4 ++--
> 2 files changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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On 2017-07-06 16:20, Richard Henderson wrote:
> Don't leave an unused bit after DELAY_SLOT_MASK.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/sh4/cpu.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Aurelien Jar
break;
> }
> -if (tb->cflags & CF_LAST_IO)
> +if (tb->cflags & CF_LAST_IO) {
> gen_io_end();
> +}
> if (cs->singlestep_enabled) {
> gen_save_cpu_state(, true);
> gen_helper_debug(cpu_env);
Besides the minor nitpicks above:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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ions(+), 18 deletions(-)
I haven't reviewed this patch in details, but note that it breaks
booting a system under qemu-system.
--
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break;
> }
> -if (tb->cflags & CF_LAST_IO)
> +if (tb->cflags & CF_LAST_IO) {
> gen_io_end();
> +}
> if (cs->singlestep_enabled) {
> gen_save_cpu_state(, true);
> gen_helper_debug(cpu_env);
Besides the minor nitpicks above:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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t:
http://lists.nongnu.org/archive/html/qemu-devel/2017-07/msg00095.html
I'll try to review it over the next days, but unfortunately I'll have
little time before Monday.
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how m68k specific are those trigonometric
functions. If we can have a way to implement them as generic
trigonometric functions reusable by other targets, I am all for it. If
not that code would probably be better in target/m68k.
Aurelien
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the check, and at the same time use a TCG instruction instead of
a helper to clear one bit.
LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <br...@clisp.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h| 2 --
target/sh4/op_helper.c |
In case of unordered compare, the fcmp instructions should either
trigger and invalid exception (if enabled) or set T=0. The existing code
left it unchanged.
LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <br...@clisp.org>
Signed-off-by: Aurelien Jarno
Since that the T bit of the SR register is mapped using a TGC global,
it's better to return the value through TCG than writing it directly. It
allows to declare the helpers with the flag TCG_CALL_NO_WG.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h
bug. It also improves a bit the fneg
and fcmp instructions.
Aurelien Jarno (5):
target/sh4: do not check for PR bit for fabs instruction
target/sh4: fix FPU unorderered compare
target/sh4: fix FPSCR cause vs flag inversion
target/sh4: do not use a helper to implement fneg
target/sh4
The floating-point status/control register contains cause and flag
bits. The cause bits are set to 0 before executing the instruction,
while the flag bits hold the status of the exception generated after
the field was last cleared.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
There is no need to use a helper to flip one bit, just use a TCG xor
instruction instead.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h| 1 -
target/sh4/op_helper.c | 5 -
target/sh4/translate.c | 5 ++---
3 files changed, 2 insertions(+), 9 del
This patchset should fix the bug #1701821 reported by Bruno Haible,
which makes the gnulib testsuite to fail for single precision libm
tests.
Aurelien Jarno (2):
target/sh4: do not check for PR bit for fabs instruction
target/sh4: do not use a helper to implement fneg
target/sh4/helper.h
the check, and at the same time use a TCG instruction instead of
a helper to clear one bit.
LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <br...@clisp.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h| 2 --
target/sh4/op_helper.c |
There is no need to use a helper to flip one bit, just use a TCG xor
instruction instead.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h| 1 -
target/sh4/op_helper.c | 5 -
target/sh4/translate.c | 5 ++---
3 files changed, 2 insertions(+), 9 del
len <= rot
>
> Reported-by: David Hildenbrand <da...@redhat.com>
> Suggested-by: Aurelien Jarno <aurel...@aurel32.net>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/translate.c | 4 ++--
> 1 file changed, 2 insertion
t to me. The well-formedness checking is part of
ETF3_ENH facility, for both convert unicode instructions that are part
of the Z architecture (CU12 and CU21) and for the ones added by the ETF3
facility (CU14 and CU24).
The rest of the patch now looks fine.
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is rounded
(floatx80_rounding_precision) ?
Otherwise looks all fine to me.
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el would trigger weird
> BUG_ONs very early while starting up, which basically gave not really
> many hints of what was actually going wrong.
>
> target/s390x/translate.c | 6 --
> 1 file changed, 6 deletions(-)
But the patch is also correct.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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112, <
> oi=32, retaddr=140737129226144)
> at /home/vini/projs/emuladores/qemu-routers/softmmu_template.h:141
> #3 0x7fffea982108 in code_gen_buffer ()
... while helper_le_ldul_mmu and io_readl are read functions. The
assembly code and the backtrace do not
>
> I think we can get to z990 fairly quickly after this.
> Ignoring HFP, the ones I see missing are DAT-ENH, MSA.
Thanks for this work. For the record I have started working on HFP
sometimes ago. I'll try to finish that and submit patches in the next
weeks.
--
Aurelien Jarno
S390_FEAT_ETF3_ENH,
> S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
> S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
> S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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et/s390x/helper.h | 1 +
> target/s390x/insn-data.def | 2 ++
> target/s390x/mem_helper.c | 20 +---
> target/s390x/translate.c | 9 +
> 4 files changed, 25 insertions(+), 7 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurel
o->in2);
> +gen_helper_srst(o->in1, cpu_env, o->in1, o->in2);
> set_cc_static(s);
> return_low128(o->in2);
> return NO_EXIT;
The cleanup is a good step, but I guess that should also be the moment
to improve the address masking/wrapping (see comment on next patch).
Anyway:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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aurel...@aurel32.net http://www.aurel32.net
.net>
> ---
> target/s390x/cpu.h | 24 +---
> target/s390x/translate.c | 16
> 2 files changed, 17 insertions(+), 23 deletions(-)
>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
4_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t
> s2)
> {
Overall that looks fine, but I think we should get the wrapping (almost)
correct, now that we have the get_address / set_address functions. As
all registers are saved on input, I guess the registers can be directly
written back in the helper using set_address. It should handle most of
the cases, except wrapping at the end of the address space, but anyway
I don't think it's handled somewhere.
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return 1;
> +}
> +cpu_stw_data_ra(env, addr, c, ra);
> +*olen = 2;
> +} else {
> +/* two word character */
> +if (ilen < 4) {
> +return 1;
> +}
> +d1 = 0xbc00 | extract32(c, 0, 10);
> +d0 = 0xb800 | extract32(c, 10, 6);
This should be 0xdc00 and 0xd800;
Otherwise the patch looks fine to me.
--
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1 file changed, 1 insertion(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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aurel...@aurel32.net http://www.aurel32.net
get/s390x/translate.c | 5 +++--
> 2 files changed, 13 insertions(+), 3 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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On 2017-06-19 17:03, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/insn-data.def | 9 +
> target/s390x/translate.c | 5 -
> 2 files changed, 13 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno
sertions(+), 3 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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On 2017-06-19 17:03, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/insn-data.def | 3 +++
> target/s390x/translate.c | 1 +
> 2 files changed, 4 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.
On 2017-06-19 17:03, Richard Henderson wrote:
> This facility bit includes load-on-condition-2 and
> load-and-zero-rightmost-byte.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/cpu_models.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewe
is considered a separate instruction in the PoO,
called LOAD LOGICAL AND ZERO RIGHTMOST BYTE.
That said:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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pu_models.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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com>
> Signed-off-by: David Hildenbrand <da...@redhat.com>
> Message-Id: <20170614133819.18480-2-da...@redhat.com>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/cpu.h | 2 +-
> target/s390x/translate.c | 2 +-
> 2 files changed
--
> 1 file changed, 29 insertions(+), 30 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
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Currently the malta board is loading the initrd just after the kernel.
This doesn't work for kaslr enabled kernels, as the initrd ends-up being
overwritten.
Move the initrd at the end of the low memory, that should leave a
sufficient gap for kaslr.
Signed-off-by: Aurelien Jarno <aurel...@aure
/mips/translate.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Acked-by: Aurelien Jarno <aurel...@aurel32.net>
--
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aurel...@aurel32.net http://www.aurel32.net
On 2017-06-15 14:10, Richard Henderson wrote:
> On 06/15/2017 01:49 PM, Aurelien Jarno wrote:
> > > +S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
> >
> > Theoretically the floating-point-support-enhancement facilities include
> > the DFP rounding facility. Gi
On 2017-06-14 12:48, Richard Henderson wrote:
> From: Paolo Bonzini <pbonz...@redhat.com>
>
> Exit to cpu loop so we reevaluate cpu_mips_hw_interrupts.
>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> Cc: Yongbok Kim <yongbok@imgtec.com>
> Signed-off-
dc.features = cpu->model->features;
> }
>
>
> ...
>
> if (s->features && !test_bit(insn->fac, s->features)) {
> gen_program_exception(s, PGM_OPERATION);
> return EXIT_NORETURN;
> }
I don't know that part of the code enough to tell if
nt facilities include
the DFP rounding facility. Given We don't implement the DFP facility I
guess this can be ignored.
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aurel...@aurel32.net http://www.aurel32.net
On 2017-06-15 13:28, David Hildenbrand wrote:
> On 15.06.2017 09:01, Aurelien Jarno wrote:
> > On 2017-06-14 22:53, Richard Henderson wrote:
> >> Signed-off-by: Richard Henderson <r...@twiddle.net>
> >> ---
> >> target/s390x/translate.c | 8 +
ludes for
example FPE, LPP, MIE, LAT, I_SIM and more.
We could maybe provide a way to override the check, or only enable
enforcement for fully implemented facilities. Failing to do so means we
just introduce a regression from the user point of view (many binaries
will stop working) and also that
Instead of unconditionally exiting to the exec loop for indirect jumps
or cross-page direct jumps, use the lookup_and_goto_ptr helper to jump
to the target if it is valid.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 4 ++--
1 file changed, 2 insertions
On 2017-06-05 17:29, Rob Landley wrote:
> On 05/18/2017 06:01 PM, Aurelien Jarno wrote:
> > On 2017-05-18 17:37, Rob Landley wrote:
> >> On 05/18/2017 02:00 PM, Aurelien Jarno wrote:
> >>> On 2017-05-18 11:08, Rob Landley wrote:
> >>>> Serial inpu
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 24
target/s390x/translate.c | 6 ++
4 files changed, 33 insertions(+)
diff --git a/target/s390x/help
The CDSG instruction requires a 16-byte alignement, as expressed in
the MO_ALIGN_16 passed to helper_atomic_cmpxchgo_be_mmu. In the non
parallel case, use check_alignment to enforce this.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/mem_helper.c | 2 ++
1 file chan
to be applied over the pull request
as it makes uses of the check_alignment function.
Finally the latest patch fixes a lack of alignement check in CDSG,
discovered as I used it as an example about how to properly handle hosts
without atomic128 support.
Aurelien Jarno (3):
target/s390x: implement LOAD PAIR
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 27 +++
target/s390x/translate.c | 7 +++
4 files changed, 37 insertions(+)
diff --git a/target
conflict to solve in helper.h. Properly implementing
the !CONFIG_ATOMIC128 case requires to check the alignment and it's
better done with the check_alignment function introduced later in the
series.
I'll send new patches for those two instructions in the next hours.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Hildenbrand had objections to that; I expect
> that we can address that in the next patch set.
Fair enough. I think I'll put this one in standby and look at that again
when QEMU can emulate a higher model like a z990.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
au
ected to be executed on hot paths, I
> think moving it into a helper is the right thing to do.
This is not only about performance, but also avoiding code that is
spread in many files. Well theoretically increasing the number of
entries in the helper hash table has a performance impact, but i don't
think it is measurable.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2017-06-02 13:30, David Hildenbrand wrote:
> On 02.06.2017 10:09, Thomas Huth wrote:
> > On 01.06.2017 21:17, Aurelien Jarno wrote:
> >> On 2017-06-01 11:04, David Hildenbrand wrote:
> >>> On 01.06.2017 10:38, David Hildenbrand wrote:
> >>>&
On 2017-06-01 21:56, David Hildenbrand wrote:
> On 01.06.2017 21:17, Aurelien Jarno wrote:
> > On 2017-06-01 10:38, David Hildenbrand wrote:
> >> On 01.06.2017 00:01, Aurelien Jarno wrote:
> >>> At the same time fix the TCG version of get_max_cpu_model to return the
&
chance to object...
>
> Yeah, Alpha, MIPS and SH are those that support PCI. Adding Richard and
> Aurelien, do your platforms support MSI on real hardware but not in QEMU?
SH clearly doesn't support MSI.
The oldest MIPS board also do not support MSI, but I guess the Boston
board might sup
);
> +uint64_t cpuid = s390_cpuid_from_cpu_model(cpu->model);
> +
> +if (addr & 0x7) {
> +program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
> +return;
> +}
> +
> +/* basic mode, write the cpu address into the first 4 bit of the ID */
> +cpuid |= ((uint64_t)env->cpu_num & 0xf) << 54;
> +cpu_stq_data(env, addr, cpuid);
> +}
> +#endif
I don't really see the point of using an helper instead of just updating
the existing code. From what I understand the cpuid does not change at
runtime, so the s390_cpuid_from_cpu_model function can also be called
from translate.c.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2017-06-01 11:04, David Hildenbrand wrote:
> On 01.06.2017 10:38, David Hildenbrand wrote:
> > On 01.06.2017 00:01, Aurelien Jarno wrote:
> >> At the same time fix the TCG version of get_max_cpu_model to return the
> >> maximum model like on KVM. Remove the ETF2 and l
On 2017-06-01 10:38, David Hildenbrand wrote:
> On 01.06.2017 00:01, Aurelien Jarno wrote:
> > At the same time fix the TCG version of get_max_cpu_model to return the
> > maximum model like on KVM. Remove the ETF2 and long-displacement
>
> I don't understand the part
&
adj_len_to_page doesn't return the correct result when the address
is already page aligned and the length is bigger than a page. Fix that.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/mem_helper.c | 2 +-
1
And at the same time make IPTE SMP aware.
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 2 +-
target/s390x/mem_helper.c | 21 +
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 12
target/s390x/translate.c | 8
4 files changed, 2
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/insn-data.def | 3 +++
target/s390x/translate.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-da
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 12
target/s390x/translate.c | 6 ++
4 files changed, 21 insertions(+)
diff --git a/target/s390x/helper.h b/
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4
target/s390x/mem_helper.c | 31 +++
target/s390x/translate.c | 8 +
These functions differ from COMPARE by generating an exception for a
QNaN input. Use the non quiet version of floatXX_compare.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/fpu_helper.c | 27 +++
target/s390x/helper.h | 3 +++
target
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 13 +
target/s390x/translate.c | 7 +++
4 files changed, 23 insertions(+)
diff --git a/target/s390x/helper.h b/
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 5 +
target/s390x/mem_helper.c | 37 +
target/s390x/translate.c | 8
t;r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/mem_helper.c | 54 ---
target/s390x/translate.c | 20 +-
2 files changed, 52 insertions(+), 22 deletions(-)
diff --git a/target/s390x/mem_helpe
As MVCL and MVCLE only differ by their operands, use a common
do_mvcl helper. Optimize it calling fast_memmove and fast_memset.
Correctly write back addresses. Check that r1 and r2/r3 registers
are even.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno
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