ill be good for bisection,
> and it certainly does save storage space.
>
> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target-cris/translate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 dele
On 2015-09-22 12:26, Thomas Huth wrote:
> On 13/09/15 23:03, Aurelien Jarno wrote:
> > The xscmpodp and xscmpudp instructions only have the AX, BX bits in
> > there encoding, the lowest bit (usually TX) is marked as an invalid
> > bit. We therefore can't decode them with GEN_X
.net>
> ---
> target-sparc/translate.c | 21 ++---
> 1 file changed, 10 insertions(+), 11 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ns(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ns(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
son <r...@twiddle.net>
> ---
> tcg/tcg-op.h | 52
> tcg/tcg-opc.h | 4 ++--
> tcg/tcg.c | 13 +++--
> tcg/tcg.h | 6 ++
> 4 files changed, 59 insertions(+), 16 deletions(-)
Reviewed-by: Aurelien Jar
| 3 ++-
> 3 files changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ns(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ns(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
> target-tricore/translate.c| 2 ++
> target-unicore32/translate.c | 5 +
> target-xtensa/translate.c | 5 +
> 20 files changed, 41 insertions(+), 81 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
tci.c | 9 -
> 23 files changed, 28 insertions(+), 37 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
e.c | 3 ++-
> target-tricore/translate.c| 3 +--
> target-unicore32/translate.c | 4 ++--
> target-xtensa/translate.c | 4 ++--
> 19 files changed, 41 insertions(+), 39 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and
tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly
pass oi to the tcg_out_tlb_load function and compute mem_index and
s_bits there.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Au
son <r...@twiddle.net>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mips/tcg-target.c | 26 +++---
1 file changed, 15 insertions(+), 11 delet
Somehow the tcg_out_addsub2 function ended-up in the middle of the
qemu_ld/st related functions. Move it with other arithmetics related
functions.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mips/tcg-t
to 81dfaf1a8f7f95259801da9732472f879023ef77:
tcg/mips: pass oi to tcg_out_tlb_load (2015-09-19 11:53:15 +0200)
TCG MIPS queue
- Fixes for 64-bit guests
- Small cleanups
Aurelien
I have these patches for quite some time in one of my local branch in
the hope I would have time to do further changes. Given that I am going
to send a pull request for the 64-bit qemu_ld issue, I think it's a good
opportunity to also include them.
Aurelien Jarno (2):
tcg/mips: move
omparator
> +lw a0,9160(a0) load addend
> -bne v0,a1,0x836d838
> +bne at,a1,0x836d838
> addu v0,a0,v0
> lw t0,0(v0)
>
> Suggested-by: Richard Henderson <r...@twiddle.net>
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Cc:
Somehow the tcg_out_addsub2 function ended-up in the middle of the
qemu_ld/st related functions. Move it with other arithmetics related
functions.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mips/tcg-target.c | 98 +--
Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and
tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly
pass oi to the tcg_out_tlb_load function and compute mem_index and
s_bits there.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mi
lex Smith <alex.sm...@imgtec.com>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> Cc: Leon Alrae <leon.al...@imgtec.com>
> ---
> Changes in v2:
> - Fix build breakage for user builds.
> - Correct existing code to follow QEMU coding style.
> ---
> target-mi
y recent, that's why we
had it opened coded up to now.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
troduced a serious performance regression in user mode:
https://lists.gnu.org/archive/html/qemu-devel/2015-08/msg01620.html
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
TCGv t0 = tcg_temp_new();
> gen_load_gpr(t0, rs);
> tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
do {
> lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd001u);
> -idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
> + idx = lfsr % nb_rand_tlb + env->CP0_Wired;
> } while (idx == prev_idx);
> prev_idx = i
the lowest bit as invalid.
Cc: Tom Musta <tommu...@gmail.com>
Cc: Alexander Graf <ag...@suse.de>
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-ppc/translate.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff
This patchset fixes some vector instructions which are incorrectly
decoded or implemented. The first patch is needed to run recent version
of openssl, as it enabled POWER8 instrutctions when it detects such a
CPU.
Aurelien Jarno (2):
target-ppc: fix vcipher, vcipherlast, vncipherlast
From: Guenter Roeck <li...@roeck-us.net>
If host and target endianness does not match, loding an initramfs does not work.
Fix by writing boot parameters with appropriate endianness conversion.
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Signed-off-by: Aurelien Jarno <aurel
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-sh4/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index be0cb32..50043cf 100644
nce the high bits
set due to a value greater than 0x80 in the first sub-expression are
masked off by the second.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-sh4/translate.c | 17 +
1 file chan
in an temporary variable.
This fixes openssl when emulating a POWER8 CPU.
Cc: Tom Musta <tommu...@gmail.com>
Cc: Alexander Graf <ag...@suse.de>
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-ppc/int_helper.c | 19 ++-
1 file chan
net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-sh4/translate.c | 48 ++--
1 file changed, 22 insertions(+), 26 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index ca6ef5a..c8dd3a7 100644
---
Most floating point helpers can trigger an exception, but don't change
the globals. Mark these helpers as TCG_CALL_NO_WG.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-sh4/helper.h | 34 +-
issue
Aurelien Jarno (5):
target-sh4: add flags markups for FP helpers
target-sh4: use deposit in swap.b instruction
target-sh4: improve cmp/str instruction
target-sh4: improve shld instruction
target-sh4
net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-sh4/translate.c | 53 +-
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c8dd3a7..724c0e7 100644
---
On 2015-09-10 19:48, Aurelien Jarno wrote:
> On 2015-09-01 22:51, Richard Henderson wrote:
> > I've been looking at this problem off and on for the last week or so,
> > prompted by the sparc performance work. Although I havn't been able
> > to get a proper sparc64 guest i
translate.c.
Cc: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-mips/translate.c | 624 ++--
1 file changed, 19 insertions(+), 605 deletions(-)
diff --git a/target-mips/translate.c b/target-mips
, it's
probably time to apply it.
Aurelien Jarno (2):
target-mips: get rid of MIPS_DEBUG
target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
target-mips/translate.c | 663 ++--
1 file changed, 19 insertions(+), 644 deletions(-)
--
2.1.4
MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.
Cc: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-mips/tran
for (i = 0; i < nb_oargs + nb_iargs; i++) {
> +init_temp_info(args[i]);
> +}
> }
>
> /* Do copy propagation */
>
>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
have to take care
that the informations to store do not take too much space compared to
the actual translated code.
I'll give a look and a test asap.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
is modelled might triggered plenty of costly retranslation. This
happens for example on SH4, and to a lesser extent on MIPS.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
a good optimization target seems to be the tcg_optimize
function. If I zoom I see it spends most of the time in
reset_all_temps.
Any suggestions how to improve it?
Try this patch:
http://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg02042.html
Aurelien
--
Aurelien Jarno
for a compilation which should be CPU bounded. Maybe try
to add the -pipe argument to g++.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-17 12:38, Richard Henderson wrote:
From: Aurelien Jarno aurel...@aurel32.net
Now that we have real size changing ops, we don't need to mark high
bits of the destination as garbage. The goal of the optimizer is to
predict the value of the temps (and not of the registers) and do
definition from the global
namespace.
Cc: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
target-sh4/cpu.h | 2 --
1 file changed, 2 deletions(-)
Acked-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG
, as that is
architecture specific code.
This removes another architecture specific definition from the global
namespace.
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: Leon Alrae leon.al...@imgtec.com
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
hw/mips/mips_fulong2e.c
On 2015-08-13 23:03, Mark Cave-Ayland wrote:
On 01/08/15 19:33, Aurelien Jarno wrote:
On 2015-08-01 17:54, Mark Cave-Ayland wrote:
The existing code incorrectly changes the dma_active flag when a non-block
transfer has completed leading to a hang on newer versions of Linux
because
(initrd_size);
}
if (kernel_cmdline) {
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Good catch. I have added it to my sh4-next queue:
http://git.aurel32.net/?p=qemu.git;a=shortlog;h=refs/heads/sh4-next
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32
be to switch to softmmu for the user mode. I know
there are people working on that, but given that it might take time, it
could be a simple temporary solution.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
. Pavel, do you have an idea for that?
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-09 09:11, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
On 2015-08-07 19:03, Alvise Rigo wrote:
Introduce the new --enable-tcg-ldst-excl configure option to enable the
LL/SC operations only for those backends that support them.
Suggested-by: Jani
On 2015-08-09 10:51, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
On 2015-08-09 09:11, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
On 2015-08-07 19:03, Alvise Rigo wrote:
Introduce the new --enable-tcg-ldst-excl configure option to enable
the backend maintainers. I can try to provide
the corresponding patches for mips and ia64.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
for all backends. Of course we might still want a wrapper so that the
tcg_gen_* functions transparently call the right helper.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-05 12:08, Peter Maydell wrote:
On 28 July 2015 at 19:03, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-07-28 19:22, Stefan Weil wrote:
are there QEMU developers at the Debian Conference 2015 in Heidelberg
(Germany)
(http://debconf15.debconf.org/)? I'll be there for one
when this option is enabled?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
);
}
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
for the other architectures.
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
+tlb_debug(tlb_set_page: vaddr= TARGET_FMT_lx paddr=0x TARGET_FMT_plx
+ prot=%x idx=%d\n,
+ vaddr, paddr, prot, mmu_idx);
address = vaddr;
if (!memory_region_is_ram(section-mr)
!memory_region_is_romd(section-mr)) {
--
2.5.0
--
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
:
+tb_enable_perfmap();
+break;
case QEMU_OPTION_s:
add_device_config(DEV_GDB, tcp:: DEFAULT_GDBSTUB_PORT);
break;
--
2.5.0
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http
by the new value. If the invalidated TB is not the
last one, it is just left in the generated code.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
);
qemu_log(\n);
--
2.5.0
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
, so this triggers a
warning. That's also a reason I suggested to use a fixed date format.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
-system-i386 -d cpu,exec,dfilter=0x8000-0x9000
Otherwise:
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
- %p [ TARGET_FMT_lx ]\n,
+ tb-tc_ptr, tb-pc, n, tb_next-tc_ptr, tb_next-pc);
/* patch the native jump address */
tb_set_jmp_target(tb, n, (uintptr_t)tb_next-tc_ptr);
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno
Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
);
-if ((qemu_loglevel mask) qemu_logfile) {
-vfprintf(qemu_logfile, fmt, ap);
-}
-va_end(ap);
-}
-
/* enable or disable low levels log */
void do_qemu_set_log(int log_flags, bool use_own_buffers)
{
Good idea.
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
On 2015-08-04 13:55, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
On 2015-08-04 08:39, Alex Bennée wrote:
Paolo Bonzini pbonz...@redhat.com writes:
On 03/08/2015 11:14, Alex Bennée wrote:
This allows the perf tool to map samples to each individual translation
On 2015-08-03 14:41, Richard Henderson wrote:
On 08/03/2015 02:31 PM, Aurelien Jarno wrote:
On 2015-08-03 12:35, Richard Henderson wrote:
if (msb != 31) {
-tcg_gen_andi_tl(t0, t0, (1 (msb + 1)) - 1);
+tcg_gen_andi_tl(t0, t0, (1U (msb + 1)) - 1
...@imgtec.com
---
target-mips/translate.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
insertions(+), 20 deletions(-)
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
/html/qemu-devel/2015-07/msg02581.html
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
, lsb, msb - lsb + 1);
break;
Despite the above comments:
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Should we try to get this one into 2.4, if not already too late?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http
On 2015-08-03 10:31, Artyom Tarasenko wrote:
Hi Aurelien,
On Fri, Jul 31, 2015 at 5:43 PM, Aurelien Jarno aurel...@aurel32.net wrote:
It uses a lot of integer functions
based on CPU flags, so most of the time is spent computing them in
helper_compute_psr.
I wonder if this can
.
Aurelien Jarno (4):
tcg/mips: fix TLB loading for BE host with 32-bit guests
tcg/mips: Mask TCGMemOp appropriately for indexing
tcg/s390x: Mask TCGMemOp appropriately for indexing
tcg/mips: fix add2
tcg/mips/tcg-target.c | 11
For 32-bit guest, we load a 32-bit address from the TLB, so there is no
need to compensate for the low or high part. This fixes 32-bit guests on
big-endian hosts.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg
to boot on a
MIPS host.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/mips/tcg-target.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 064db46..e97980d
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG MIPS backend.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/mips/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG S390 backend.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/s390/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2
On 2015-08-01 12:21, Mark Cave-Ayland wrote:
On 28/07/15 19:02, Aurelien Jarno wrote:
Thanks for the heads-up. I have a fairly comprehensive suite of various
OS test images I use for OpenBIOS testing and evidently not a single one
of them issues a TRIM command as I don't see any
On 2015-08-01 12:10, Mark Cave-Ayland wrote:
On 29/07/15 20:27, Aurelien Jarno wrote:
Commit bd4214fc dropped TRIM support by mistake. Given it is still
advertised to the host when using a drive with discard=on, this cause
the IDE bus to hang when the host issues a TRIM command
}
[ 307.271251] ata2.00: configured for MWDMA2
[ 307.271824] ata2: EH complete
The CD-ROM is fully functional though.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
to boot on a
MIPS host.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/mips/tcg-target.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 064db46..e97980d 100644
--- a/tcg/mips/tcg-target.c
On 2015-07-31 17:31, Artyom Tarasenko wrote:
On Thu, Jul 30, 2015 at 5:50 PM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-07-30 10:55, Aurelien Jarno wrote:
On 2015-07-30 10:16, Dennis Luehring wrote:
Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
On 2015-07-30 05:52, Dennis
-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
For 32-bit guest, we load a 32-bit address from the TLB, so there is no
need to compensate for the low or high part. This fixes 32-bit guests on
big-endian hosts.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/mips/tcg-target.c | 4 +++-
1 file
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG S390 backend.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/s390/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
These are small fixes for MIPS and S390 hosts, found by testing various
guests on these hosts.
Aurelien Jarno (3):
tcg/mips: fix TLB loading for BE host with 32-bit guests
tcg/mips: Mask TCGMemOp appropriately for indexing
tcg/s390x: Mask TCGMemOp appropriately for indexing
tcg/mips/tcg
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG MIPS backend.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/mips/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
patch.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
I don't have a fulong2e image, so this is compile tested only...
I have just tested, it still boots fine with the change.
hw/pci-host/bonito.c | 16
1 file changed, 16 insertions(+)
Acked-by: Aurelien Jarno
On 2015-07-29 21:42, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
On 2015-07-29 17:12, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
Now that copies and constants are tracked separately, we can allow
constant to have copies, deferring
On 2015-07-30 05:52, Dennis Luehring wrote:
Am 29.07.2015 um 17:01 schrieb Aurelien Jarno:
The point is that emulation has a cost, and it's quite difficult to
to lower it and thus improve the emulation speed.
so its just not strange for you to see an 1/100...200 of the native x64
speed
it's actually the reverse. The fact that
aarch64 does unaligned access means they have to go through the slow
path (I have posted a patch to improve that). On sparc given that all
access are aligned means there are more chances to go through the fast
path.
--
Aurelien Jarno
On 2015-07-30 10:55, Aurelien Jarno wrote:
On 2015-07-30 10:16, Dennis Luehring wrote:
Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
On 2015-07-30 05:52, Dennis Luehring wrote:
Am 29.07.2015 um 17:01 schrieb Aurelien Jarno:
The point is that emulation has a cost, and it's quite
On 2015-07-30 11:35, Artyom Tarasenko wrote:
On Thu, Jul 30, 2015 at 10:55 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-07-30 10:16, Dennis Luehring wrote:
Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
On 2015-07-30 05:52, Dennis Luehring wrote:
Am 29.07.2015 um 17:01 schrieb
On 2015-07-30 10:16, Dennis Luehring wrote:
Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
On 2015-07-30 05:52, Dennis Luehring wrote:
Am 29.07.2015 um 17:01 schrieb Aurelien Jarno:
The point is that emulation has a cost, and it's quite difficult to
to lower it and thus improve
On 2015-07-29 17:10, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
Use two bools to track constants and copies instead of an enum.
More of an explanation would be useful as to why, otherwise it seems to
me we are just increasing the size of the structure (assuming
On 2015-07-29 17:12, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
Now that copies and constants are tracked separately, we can allow
constant to have copies, deferring the choice to use a register or a
constant to the register allocation pass. This prevent this kind
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