On 2015-07-27 12:56, Aurelien Jarno wrote:
Now that we have real size changing ops, we don't need to mark high
bits of the destination as garbage. The goal of the optimizer is to
predict the value of the temps (and not of the registers) and do
simplifications when possible. The problem
.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-29 17:01, Alex Bennée wrote:
Aurelien Jarno aurel...@aurel32.net writes:
Add two accessor functions temp_is_const and temp_is_copy, to make the
code more readable and make code change easier.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel
Cave-Ayland mark.cave-ayl...@ilande.co.uk
Cc: John Snow js...@redhat.com
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
hw/ide/macio.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index a55a479..66ac2ba 100644
--- a/hw/ide
able to see, the sparc (but also mips and sh4) targets would benefit
from MMU emulation improvements. But that's not easy to do either.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
the clock speed of the cpu/fpu without killing
other timemings - or switch to a different cpu?
(because i do not need real speed behavior for my testing)
The easiest (but not the cheapest) is probably to upgrade your host
machine to something faster.
Aurelien
--
Aurelien Jarno
On 2015-07-28 09:52, Mark Cave-Ayland wrote:
On 27/07/15 23:00, Aurelien Jarno wrote:
On 2015-05-22 15:59, John Snow wrote:
From: Mark Cave-Ayland mark.cave-ayl...@ilande.co.uk
Similarly switch the macio IDE routines over to use the new function and
tidy-up the remaining code
, just contact me a few days before you arrive.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
them as they are fixing bugs triggered by patches from these
series.
Changes v1-v2
- Added patches 1 2
- patch 3: use bitmap_zero instead of memset
for the call op, only reset temps that are in use
- patch 4: do not use a bool to detect copies
Aurelien Jarno (12):
tcg: correctly
They behave the same as ext32s_i64 and ext32u_i64 from the constant
folding and zero propagation point of view, except that they can't
be replaced by a mov, so we don't compute the affected value.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg
The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32,
and the name in the README doesn't match the name offered to the
frontends.
Always use the long name to make it clear it is a size changing op.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno
...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index cd0e793..425c14b 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -50,6 +50,7
.
Cc: Richard Henderson r...@twiddle.net
Reported-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 7e088b1..9a2508b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
0x7ffbebcae426
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index e69ab05..2d3c72b 100644
--- a/tcg/optimize.c
+++ b/tcg
Add two accessor functions temp_is_const and temp_is_copy, to make the
code more readable and make code change easier.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 131 ++---
1
On 2015-07-27 13:26, Paolo Bonzini wrote:
On 27/07/2015 12:56, Aurelien Jarno wrote:
temps[dst].next_copy = temps[src].next_copy;
temps[dst].prev_copy = src;
temps[temps[dst].next_copy].prev_copy = dst;
temps[src].next_copy = dst;
Note
are not counted as garbage, but that a size
changing op is replaced by a move.
This patch is basically a revert of 24666baf, including the changes that
have been made since then.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 41
The tcg_gen_trunc_shr_i64_i32 function takes a 64-bit argument and
returns a 32-bit value. Directly call tcg_gen_op3 with the correct
types instead of calling tcg_gen_op3i_i32 and abusing the TCG types.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/README | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tcg/README b/tcg/README
index 61b3899..a22f251 100644
--- a/tcg/README
+++ b/tcg/README
@@ -466,13
-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 42 ++
1 file changed, 14 insertions(+), 28 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 719fee2..e69ab05 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -35,14 +35,8
When a constant has to be loaded in a mov op, we fail to set
mem_coherent = 0. This patch fixes that.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 9a2508b
Cc: Claudio Fontana claudio.font...@huawei.com
Cc: Claudio Fontana claudio.font...@gmail.com
Cc: Richard Henderson r...@twiddle.net
Cc: Stefan Weil s...@weilnetz.de
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/aarch64/tcg-target.c | 4
tcg/i386/tcg-target.c| 5 +
tcg
complete
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-27 10:21, Paolo Bonzini wrote:
On 24/07/2015 18:30, Aurelien Jarno wrote:
The tcg_temp_info structure uses 24 bytes per temp. Now that we emulate
vector registers on most guests, it's not uncommon to have more than 100
used temps. This means we have initialize more than 2kB
On 2015-07-27 10:25, Paolo Bonzini wrote:
On 24/07/2015 18:30, Aurelien Jarno wrote:
Use two bools to track constants and copies instead of an enum.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 30
*/
if ((s-regs[SONIC_RCR] SONIC_RCR_PRO) (buf[0] 1) == 0) {
return 0;
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-25 16:12, Richard Henderson wrote:
On 07/25/2015 03:51 PM, Aurelien Jarno wrote:
On 2015-07-25 15:06, Richard Henderson wrote:
On 07/24/2015 04:34 PM, Aurelien Jarno wrote:
ots-val_type = TEMP_VAL_CONST;
ots-val = ts-val;
+if (IS_DEAD_ARG(1
. Looking at other code, it seems they call
memory_region_set_readonly() instead of providing an accepts function.
Maybe readonly should be the default for a rom device?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
= vmstate_dp8393x;
dc-props = dp8393x_properties;
+/* Reason: dma_mr property can't be set */
+dc-cannot_instantiate_with_device_add_yet = true;
}
static const TypeInfo dp8393x_info = {
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG
When a constant has to be loaded in a mov op, we fail to assign
mem_coherent = 0. This patch fixes that.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg.c | 1 +
1 file changed, 1 insertion(+)
I found this issue by review. I haven't been
prefer the attached patch?
I have to say I am not sure what is the best, I don't know this part of
the code enough. I have added Paolo in Cc:, I guess he might have an
idea about that.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net
On 2015-07-25 15:06, Richard Henderson wrote:
On 07/24/2015 04:34 PM, Aurelien Jarno wrote:
ots-val_type = TEMP_VAL_CONST;
ots-val = ts-val;
+if (IS_DEAD_ARG(1)) {
+temp_dead(s, args[1]);
+}
Aren't we also missing
if (NEED_SYNC_ARG(0
This patchset improves the code generation for the SH4 target, by using
new TCG ops or using some tricks.
Aurelien Jarno (5):
target-sh4: add flags markups for FP helpers
target-sh4: use deposit in swap.b instruction
target-sh4: improve cmp/str instruction
target-sh4: improve shld
the implementation by computing both the value shifted to the
left and to the right, and then selecting the correct one with a
movcond. As with a negative value the shift amount can go up to 32 which
is undefined, we shift the value in two steps.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 3b4a1b5..a6f3f59 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
Most floating point helpers can trigger an exception, but don't change
the globals. Mark these helpers as TCG_CALL_NO_WG.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/helper.h | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff
the implementation by computing both the value shifted to the
left and to the right, and then selecting the correct one with a
movcond. As with a negative value the shift amount can go up to 32 which
is undefined, we shift the value in two steps.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
bits
set due to a value greater than 0x80 in the first sub-expression are
masked off by the second.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4
On 2015-07-24 13:14, Aurelien Jarno wrote:
The SH4 shad instruction can shift in both direction, depending on the
sign of the shift. This is currently implemented using branches, which
is not really efficient and prevents the optimizer to do its job. In
practice it is often used
The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32,
and the name in the README doesn't match the name offered to the
frontends.
Always use the long name to make it clear it is a size changing op.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno
variants of the code and with that bugs.
This patchset has been fully tested on x86-64 host, but only lightly
tested on aarch64, ppc64 and s390x hosts.
Aurelien Jarno (10):
tcg/optimize: optimize temps tracking
tcg/optimize: add temp_is_const and temp_is_copy functions
tcg/optimize: track
Cc: Claudio Fontana claudio.font...@huawei.com
Cc: Claudio Fontana claudio.font...@gmail.com
Cc: Richard Henderson r...@twiddle.net
Cc: Stefan Weil s...@weilnetz.de
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/aarch64/tcg-target.c | 4
tcg/i386/tcg-target.c| 5 +
tcg
Add two accessor functions temp_is_const and temp_is_copy, to make the
code more readable and make code change easier.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 131 ++---
1
are not counted as garbage, but that a size
changing op is replaced by a move.
This patch is basically a revert of 24666baf, including the changes that
have been made since then.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 43
0x7ffbebcae426
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index f16eb1e..48103b2 100644
--- a/tcg/optimize.c
+++ b/tcg
...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index cd0e793..20e24b3 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -50,6 +50,7
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/README | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tcg/README b/tcg/README
index 61b3899..a22f251 100644
--- a/tcg/README
+++ b/tcg/README
@@ -466,13
The tcg_gen_trunc_shr_i64_i32 function takes a 64-bit argument and
returns a 32-bit value. Directly call tcg_gen_op3 with the correct
types instead of calling tcg_gen_op3i_i32 and abusing the TCG types.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32
They behave the same as ext32s_i64 and ext32u_i64 from the constant
folding and zero propagation point of view, except that they can't
be replaced by a mov, so we don't compute the affected value.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg
Use two bools to track constants and copies instead of an enum.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/tcg/optimize.c b/tcg
On 2015-07-24 13:15, Richard Henderson wrote:
On 07/24/2015 09:30 AM, Aurelien Jarno wrote:
Now that copies and constants are tracked separately, we can allow
constant to have copies, deferring the choice to use a register or a
constant to the register allocation pass. This prevent
.
Cc: Richard Henderson r...@twiddle.net
Reported-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg.c | 3 +++
1 file changed, 3 insertions(+)
This is triggered by the patch tcg/optimize: allow constant to have
copies, but I guess it might
Someone has posted a similar fix a few weeks ago, and it has just been
merged.
** Changed in: qemu
Status: New = Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1477683
Title:
);
if (get_float_exception_flags(env-fp_status) float_flag_invalid) {
val = 0x8000ULL;
}
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Adding the maintainers of target-i386 in the loop so they might pick-up
the patch for 2.4.
--
Aurelien Jarno
pbonz...@redhat.com
Cc: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
While applying Paolo's fix for user-mode, I noticed this.
I've never seen this fail, but obviously what we have is wrong.
This patch depends on Paolo's cleanup.
r
having a mismatch because we'll end up pointing to the next
page which cannot possibly be in that same TLB entry.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel
this one in the pull request.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-20 09:33, Benjamin Herrenschmidt wrote:
On Mon, 2015-07-20 at 01:01 +0200, Aurelien Jarno wrote:
One way to improve this would be to reduce the size of a TLB entry.
Currently we store the page address separately for read, write and
code. The information is therefore quite
On 2015-07-18 23:18, Aurelien Jarno wrote:
On 2015-07-18 08:58, Richard Henderson wrote:
Enforce the invariant that 32-bit quantities are zero extended
in the register. This avoids having to re-zero-extend at memory
accesses for 32-bit guests.
Signed-off-by: Richard Henderson r
When computing the TLB address we are likely to mask out the high
32-bits by using shr + and. We can use 32-bit instructions in that
case. This saves 2 bytes per TLB access.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/i386/tcg-target.c | 16
entry by two on a 64-bit machine. It might be worth a try.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
/msg02492.html
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
and trunc_hi. No one really uses any other value for the
shift, and x86 could really use different constraints for the two.
That sounds like a good idea.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-18 08:21, Richard Henderson wrote:
On 07/17/2015 02:42 PM, Aurelien Jarno wrote:
On 2015-07-17 12:23, Aurelien Jarno wrote:
On 2015-07-16 22:29, Richard Henderson wrote:
On 07/15/2015 09:54 PM, Aurelien Jarno wrote:
While I understand why we need the new trunc_shr_i32 opcode
On 2015-07-18 08:24, Richard Henderson wrote:
On 07/17/2015 11:33 AM, Aurelien Jarno wrote:
For now I do wonder if we shouldn't get the size changing extu/exts
mandatory instead of reusing the 64-bit only version. This doesn't
change the generated code, at least on x86.
I'd be surprised
On 2015-07-17 12:23, Aurelien Jarno wrote:
On 2015-07-16 22:29, Richard Henderson wrote:
On 07/15/2015 09:54 PM, Aurelien Jarno wrote:
While I understand why we need the new trunc_shr_i32 opcode for MIPS64
(the 32-bit values must be kept sign-extended), I currently fail to
see why
insertions(+), 64 deletions(-)
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
That said I do wonder if it is 2.4 material or if it should be deferred
to 2.5.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-16 22:29, Richard Henderson wrote:
On 07/15/2015 09:54 PM, Aurelien Jarno wrote:
While I understand why we need the new trunc_shr_i32 opcode for MIPS64
(the 32-bit values must be kept sign-extended), I currently fail to
see why it is needed for SPARC.
As far as I recall
On 2015-07-17 07:38, Richard Henderson wrote:
On 07/15/2015 12:03 PM, Aurelien Jarno wrote:
Now that we have real size changing ops, we don't need to marked high
bits of the destination as garbage. The goal of the optimizer is to
predict the value of the temps (and not of the registers) and do
that it doesn't fail before using %gs.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
as the source of the store.
Indeed, that's something we might want to improve (and is due to the
fact we have just replaced trunc_shr_i64_i32 by a move on x86). Note
however that this simplification might be target specific (it is at
least little endian specific if we don't adjust the address).
--
Aurelien
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/README | 2 +-
tcg/aarch64/tcg-target.h | 2 +-
tcg/i386/tcg-target.h| 2 +-
tcg/ia64/tcg-target.h| 2 +-
tcg/optimize.c | 6 +++---
tcg/ppc/tcg-target.h | 2 +-
tcg/s390/tcg-target.h| 2 +-
tcg/sparc
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/aarch64/tcg-target.h | 6 +-
tcg/i386/tcg-target.h| 7 ++-
tcg/ia64/tcg-target.h| 6 +-
tcg/ppc/tcg-target.h | 7 ++-
tcg/s390/tcg-target.h| 6 +-
tcg/sparc/tcg-target.h | 6 +-
tcg/tcg-op.c
-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg-op.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 61b64db..0e79fd1 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1752,8 +1752,8 @@ void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret, TCGv_i64
arg
Implementing them as real ops means they can't be optimized out by
the register allocator or the optimizer.
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/i386/tcg-target.c | 5 +
tcg/i386/tcg-target.h
They behave the same as ext32s_i64 and ext32u_i64 from the constant
folding and zero propagation point of view, except that they can't
be replaced by a mov, so we don't compute the affected value.
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien
things are
currently handled.
Aurelien Jarno (9):
tcg: rename trunc_shr_i32 into trunc_shr_i64_i32
tcg: don't abuse TCG type in tcg_gen_trunc_shr_i64_i32
tcg: implement real ext_i32_i64 and extu_i32_i64 ops
tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops
tcg/i386
On 2015-07-15 11:02, Richard Henderson wrote:
On 07/15/2015 09:06 AM, Aurelien Jarno wrote:
On 2015-07-15 09:31, Paolo Bonzini wrote:
Ok, I see your point. If you put it like this :) the fault definitely
lies in the backends. What I'm proposing would be in a new
tcg_reg_alloc_trunc function
On 2015-07-15 12:14, Aurelien Jarno wrote:
On 2015-07-15 11:02, Richard Henderson wrote:
On 07/15/2015 09:06 AM, Aurelien Jarno wrote:
On 2015-07-15 09:31, Paolo Bonzini wrote:
Ok, I see your point. If you put it like this :) the fault definitely
lies in the backends. What I'm proposing
...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg-op.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c8db812..b4b1654 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1775,7 +1775,7
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/README | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/README b/tcg/README
index 61b3899..d8fd17a 100644
--- a/tcg
? It
doesn't make sense either given the high bits of some of these registers
can become garbage at any moment.
Can you please give some more details about this so that I can add SPARC
target support to the tcg: improve size changing ops series? Thanks.
Aurelien
--
Aurelien Jarno
are not counted as garbage, but that a size
changing op is replaced by a move.
This patch is basically a revert of 24666baf, including the changes that
have been made since then.
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/i386/tcg-target.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 16f3949..d483083
,
+ GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR,
+ otype, addr_reg);
#endif /* CONFIG_SOFTMMU */
}
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http
, I3312_STRX, data_r, addr_r, otype, off_r);
break;
default:
tcg_abort();
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
an explicit zero-extension.
The zero-extension can be done in place as we know the registers holds
a 32-bit value.
Reported-by: Leon Alrae leon.al...@imgtec.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien
loading which can take a few instructions on RISC hosts.
Cc: Leon Alrae leon.al...@imgtec.com
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
Changes v1 - v2:
- Use ~(-1 t1) instead of (1 t1) - 1
to wait for 2.5.
Aurelien Jarno (2):
target-mips: fix page fault address for LWL/LWR/LDL/LDR
target-mips: simplify LWL/LDL mask generation
target-mips/translate.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
--
2.1.4
;
+env-hflags = ~MIPS_HFLAG_DM;
compute_hflags(env);
debug_post_eret(env);
-env-lladdr = 1;
}
#endif /* !CONFIG_USER_ONLY */
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http
= CMPOP;
break;
default:
MIPS_INVAL(opn);
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
By the way, is this debug code really useful? I think by looking at the
TCG code (-d in_asm,op), it's easy to determine if an instruction is
correctly disassembled or not.
--
Aurelien
On 2015-07-11 19:00, Peter Crosthwaite wrote:
From: Peter Crosthwaite crosthwaitepe...@gmail.com
Move the target_disas() sh4 specifics to the QOM disas_set_info hook
and delete the #ifdef specific code in disas.c.
Cc: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Peter Crosthwaite
-bit
constant loading which can take a few instructions on RISC hosts.
Cc: Leon Alrae leon.al...@imgtec.com
Tested-by: Hervé Poussineau hpous...@reactos.org
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions
Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
to possibly trigger a page
fault and fill the QEMU TLB.
Cc: Leon Alrae leon.al...@imgtec.com
Reported-by: Hervé Poussineau hpous...@reactos.org
Tested-by: Hervé Poussineau hpous...@reactos.org
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 12
1 file
On 2015-07-14 17:22, Leon Alrae wrote:
On 14/07/2015 16:45, Aurelien Jarno wrote:
By the way, is this debug code really useful? I think by looking at the
TCG code (-d in_asm,op), it's easy to determine if an instruction is
correctly disassembled or not.
For me this debug code doesn't
On 2015-07-14 18:17, Paolo Bonzini wrote:
On 14/07/2015 17:45, Aurelien Jarno wrote:
The LWL/LDL instructions mask the GPR with a mask depending on the
address alignement. It is currently computed by doing:
mask = 0x7fffull (t1 ^ 63)
It's simpler to generate
for 2.4 to fix this, but in case it's not
possible we can apply your patch.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-07-14 22:56, Paolo Bonzini wrote:
On 14/07/2015 20:37, Aurelien Jarno wrote:
I certainly don't have a global view, so much that I didn't think at
all of the optimizer... Instead, it looks to me like a bug in the
register allocator. In particular this code
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