This remove the corresponding error messages in TCG mode, and allow to
simplify the s390_assign_subch_ioeventfd() function.
CC: Cornelia Huck cornelia.h...@de.ibm.com
Cc: Christian Borntraeger borntrae...@de.ibm.com
Cc: Alexander Graf ag...@suse.de
Signed-off-by: Aurelien Jarno aurel...@aurel32
-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/ioinst.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/ioinst.h b/target-s390x/ioinst.h
index 203bdba..013cc91 100644
--- a/target-s390x/ioinst.h
+++ b/target-s390x/ioinst.h
@@ -220,7 +220,7 @@ typedef
From: Alexander Graf ag...@suse.de
The ioinst_schib_valid gets a SCHIB in guest endianness, we should
byteswap the fields we access.
Cc: Christian Borntraeger borntrae...@de.ibm.com
Cc: Cornelia Huck cornelia.h...@de.ibm.com
Signed-off-by: Alexander Graf ag...@suse.de
Signed-off-by: Aurelien
From: Alexander Graf ag...@suse.de
The code handling the I/O instructions for KVM decodes the instruction
itself. In TCG mode also pass the full instruction word to the helpers.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Alexander Graf ag...@suse.de
Signed-off-by: Aurelien Jarno aurel
...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 7f17823..c4e8a87 100644
--- a/target-s390x/cpu.c
+++ b
env-io_index[] should be set to -1 during CPU reset to mark the
I/O interrupt queue as empty.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.c | 8
1 file changed, 8 insertions(+)
diff
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/misc_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index e36d957..3addde5 100644
: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 08a79dd..93f66f9 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -709,6 +709,7
Make sure to not modify the branch target. This ensure that the
branch target is not corrupted during partial retranslation.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/s390/tcg-target.c | 12
1
On 2015-06-15 10:39, Pavel Dovgaluk wrote:
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-06-15 07:53, Pavel Dovgaluk wrote:
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
This patch fixes exception handling in MIPS
On 2015-06-15 10:48, Pavel Dovgaluk wrote:
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-06-15 07:53, Pavel Dovgaluk wrote:
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
This patch fixes exception handling in MIPS
On 2015-06-15 07:53, Pavel Dovgaluk wrote:
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
This patch fixes exception handling in MIPS.
MIPS instructions generate several types of exceptions.
When exception is generated, it breaks
or an admin can probably fix that.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Aurelien Jarno (9):
sh4/r2d: convert to new MMIO accessor style
target-sh4: use bit number for SR constants
target-sh4: Split out T from SR
target-sh4: optimize addc using add2
target-sh4: optimize subc using sub2
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
linux-user/main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 6989b82..a0d3e58 100644
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5c90fe3..b8abfd5 100644
In preparation for more efficient setting of this field.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bcdf4f3..5c90fe3 100644
--- a/target
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 44d0e94..e8b9217 100644
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
At the same time removed the now unused gen_copy_bit_i32 function.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.h
to trigger the watchpoint. For now we assume it comes
from the default ASC.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu-qom.h| 1 +
target-s390x/cpu.c| 1 +
target-s390x/cpu.h
To avoid to many #ifdef in target code, provide a tlb_vaddr_to_host for
both user and softmmu modes. In the first case the function always
succeed and just call the g2h function.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
include/exec/cpu_ldst.h | 8 ++--
1 file changed, 6
On 2015-06-12 16:12, Riku Voipio wrote:
On Thursday, June 4, 2015 10:55:12 PM EEST, Aurelien Jarno wrote:
On 2015-06-02 21:50, Richard Henderson wrote:
On 05/24/2015 03:51 PM, Aurelien Jarno wrote: ...
I have added them in my sh4-next branch [1], they will be in the next
pull request.
[1
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.h | 16
1 file changed, 16 insertions(+)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 584e74b..4ff3f5c 100644
This function returns the ATMID field that is stored in the
per_perc_atmid lowcore entry.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.h | 12
1 file changed, 12 insertions(+)
diff
performances improvements.
At the same time change the name of the function to fast_memset as it's
not specific to mvc and use the same argument order as the C memset
function.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
This patch adds a function to adjust the length of a transfer so that
it doesn't cross a page boundary in softmmu mode. It does nothing in
user mode.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x
in that case, don't try to retranslate the code, but
assume that the CPU state (and especially the program counter) has been
saved before calling the helper. Then invalidate the TB based on this
address.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
translate-all.c | 20 +++-
1 file
This function checks if an address is in between the PER starting
address and the PER ending address, taking care of a possible
address range loop.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.h
and watchpoints.
Aurelien Jarno (15):
softmmu: provide tlb_vaddr_to_host function for user mode
target-s390x: function to adjust the length wrt page boundary
target-s390x: mvc_fast_memset: access memory through softmmu
target-s390x: mvc_fast_memmove: access memory through softmmu
target-s390x: add
helper.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/misc_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index ca3aabe
as the C memmove
function.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/mem_helper.c | 84 +++
1 file changed, 27 insertions(+), 57 deletions(-)
diff --git
This PER event happens each time the STURA or STURG instructions are
used. As they use helpers, we can just save the event in the PER code
there, if enabled.
Cc: Richard Henderson r...@twiddle.net
Cc: Alexander Graf ag...@suse.de
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target
, as we have disabled
them in the previous patch.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/helper.h | 1 +
target-s390x/misc_helper.c | 11 +++
target-s390x/translate.c | 39
-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/helper.h | 1 +
target-s390x/misc_helper.c | 8
target-s390x/translate.c | 8
3 files changed, 17 insertions(+)
diff --git a/target-s390x
to low core memory when a program exception
happens.
Cc: Richard Henderson r...@twiddle.net
Cc: Alexander Graf ag...@suse.de
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.c | 6 ++
target-s390x/cpu.h | 12 +++-
target-s390x/helper.c| 1 +
target
exception immediately after.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.h | 3 +++
target-s390x/helper.c | 54 ++
target-s390x/helper.h | 1
From: Richard Henderson r...@twiddle.net
Only exposing FPU and LLSC as the only features
supported by the translator.
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
linux-user/elfload.c | 29 +
1 file changed
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index b8abfd5..9ab3ba0 100644
--- a/target
The documentation is clear to use 16-bit accesses for all registers.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
hw/sh4/r2d.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 4221060..5e22ed7 100644
--- a/hw/sh4/r2d.c
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index e8b9217..28259f9 100644
--- a/target-sh4/translate.c
+++ b/target
applies on top of the Config5.FRE patches.
Regards,
Leon
The whole series is:
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
is
not linear.
That said address_space_translate is supposed to adjust the length if
needed, but does so only if iommu_ops is defined. I therefore wonder if
you therefore shouldn't model this DMA translation tables by using IOMMU
ops instead of subregions.
--
Aurelien Jarno
);
gen_helper_0e0i(raise_exception, excp);
+ctx-bstate = BS_STOP;
}
Why do we need to stop the translation here? The exception might be
conditional (for example for ADDU or SUBU).
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Most of the calls to tcg_opt_gen_mov are preceeded by a test to check if
the source temp is a constant. Fold that into the tcg_opt_gen_mov
function.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 89
/translate_init.c | 4 +++-
6 files changed, 32 insertions(+), 7 deletions(-)
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
As a side note, I have seen that you have added a check for MIPS2 to the
ERET instruction. This is correct, but given in practice we don't
emulate any MIPS1 CPU, I do wonder
-cpu_model-CP0_SRSConf1_rw_bitmask;
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-04 14:07, Richard Henderson wrote:
On 06/04/2015 12:53 PM, Aurelien Jarno wrote:
+
static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args,
TCGArg dst, TCGArg src)
{
+if (temps[src].state == TCG_TEMP_CONST
...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/tcg.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8b43bbb..c5e2ce9 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1998,6 +1998,16 @@ static void tcg_reg_alloc_op(TCGContext *s
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bcdf4f3..5c90fe3 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5453a86..4c75575 100644
--- a/target-sh4/translate.c
+++ b/target
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 44d0e94..5453a86 100644
This patch series does some small cleanups to make the optimizer code
more readable. It doesn't bring any functional change.
Aurelien Jarno (5):
tcg/optimize: remove opc argument from tcg_opt_gen_movi
tcg/optimize: remove opc argument from tcg_opt_gen_mov
tcg/optimize: fold temp copies
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30
the tricks used in div1
Changes v1 - v2:
- rebased
- added last patch
Aurelien Jarno (8):
target-sh4: use bit number for SR constants
target-sh4: Split out T from SR
target-sh4: optimize addc using add2
target-sh4: optimize subc using sub2
target-sh4: optimize negc using add2 and sub2
target
// %ebx is now cpu_sr_t
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-02 21:25, Aurelien Jarno wrote:
The following changes since commit f5790c3bc81702c98c7ddadedb274758cff8cbe7:
Revert target-alpha: Add vector implementation for CMPBGE (2015-05-22
12:30:13 +0100)
are available in the git repository at:
git://git.aurel32.net/qemu.git tags
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5c90fe3..b8abfd5 100644
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 213
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
At the same time removed the now unused gen_copy_bit_i32 function.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.h
Most of the calls to tcg_opt_gen_mov are preceeded by a test to check if
the source temp is a constant. Fold that into the tcg_opt_gen_mov
function.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 89
Each call to tcg_opt_gen_mov is preceeded by a test to check if the
source and destination temps are copies. Fold that into the
tcg_opt_gen_mov function.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 27
The tcg_constant_folding folding ends up doing all the optimizations
(which is a good thing to avoid looping on all ops multiple time), so
make it clear and just rename it tcg_optimize.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c
. This avoid emitting a move
and using a register for the movcond instruction when used as move if
true on x86-64. This might bring more improvements on RISC TCG targets
which don't have outputs aliased to inputs.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel
triggered by the second one.
Aurelien Jarno (2):
tcg: fix register allocation with two aliased dead inputs
tcg: fix dead computation for repeated input arguments
tcg/tcg.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
--
2.1.4
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index b8abfd5..9ab3ba0 100644
--- a/target
We can get the opcode using the TCGOp pointer. It needs to be
dereferenced, but it's anyway done a few lines below to write
the new value.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 14 +++---
1 file changed, 7
On 2015-06-02 21:50, Richard Henderson wrote:
On 05/24/2015 03:51 PM, Aurelien Jarno wrote:
On 2015-05-23 15:06, Richard Henderson wrote:
As reported by Rich the other day. As I don't have a user-land
binary that depends on this, I merely note that it still runs
the linux-user-test sh4
We can get the opcode using the TCGOp pointer. It needs to be
dereferenced, but it's anyway done a few lines below to write
the new value.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/optimize.c | 40
1
It belongs to the DFP rounding facility.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the
numbers as unsigned, as its name implies.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/insn-data.def | 2 +-
1 file
It is part of the basic zArchitecture instructions. Allow it to be call
from EXECUTE.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2
RISBGN is the same as RISBG, but without setting the condition code.
CLT and CLGT are the same as CLRT and CLGRT, but using memory for the
second operand.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
Use constants to define the MMU indexes, and add a function to do
the reverse conversion of cpu_mmu_index.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/cpu.h | 25 ++---
1 file
},
-{ mips, magnum, 0x9000, .bswap = true },
-{ mips, pica61, 0x9000, .bswap = true },
{ mips, mips, 0x1400, .bswap = true },
{ mips, malta, 0x1000, .bswap = true },
{ mips64, magnum, 0x9000, .bswap = true },
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/mem_helper.c | 53 ++-
1 file changed, 20 insertions(+), 33 deletions(-)
diff --git a/target-s390x/mem_helper.c b/target-s390x
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/insn-data.def | 10 ++
target-s390x/translate.c | 80 --
2 files changed, 81 insertions(+), 9 deletions(-)
diff --git a/target-s390x/insn
This complete the floating point support sign handling facility.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/insn-data.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-s390x
This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test
in the gcc testsuite.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/fpu_helper.c | 31 +++
target
Besides RISBHG and RISBLG, all high-word instructions are not
implemented. Fix that.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/insn-data.def | 47
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
STORE CLOCK FAST should be in the SCF facility.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn
represents (length - 1).
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/mem_helper.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
It is part of the basic zArchitecture instructions.
Cc: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_helper.c | 39
0x0001 to generate a trap.
Cc: Alexander Graf ag...@suse.de
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/translate.c b/target-s390x
: Alexander Graf ag...@suse.de
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-s390x/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 6b47766..90d273c 100644
--- a/target
The documentation is clear to use 16-bit accesses for all registers.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
hw/sh4/r2d.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 4221060..5e22ed7 100644
--- a/hw/sh4/r2d.c
in patch 6
- add specification exception for odd r1 in patch 8
- pass more values as arguments in patch 8
- add the 4 last patches
Aurelien Jarno (16):
target-s390x: fix exception for invalid operation code
target-s390x: fix CLGIT instruction
target-s390x: change CHRL and CGHRL format to RIL
On 2015-06-02 19:01, Christopher Covington wrote:
Hi Aurelien,
On 06/01/2015 05:29 PM, Aurelien Jarno wrote:
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson r...@twiddle.net
On 2015-06-03 09:09, Aurelien Jarno wrote:
On 2015-06-02 19:01, Christopher Covington wrote:
Hi Aurelien,
On 06/01/2015 05:29 PM, Aurelien Jarno wrote:
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts
On 2015-06-02 13:58, Richard Henderson wrote:
On 06/02/2015 01:10 PM, Aurelien Jarno wrote:
It looks like we have to go through the MMIO functions to get the
TLB_NOTDIRTY bit cleaned correctly. This is something we don't want for
probe_write, so we definitely want two different functions
On 2015-06-02 13:54, Richard Henderson wrote:
On 06/02/2015 04:26 AM, Aurelien Jarno wrote:
int index = (addr TARGET_PAGE_BITS) (CPU_TLB_SIZE - 1);
-CPUTLBEntry *tlbentry = env-tlb_table[mmu_idx][index];
+CPUTLBEntry *tlbentry;
target_ulong tlb_addr;
uintptr_t
/ TARGET_PAGE_SIZE];
if (*flags PAGE_READ) {
*sk |= SK_R;
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-01 18:33, Richard Henderson wrote:
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
D(0x8400, BRXH,RSI, Z, 0, 0, 0, 0, bx32, 0, 0)
D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
-D(0xec45
On 2015-06-01 20:07, Richard Henderson wrote:
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
+/* LOAD FP INTEGER */
+C(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0)
+C(0xb35f, FIDBR, RRF_e, Z, 0, f2_o, f1, 0, fidb, 0)
+C(0xb347, FIXBR, RRF_e, Z, 0, f2_o, x1, 0, fixb
On 2015-06-02 10:07, Richard Henderson wrote:
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
+/* TRANSLATE EXTENDED */
+C(0xb2a5, TRE, RRE, Z, 0, 0, 0, 0, tre, 0)
...
+static ExitStatus op_tre(DisasContext *s, DisasOps *o)
+{
+TCGv_i32 r1 = tcg_const_i32(get_field(s
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 212
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30
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