Hi Sameer,
On Tue, Apr 16, 2024 at 02:26:10PM -0400, Sameer Kalliadan Poyil wrote:
> Hi Bastian,
>
> Thanks for the information. I thought that I can do some prototyping before
> the
> HW arrives. :)
>
> Yes I am interested for your bare metal program boot_to_main run it on TSIM.
>
> Is
Hi Sameer,
On Sun, Apr 14, 2024 at 06:15:56PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Sameer,
>
> On 13/4/24 14:52, Sameer Kalliadan Poyil wrote:
> > Hello All,
> > I see that Latest qemu supports for tricore TC277 and TC377
> > image.png
> > But when I downloaded source code and checked for
2 files changed, 13 insertions(+), 12 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
y: Philippe Mathieu-Daudé
> ---
> target/tricore/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
| 4 +---
> 2 files changed, 1 insertion(+), 6 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On Tue, Jan 30, 2024 at 09:30:40AM +1000, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/tricore/cpu.c | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
e/cpu.c | 20
> target/tricore/gdbstub.c | 6 ++
> target/tricore/helper.c| 3 +--
> target/tricore/translate.c | 3 +--
> 4 files changed, 8 insertions(+), 24 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On Thu, Oct 19, 2023 at 11:29:20AM -0700, Richard Henderson wrote:
> The EXTR instructions can use the extract opcodes.
>
> Signed-off-by: Richard Henderson
> ---
> target/tricore/translate.c | 20
> 1 file changed, 4 insertions(+), 16 deletions(-)
Re
Signed-off-by: Bastian Koppelmann
---
target/tricore/tricore-semi.c | 101 ++
1 file changed, 101 insertions(+)
diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c
index 2188ceeed0..34e546c3bf 100644
--- a/target/tricore/tricore-semi.c
Signed-off-by: Bastian Koppelmann
---
target/tricore/tricore-semi.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c
index 27e1bdc59d..ccbeae4bc0 100644
--- a/target/tricore/tricore-semi.c
+++ b
Signed-off-by: Bastian Koppelmann
---
target/tricore/tricore-semi.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c
index ccbeae4bc0..6f321391ef 100644
--- a/target/tricore/tricore-semi.c
+++ b/target/tricore
] https://github.com/bkoppelmann/package_940/tree/main/newlib/libgloss/tricore
Bastian Koppelmann (6):
target/tricore: Add semihosting stub
target/tricore: Add read and write semihosting calls
target/tricore: Add lseek semihosting call
target/tricore: Add close semihosting call
target
Signed-off-by: Bastian Koppelmann
---
target/tricore/tricore-semi.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c
index 6f321391ef..2188ceeed0 100644
--- a/target/tricore/tricore-semi.c
+++ b/target/tricore
Signed-off-by: Bastian Koppelmann
---
configs/devices/tricore-softmmu/default.mak | 1 +
docs/about/emulation.rst| 3 +++
qemu-options.hx | 3 ++-
target/tricore/translate.c | 13 +++--
4 files changed, 17 insertions
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/meson.build| 1 +
target/tricore/tricore-semi.c | 197 ++
3 files changed, 199 insertions(+)
create mode 100644 target/tricore/tricore-semi.c
diff --git a/target
On Fri, Oct 13, 2023 at 11:46:02AM +0300, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis
> ---
Reviewed-by: Bas
Reviewed-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 36 +++
target/tricore/he
this is not something other ISAs do, so clarify it with a comment.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 5 +
1 file changed, 5 insertions(+)
diff
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/ma
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++
1 file changed, 9 inse
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 32 +++
target/tricore/helper.h | 1 +
target/tricore/trans
as this is an effective address and those cannot be signed,
it should not be a signed integer.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16
1 file changed, 8 insertions
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_he
riCore is not
the one used by softfloat.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-4-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/ta
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-3-kbast...@mail.uni-paderborn.de>
---
hw/tricore/tricore_testdevice.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..9028d970b0
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/t
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-12-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/trans
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-7-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 38 +++
target/t
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-4-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file chan
Changes from v2:
- Replaced %ld with PRIu64 for patch 13
- Dropped patches 15 - 19, as they require an updated patch series
Bastian Koppelmann (16):
tests/tcg/tricore: Bump cpu to tc37x
target
we don't want to exclude ISA v1.6.2 insns from our tests.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230828112651.522058-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Hi,
On Thu, Sep 28, 2023 at 10:26:18AM -0400, Stefan Hajnoczi wrote:
> Please take a look at these CI test failures:
> https://gitlab.com/qemu-project/qemu/-/jobs/5185201978
> https://gitlab.com/qemu-project/qemu/-/jobs/5185202098
I'll fix the build failure and drop the patches that fail the
Changes from v1:
- Removed sas.py file that slipped in patch 15
Bastian Koppelmann (21):
tests/tcg/tricore: Bump cpu to tc37x
target/tricore: Implement CRCN
this is not something other ISAs do, so clarify it with a comment.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 5 +
1 file changed, 5 insertions(+)
diff
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++
1 file changed, 9 inse
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/ma
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-4-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file chan
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-8-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 13
tests/tcg/tricore/asm/test_arith.S | 105 +
2 files changed, 118 insertions(+)
diff --git a/tests/tcg/trico
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-6-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 11 +++
tests/tcg/tricore/asm/test_arith.S | 47 ++
2 files changed, 58 insertions(+)
diff --git a/tests/tcg/trico
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/t
Reviewed-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 36 +++
target/tricore/he
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-5-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 3 +-
tests/tcg/tricore/asm/macros.h| 50 +++
tests/tcg/tricore/asm/test_arith.S
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 32 +++
target/tricore/helper.h | 1 +
target/tricore/trans
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-7-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 38 +++
target/t
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-7-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 51 ++--
tests/tcg/tricore/asm/test_arith.S | 53 ++
2 files changed, 102 insertions(+), 2 del
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-9-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/test_arith.S | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tests/tcg/tricore/asm/test_arith.S
b/tests/tcg/trico
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_he
as this is an effective address and those cannot be signed,
it should not be a signed integer.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16
1 file changed, 8 insertions
we don't want to exclude ISA v1.6.2 insns from our tests.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230828112651.522058-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-12-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/trans
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-3-kbast...@mail.uni-paderborn.de>
---
hw/tricore/tricore_testdevice.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..d0f8db9089
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3
riCore is not
the one used by softfloat.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-4-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/ta
On Wed, Sep 27, 2023 at 11:35:31AM +0200, Bastian Koppelmann wrote:
> The following changes since commit 11a629d246e4e7785a6f0efb99bd15a32c04feda:
>
> Merge tag 'pull-nbd-2023-09-25' of https://repo.or.cz/qemu/ericb into
> staging (2023-09-26 09:04:23 -0400)
>
> are av
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-3-kbast...@mail.uni-paderborn.de>
---
hw/tricore/tricore_testdevice.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..d0f8db9089
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/t
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 36 +++
target/tricore/he
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/ma
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-4-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file chan
this is not something other ISAs do, so clarify it with a comment.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 5 +
1 file changed, 5 insertions(+)
diff
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_he
riCore is not
the one used by softfloat.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-4-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/ta
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 32 +++
target/tricore/helper.h | 1 +
target/tricore/trans
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-9-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/test_arith.S | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tests/tcg/tricore/asm/test_arith.S
b/tests/tcg/trico
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-5-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 3 +-
tests/tcg/tricore/asm/macros.h| 50 +++
tests/tcg/tricore/asm/sas.py | 21 ++
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-8-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 13
tests/tcg/tricore/asm/test_arith.S | 105 +
2 files changed, 118 insertions(+)
diff --git a/tests/tcg/trico
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-7-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 38 +++
target/t
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-7-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 51 ++--
tests/tcg/tricore/asm/test_arith.S | 53 ++
2 files changed, 102 insertions(+), 2 del
TriCore insns
Bastian Koppelmann (21):
tests/tcg/tricore: Bump cpu to tc37x
target/tricore: Implement CRCN insn
target/tricore: Correctly handle FPU RM from PSW
target/tricore: Implement FTOU insn
target
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-12-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/trans
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++
1 file changed, 9 inse
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-6-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 11 +++
tests/tcg/tricore/asm/test_arith.S | 47 ++
2 files changed, 58 insertions(+)
diff --git a/tests/tcg/trico
as this is an effective address and those cannot be signed,
it should not be a signed integer.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16
1 file changed, 8 insertions
we don't want to exclude ISA v1.6.2 insns from our tests.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230828112651.522058-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
). These are already defined in csfr.h.inc, so I use
this definition.
I also changed the types of the effective address (ea) in op_helper.c to
target_ulong, as it cannot be sign extened.
Cheers,
Bastian
Bastian Koppelmann (10):
tests/tcg/tricore: Extended and non-extened regs now match
hw/tricore: Log failing
as this is an effective address and those cannot be signed,
it should not be a signed integed.
Signed-off-by: Bastian Koppelmann
---
target/tricore/op_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/macros.h | 13
tests/tcg/tricore/asm/test_arith.S | 105 +
2 files changed, 118 insertions(+)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 92f0f7b22b
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/macros.h | 38 +-
1 file changed, 19
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 3 +-
tests/tcg/tricore/asm/macros.h| 50 +++
tests/tcg/tricore/asm/test_arith.S| 41 +++
3 files changed, 93 insertions(+), 1 deletion(-)
create mode
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/tricore/asm
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/macros.h | 11 +++
tests/tcg/tricore/asm/test_arith.S | 47 ++
2 files changed, 58 insertions(+)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 8ed2249b0d
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.h | 143 +++
1 file changed, 9 insertions(+), 134 deletions(-)
diff --git a/target/tricore/cpu.h b/target
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/test_arith.S | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tests/tcg/tricore/asm/test_arith.S
b/tests/tcg/tricore/asm/test_arith.S
index 728509cfa9..02637f89f9 100644
--- a/tests/tcg/tricore/asm
Signed-off-by: Bastian Koppelmann
---
hw/tricore/tricore_testdevice.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..d0f8db9089 100644
--- a/hw/tricore/tricore_testdevice.c
+++ b/hw/tricore
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/macros.h | 51 ++--
tests/tcg/tricore/asm/test_arith.S | 53 ++
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore
lper.c | 13 +
> 2 files changed, 10 insertions(+), 12 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
tant_i32(const9);
> | ^~~~
> target/tricore/translate.c:4958:10: note: shadowed declaration is here
>4958 | TCGv temp;
> | ^~~~
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/tricore/translate.c | 6 +++---
> 1 file changed, 3 insertion
On Mon, Aug 28, 2023 at 06:52:42PM -0400, Stefan Hajnoczi wrote:
> On Thu, 24 Aug 2023 at 14:29, Richard Henderson
> wrote:
> >
> > The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
> >
> > Merge tag 'pull-target-arm-20230824' of
> >
this is not something other ISAs do, so clarify it with a comment.
Signed-off-by: Bastian Koppelmann
---
target/tricore/fpu_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3aefeb776e..d0c474c5f3 100644
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 403533c564..cc2030be14 100644
--- a/target/tricore/translate.c
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Removed special case for f_arg being infinity
- Clarified, why we need a special case for arg being NAN
target/tricore/fpu_helper.c |
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Removed special case for f_arg being infinity
- Clarified, why we need a special case for arg being NAN
target/tricore/fpu_helper.c |
e need a special case for arg being NAN (ftohp, hptof)
Bastian Koppelmann (11):
tests/tcg/tricore: Bump cpu to tc37x
target/tricore: Implement CRCN insn
target/tricore: Correctly handle FPU RM from PSW
target/tricore: Implement FTOU insn
target/tricore: Clarify special case for FTOUZ insn
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