On 03/30/2017 03:04 PM, Cédric Le Goater wrote:
> On 03/30/2017 08:46 AM, David Gibson wrote:
>> On Wed, Mar 29, 2017 at 03:53:24PM +0200, Cédric Le Goater wrote:
>>> This is the second step to abstract the IRQ 'server' number of the
>>> XICS layer. Now that the prereq cleanups have been done in
On 06/06/2016 08:27 AM, Cédric Le Goater wrote:
> On 06/06/2016 12:26 AM, Mark Cave-Ayland wrote:
>> On 05/06/16 18:41, Cédric Le Goater wrote:
>>
>>> Hello Mark,
>>>
>>> On 06/03/2016 03:52 PM, Mark Cave-Ayland wrote:
On 03/06/16 13:11, Cédric Le Goater wrote:
> This is follow up to
On 06/03/2016 04:00 PM, Cédric Le Goater wrote:
> Hello Mark,
>
> On 06/03/2016 03:52 PM, Mark Cave-Ayland wrote:
>> On 03/06/16 13:11, Cédric Le Goater wrote:
>>
>>> This is follow up to complete the serie "ppc: preparing pnv landing
>>> (round 2)" plus a little fix on instruction privileges.
On 11/03/2014 03:53 PM, Alexander Graf wrote:
On 27.10.14 11:23, Cédric Le Goater wrote:
Currently, when the page tables are saved, the kvm_get_htab_header structs
and the ptes are assumed being big endian and dumped as a indistinct blob
in the statefile. This is no longer true when the
On 06/27/2014 06:26 AM, Richard Henderson wrote:
With rt != r0 on loads, we use rt for scratch. If we need an index
register different from base, we can't use rt, but r0 is usable.
That fixes the problem : a x86_64 fedora 20 TCG guest now runs under a
the latest qemu, (trusty ppc64le host)
On 06/13/2014 01:52 PM, Alexander Graf wrote:
On 13.06.14 13:24, Greg Kurz wrote:
From: Rusty Russell ru...@rustcorp.com.au
Signed-off-by: Rusty Russell ru...@rustcorp.com.au
Reviewed-by: Anthony Liguori aligu...@us.ibm.com
[ pass VirtIODevice * to memory accessors,
TCP checksums fix
On 04/14/2014 02:49 PM, Alexander Graf wrote:
On 14.04.14 14:46, Michael S. Tsirkin wrote:
On Mon, Apr 14, 2014 at 02:40:04PM +0200, Alexander Graf wrote:
On 14.04.14 14:37, Michael S. Tsirkin wrote:
On Mon, Apr 14, 2014 at 02:29:20PM +0200, Alexander Graf wrote:
On 14.04.14 14:24, Michael
On 02/20/2014 02:07 PM, Alexander Graf wrote:
On 20.02.2014, at 14:01, Cédric Le Goater c...@fr.ibm.com wrote:
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
000a7cc0 memrchr:
a7cc0: 11 00 4c 3c addis r2,r12,17
