On 10/23/15 01:53, Richard Henderson wrote:
> On 10/20/2015 05:26 AM, Chen Gang wrote:
>>> From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
>> From: Chen Gang <gang.chen.5...@gmail.com>
>> Date: Tue, 20 Oct 2015 23:19:02 +0800
>> Subje
>From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Tue, 20 Oct 2015 23:19:02 +0800
Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
Originally, tilegx qemu only implement prefetch instruction
>From 5bfae9eaa7c6757c83b1b3d958dd24988394fb03 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sat, 17 Oct 2015 21:39:25 +0800
Subject: [PATCH] temporary-floating-point: Use "0 - val" for the negtive value
It is a bug, original implementation is inc
and clearly (or sometimes, I maybe misunderstand,
then waste our time resources).
Thanks.
On 10/10/15 06:50, Chen Gang wrote:
>
> On 10/10/15 06:10, Richard Henderson wrote:
>> On 10/09/2015 09:48 AM, Chen Gang wrote:
>>> On 10/7/15 18:17, Chen Gang wrote:
>>>> On 10/7/
On 10/10/15 06:10, Richard Henderson wrote:
> On 10/09/2015 09:48 AM, Chen Gang wrote:
>> On 10/7/15 18:17, Chen Gang wrote:
>>> On 10/7/15 17:19, Richard Henderson wrote:
>>>> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>>>>> From 40ec3f1c75b4c97e3
On 10/7/15 18:17, Chen Gang wrote:
> On 10/7/15 17:19, Richard Henderson wrote:
>> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>>> From: Chen Gang<gang.chen.5...@gmail.com>
>>> Dat
On 10/7/15 17:29, Richard Henderson wrote:
> On 10/07/2015 01:56 AM, Chen Gang wrote:
>>> From 3655bbab04063bc0878510ab260832c7a6a2a925 Mon Sep 17 00:00:00 2001
>> From: Chen Gang<gang.chen.5...@gmail.com>
>> Date: Tue, 6 Oct 2015 21:45:11 +0800
>> Subject:
On 10/7/15 17:19, Richard Henderson wrote:
> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>> From: Chen Gang<gang.chen.5...@gmail.com>
>> Date: Sun, 4 Oct 2015 17:34:17 +0800
>> Subject: [PA
>From fa0950e403bbb98989117f632215ae0e698457d7 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:41:14 +0800
Subject: [PATCH v5] target-tilegx: Support iret instruction and related special
registers
Acording to the __longjmp tilegx libc imple
Oh, sorry. I will send patch v6 for it.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
> Subject: Re: [PATCH v5] target-tilegx: Support iret instruction and related
> special registers
> To: xil
>From fa0950e403bbb98989117f632215ae0e698457d7 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:41:14 +0800
Subject: [PATCH v6] target-tilegx: Support iret instruction and related special
registers
EX_CONTEXT_0_0 is used for jumpin
>From 3655bbab04063bc0878510ab260832c7a6a2a925 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Tue, 6 Oct 2015 21:45:11 +0800
Subject: [PATCH v2] temp-floating-point: Use make_float32/64 and float32/64_val
for the input register values
Original implementatio
> On 5 October 2015 at 12:21, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>> +static float32 t_to_float32 (uint32_t a)
>> +{
>> + CPU_FloatU r;
>> + r.l = a;
>> + return r.f;
>> +}
>
> This appears to be reimplementing make_float32().
&g
> From: peter.mayd...@linaro.org
> On 5 October 2015 at 12:54, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>>> On 5 October 2015 at 12:21, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>>> Why is the helper for a single-precision operation taking a 64-b
>From 6bb2ed5b7046cda545f6a12721b773fde40f07f1 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Mon, 5 Oct 2015 19:12:07 +0800
Subject: [PATCH] temp-floating-point: Use float32_to_t and t_to_float32 for
the input register value
Original implementation use int*_t
>From 4d12af14f361fb5e3a893fc68a599be9ea17d1dc Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 18:00:53 +0800
Subject: [PATCH] target-tilegx: Implement floating point temporarily
It is a temporary implementation, but it can pass gcc testsuite.
S
>From 418c1600c481f0acbde42987db286b48f1848399 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Fri, 2 Oct 2015 11:00:37 +0800
Subject: [PATCH v2] target-tilegx: Implement v?int_* instructions.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
>From be4b6be54c79d9ca22431f749f31e0c7b9fdd091 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Fri, 2 Oct 2015 09:19:56 +0800
Subject: [PATCH v2] target-tilegx: Implement v2sh* instructions
It is just according to v1sh* instructions implementation.
Signed-off
>From 0f53a45b3c29e3355cc6b2183ee084e62b86e5fe Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 13:34:33 +0800
Subject: [PATCH v2] target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and
TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly
For s
>From 298aa5e9be6373fea7b30236bd3e90352c6e693a Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sat, 3 Oct 2015 10:42:01 +0800
Subject: [PATCH v2] target-tilegx: Implement v2mults instruction
Just according to v1multu instruction implementation.
Signed-off-by:
>From 8e8d35fffd735df997c78324b301f22cf270b515 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:41:14 +0800
Subject: [PATCH v4] target-tilegx: Support iret instruction and related special
registers
Acording to the __longjmp tilegx libc imple
>From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:34:17 +0800
Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before
allocating dest temporary register
Or it will ca
and start tilegx qemu system mode, next.
Thanks
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
> From: xili_gchen_5...@hotmail.com
> To: r...@twiddle.net; peter.mayd...@linaro.org; cmetc...@ezchip.com
> CC: qe
Oh, sorry, also one modification about TILEGX_EXCP_OPCODE_UNIMPLEMENTED
left. I shall send patch v2 for it.
Thanks.
On 10/3/15 16:54, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> For some cases, they are for TILEGX_EXCP
S, 0, X0):
> +return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(V2MULTS, 0, X0):
> +gen_helper_v2mults(TDEST, tsrca, tsrcb);
> +mnemonic = "v2shl";
> +break;
> case OE_RRR(V2MZ, 0, X0):
> case OE_RRR(V2MZ, 0, X1):
>
On 10/1/15 10:29, Richard Henderson wrote:
> On 09/28/2015 11:51 PM, gang.chen.5...@gmail.com wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> At present, qemu x86_64 host backend can not remove the related dummy
>> instructions. Even the worse, sometime
Oh, sorry, when I sent this patch, I did not merge it to RTH's latest
patches. So this patch could not merge with RTH's patches.
If necessary to send patch v2, please let me know.
Thanks.
On 10/1/15 21:49, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
Oh, sorry, according to the architecture member's reply, this patch is
incorrect. I shall implement iret as "jrp lr".
Thanks.
On 10/1/15 19:01, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> Acording to the __longjmp tilegx libc impl
On 10/1/15 10:38, Richard Henderson wrote:
> I've taken the liberty of modifying some of the patches that Chen Gang
> has posted. Some of these are new cleanups that I saw along the way.
> A few are filling out the final user-level non-fp, non-vector insns.
>
Thank you very much f
ntire point of this iret path is to atomically branch
> and set INTERRUPT_CRITICAL_SECTION at the same time. So, this isn't complete.
>
OK, thanks.
> What INTERRUPT_CRITICAL_SECTION is supposed to *do* at user mode, I don't
> know.
>
Welcome any other members' ideas, suggestions and completions.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
ts (page fault, etc) cause a double-fault instead. ICS is
> automatically set on entry to interrupt handlers, so the handler has time to
> acquire any information about the interrupt from SPRs, and it is expected
> that ICS is cleared as soon as possible. ICS can also be used before
> returning from interrupts if you need to do something like adjust the
> interrupt mask prior to returning.
>
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
On 10/2/15 03:30, Richard Henderson wrote:
> On 10/01/2015 11:49 PM, gang.chen.5...@gmail.com wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> When a nop instruction is generated, but the 'dest' is a valid (e.g. for
>> any qemu skipped instructions, bu
On 9/29/15 14:34, Richard Henderson wrote:
> On 09/28/2015 03:06 PM, gang.chen.5...@gmail.com wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> Acording to the __longjmp tilegx libc implementation, and reference from
>> tilegx ISA document, we can left ir
On 9/27/15 19:48, Chen Gang wrote:
>
> After fix v1addi issue, try-pending will cause segment fault instead of
> abort, I shall continue analyzing try-pending issue, next.
>
After we check the zero dest register for ld insns, this issue can be
fixed -- at least, it is not tilegx's i
On 9/17/15 06:36, Chen Gang wrote:
>
>
> need analyzing (it is easy, I guess):
>
> mm: abort (origin has no issue)
> pcnt:abort (origin has no issue)
> v1addi: abort (origin has no issue)
>
After fix v1addi insn issue, the 3 a
On 9/27/15 00:06, Peter Maydell wrote:
> On 25 September 2015 at 21:10, <gang.chen.5...@gmail.com> wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> They content several new macro members, also contents TARGET_N*.
>>
>> Signe
DLI_OPCODE_X0, 0, X0):
>> case OE(ADDLI_OPCODE_X1, 0, X1):
>> -tcg_gen_addi_tl(tdest, tsrca, imm);
>> +if ((srca == TILEGX_R_ZERO) && (dest == TILEGX_R_ZERO)) {
>> +t0 = tcg_const_tl(imm & 0x);
>> +tcg_gen_st_tl(t0, cpu_env, offsetof(CPUTLGState, sigdata));
>> +tcg_temp_free(t0);
>> +} else {
>> +tcg_gen_addi_tl(tdest, tsrca, imm);
>> +}
>> mnemonic = "addli";
>> break;
>> case OE(ADDXLI_OPCODE_X0, 0, X0):
>>
>
> Certainly you should not be complicating addli like this.
>
OK, I'll try.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
On 9/22/15 22:45, Richard Henderson wrote:
> On 09/21/2015 10:54 PM, Chen Gang wrote:
>> On 2015年09月19日 10:34, Richard Henderson wrote:
>>>
>>> There's a trick for this that's more efficient for 4 or more elements
>>> per vector (i.e. good for v2 a
a - b = (a | 0x80808080) - (b & 0x7f7f7f7f)) ^ ((a ^ ~b) & 0x80808080)
>
For me, we need use "(a ^ b) & 0x80..." instead of "(a ^ ~b) & 0x80...".
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
The related code are changed, so this patch has to be reconstructed.
Thanks
On 9/22/15 06:26, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> Only according to v1shrs implementation.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com
Implement v*add and v*sub instructions
> Date: Tue, 22 Sep 2015 06:18:38 +0800
>
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> v4* are implemented in normal code, another are implemented in helper
> functions.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmai
;
> tcg_gen_concat_i32_i64(d64, al, ah);
>
> tcg_temp_free_i32(al);
> tcg_temp_free_i32(ah);
> tcg_temp_free_i32(bl);
> tcg_temp_free_i32(bh);
> }
>
>> case OE_RRR(V4ADD, 0, X0):
>> case OE_RRR(V4ADD, 0, X1):
>> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>> +gen_helper_v4add(tdest, tsrca, tsrcb);
>
> And then
>
> gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32);
>
OK, thanks. At least for me, what you said sounds reasonalbe.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
.
>
OK, thank you very much, I shall send patch v2 for it within the 2 days.
And sorry for replying late, (during this week end, I had to do some
personal things -- met some friends, and drunk).
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
andle v1shl, v1shru, v1shrs (2015-09-15 07:45:34 -0700)
>
>
> TileGX basic instructions
>
> ----
> Chen Gang (9):
> linux-user: tilegx: Add architecture related features
> linux-user: Support
On 9/15/15 23:04, Richard Henderson wrote:
[...]
> +/*
> + * QEMU TILE-Gx helpers
> + *
> + * Copyright (c) 2015 Chen Gang
This file is totally implemented by you, so I guess, the Copyright name
need be changed, too. :-)
> + *
> + * This library is free software; yo
On 9/15/15 23:03, Richard Henderson wrote:
[...]
> +/*
> + * QEMU TILE-Gx CPU
> + *
> + * Copyright (c) 2015 Chen Gang
> + *
Since you rewrite this file, I guess, the copyright name need be also
improved.
> + * This library is free software; you can redistribute it a
:abort (origin has no issue)
v1addi: abort (origin has no issue)
let analyzing easier:
try-pending: abort (origin causes pending).
I shall try to fix them, and send patches. Then continue gcc testsuite.
Thanks.
On 9/16/15 23:20, Chen Gang wrote:
>
> OK, thanks. I got them i
> CC: riku.voi...@iki.fi; r...@twiddle.net; xili_gchen_5...@hotmail.com;
> qemu-devel@nongnu.org
>
> On 15 September 2015 at 04:01, <gang.chen.5...@gmail.com> wrote:
> > From: Chen Gang <gang.chen.5...@gmail.com>
> >
> > After fix this issue, qemu can run i386
IGSEGV);
>> }
>
> Fallthrough into the sigsegv handler?
> That's clearly wrong.
>
OK, thanks. Need add "return" before "give_sigsegv". I shall send patch
v2 for it.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
On 9/13/15 00:23, Peter Maydell wrote:
> On 12 September 2015 at 16:32, <gang.chen.5...@gmail.com> wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> qemu has already considered about some targets may have no traditional
>> signals. And openri
From: peter.mayd...@linaro.org
> Date: Thu, 10 Sep 2015 10:02:27 +0100
>
> On 10 September 2015 at 06:43, <gang.chen.5...@gmail.com> wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> If qemu sets interp_prfix via command line '-L' instead of
hanged
> To: riku.voi...@iki.fi
> CC: r...@twiddle.net; peter.mayd...@linaro.org; qemu-devel@nongnu.org
> From: xili_gchen_5...@hotmail.com
> Date: Thu, 10 Sep 2015 13:49:18 +0800
>
> On 2015年09月10日 13:43, gang.chen.5...@gmail.com wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
tmail.com;
> qemu-devel@nongnu.org; gang.chen.5...@gmail.com
> Subject: [PATCH v2] linux-user/main.c: Set environments variables from
> command line options
> Date: Thu, 10 Sep 2015 16:10:22 +0800
>
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> When qemu execute ex
On 9/10/15 23:24, Peter Maydell wrote:
> On 10 September 2015 at 16:15, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>> Yes, we have to use binfmt_misc to let execve() run correctly. After
>> let execve() run correctly, I am analyzing another issue when let qemu
>>
:09, Chen Gang wrote:
>
> After download and merge the all related patches to my local qemu, for
> me:
>
> - The refactor code is really very good to me! :-)
>
> - It cause "hello world" test program "segment fault".
>
> Do we need fix all rel
On 9/10/15 20:35, Peter Maydell wrote:
> On 10 September 2015 at 10:32, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>>
>> For me, when users type a command line under Linux shell, they always
>> assume all related executions will know about their commands, they need
e and qemu work
together correctly.
Welcome any ideas, suggestions, and completions.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
On 2015年09月10日 13:43, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> If qemu sets interp_prfix via command line '-L' instead of environments
> variable QEMU_LD_PREFIX, it will cause syscall execve() failed. Because
> the 2nd qemu has no comm
Hello:
Could any members tell me whether he/she can receive the patches (patch
1/2, 2/2 for alpha-host) via my qq mail address?
It only seems OK, but I am not quite sure (really not sure).
Thanks.
On 8/31/15 17:17, Chen Gang wrote:
> On 2015年08月31日 16:59, gang.chen.5...@gmail.com wr
On 9/5/15 21:18, Max Filippov wrote:
> On Sat, Sep 5, 2015 at 1:18 PM, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>> Could any members tell me whether he/she can receive the patches (patch
>> 1/2, 2/2 for alpha-host) via my qq mail address?
>>
>> It only
On 9/3/15 22:53, Eric Blake wrote:
> On 09/02/2015 07:30 PM, Richard Henderson wrote:
>> From: Chen Gang <xili_gchen_5...@hotmail.com>
>
> s/Firstly add/Add/ in the subject line
>
Thank you for your careful notification. :-)
I guess, it will be modified by RTH, before
On 2015年08月31日 16:59, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> It is only for version merging, no any functional modification.
>
> Chen Gang (2):
> alpha-host: Add Alpha host tcg backend.
> alpha-host: Fix alpha host related me
merging, I shall continue to analyze tilegx gcc testsuite.
Thanks.
On 8/25/15 06:12, Chen Gang wrote:
On 8/25/15 00:17, Richard Henderson wrote:
I've flushed out the v13 I posted last Thursday to handle all the
instructions required to execute Hello World. In the process I
found a number of bugs
code into qemu
master, please let me know, I shall try, next.
- If it is necessary to provide related test programs, please let me
know, I shall provide them to.
Thanks.
On 8/29/15 21:19, Chen Gang wrote:
Is tilegx patches OK to qemu mater tree?
Or shall I do anything for it? If I
assumed all exceptions which can still let working flow continue are
all in pipe x1 (at present, it should be corret), so it is enough for us
to only process 1st exception of bundle.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Thanks.
--
Chen Gang
Open, share, and attitude like air, water
On 2015年08月19日 16:01, gchen gchen wrote:
On 2015年08月15日 04:45, Chen Gang wrote:
On 8/14/15 22:44, Richard Henderson wrote:
On 08/14/2015 02:37 AM, gchen gchen wrote:
- If I implement SW64 tcg backend, I guess, I cann't get help from qemu
upstream: I don't think SW64 is valuable enough
better, of course, would be to not exit the TB at all, and use host
atomic instructions... I suppose that multi-threading patch set is still in
limbo?
I guess, we need not.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
of the registers not
their numbers -- and delay the exception until after writeback.
Even better, of course, would be to not exit the TB at all, and use host
atomic instructions... I suppose that multi-threading patch set is still in
limbo?
I guess, we need not.
Thanks.
--
Chen Gang
Open
On 8/25/15 22:28, Richard Henderson wrote:
On 08/25/2015 06:12 AM, Chen Gang wrote:
Consider a bundle like
{ add r0, r0, r1 ; exch r2, r0, r3 }
In Chen's implementation, the writeback to r0 would occur before the
exception, and so the exch would happen to the wrong address. In my
with no register outputs.
OK, thank you for your work (originally, I really did not kown that it
would generate so many patches -- almost 3 times that I supposed).
Please review.
After this, I would hope that Chen Gang will follow up to implement
the rest of the instructions that he has identified running
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
linux-user
The related copy is from Linux kernel arch/tile/include/uapi/arch/
spr_def_64.h.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/spr_def_64.h | 216 +
1 file changed, 216
They are vectors, pcnt, revbytes, icoh, and drain.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c| 12 +-
target-tilegx/helper.h| 4 +-
target-tilegx/translate.c | 431 ++
3 files changed, 331 insertions(+), 116
The related instructions are exception, cntlz, cnttz, shufflebytes, and
add_saturate.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c | 83 ++
target-tilegx/helper.h | 5 +++
2 files changed, 88 insertions(+)
create
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
include/elf.h | 2
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/cpu.c | 143 ++
target-tilegx/cpu.h | 175
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
unsigned long long
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/opcode_tilegx.h | 220 +-
1 file changed, 110
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
linux-user/syscall.c | 50 +-
1 file changed
In fact, iret itself needs nothing, but the related previous and next
instructions need to be implemented.
SPR_EX_CONTEXT_0_0 and SPR_EX_CONTEXT_0_1 are related with iret, so let
them in a patch.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/cpu.h | 2 ++
target
The qemu errno is negative of normal errno, so revert it before return
from syscall, or the related user mode checking will fail, e.g. cp/mv
will call stat64 and check errno ENOENT (not -ENOENT).
Signed-of-by Chen Gang gang.chen.5...@gmail.com
---
linux-user/main.c | 2 +-
1 file changed, 1
the temporary implementation.
- There are still some instructions which are not implemented.
Chen Gang (16):
linux-user: tilegx: Firstly add architecture related features
linux-user: Support tilegx architecture in linux-user
linux-user/syscall.c: conditionalize syscalls which are not defined
Generate related tcg instructions, and qemu tilegx can finish running
Hello world. The elf64 binary can be static or shared.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/translate.c | 2966 +
1 file changed, 2966 insertions
It is copied from Linux kernel arch/tile/include/uapi/arch/
opcode_tilegx.h.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/opcode_tilegx.h | 1406 +
1 file changed, 1406 insertions
The interface of cpu_exec and cpu_exec_init are changed, so qemu tilegx
should match with them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/main.c | 2 +-
target-tilegx/cpu.c | 2 +-
target-tilegx/cpu.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
On 8/18/15 22:32, Peter Maydell wrote:
On 18 August 2015 at 15:27, Chen Gang xili_gchen_5...@hotmail.com wrote:
Welcome any ideas, suggestions and completions.
You should stop working on adding new features and instructions,
and concentrate on getting a coherent set of patches for some
OK, thanks. What you said sounds reasonable to me. I shall try to send
patches to qemu, firstly.
:-)
On 8/19/15 06:15, Peter Maydell wrote:
On 18 August 2015 at 22:29, Chen Gang xili_gchen_5...@hotmail.com wrote:
On 8/18/15 22:32, Peter Maydell wrote:
On 18 August 2015 at 15:27, Chen Gang
bug under bugzilla, but until now,
I do nothing for it (it is really delayed quite too much).
Welcome any ideas, suggestions and completions.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
On 8/18/15 01:31, Richard Henderson wrote:
On 08/15/2015 11:16 AM, Chen Gang wrote:
But what you said is really quite valuable to me!! we can treat the flag
as a caller saved context, then can let the caller can use callee freely
(in fact, I guess, the real hardware treats it as caller
On 8/16/15 09:41, Chen Gang wrote:
On 8/16/15 02:16, Chen Gang wrote:
On 8/15/15 23:47, Richard Henderson wrote:
On Aug 15, 2015 2:56 AM, Chen Gang xili_gchen_5...@hotmail.com
Oh, we are unlucky, after continue gcc testsuite, add/sub floating point
insns also can be mixed together
On 8/16/15 02:16, Chen Gang wrote:
On 8/15/15 23:47, Richard Henderson wrote:
On Aug 15, 2015 2:56 AM, Chen Gang xili_gchen_5...@hotmail.com
Oh, we are unlucky, after continue gcc testsuite, add/sub floating point
insns also can be mixed together! The related C code, -save-temps
On 8/13/15 22:59, Chen Gang wrote:
Hello all:
For me, I guess for single insns, they are simple, and each calculation
insns group can not be mixed with each other. So current implementation
should be OK.
For double insns, I guess, only mul calculation can be mixed with other
calculation
On 8/15/15 23:47, Richard Henderson wrote:
On Aug 15, 2015 2:56 AM, Chen Gang xili_gchen_5...@hotmail.com
Oh, we are unlucky, after continue gcc testsuite, add/sub floating point
insns also can be mixed together! The related C code, -save-temps, and
objdump files are in attachments
.
If possible, it will be better to merge the alpha tcg backend to qemu
master main branch (at least for me, it is useful).
:-)
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
* pack srca dest (dest is orig srcb of pack1)
* reference from tilegx.md: float(uns)sidf2.
* get (u)int32_t a, then (u)int32_to_float64.
* else
* skipped.
*/
On 8/11/15 21:18, Chen Gang
r3, r13, r16
...
Welcome any additional ideas, suggestions and completions.
Thanks.
On 8/9/15 09:14, Chen Gang wrote:
On 8/9/15 09:10, Chen Gang wrote:
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise
,
e.g gcc testsuit for complex number).
Next, I shall implement the floating point insns, welcome any related
ideas, suggestions, and completions.
Thanks.
On 8/5/15 22:16, Chen Gang wrote:
On 8/4/15 23:04, Richard Henderson wrote:
On 08/04/2015 06:56 AM, Chen Gang wrote:
On 8/4/15 04:47, Chen
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used individually:
fsingle_add1
On 8/9/15 09:10, Chen Gang wrote:
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used
On 8/4/15 23:04, Richard Henderson wrote:
On 08/04/2015 06:56 AM, Chen Gang wrote:
On 8/4/15 04:47, Chen Gang wrote:
On 8/4/15 00:40, Richard Henderson wrote:
On 08/01/2015 02:47 AM, Chen Gang wrote:
I am just adding floating point instructions (e.g. fsingle_add1),
but for me, I can
On 8/4/15 04:47, Chen Gang wrote:
On 8/4/15 00:40, Richard Henderson wrote:
On 08/01/2015 02:47 AM, Chen Gang wrote:
I am just adding floating point instructions (e.g. fsingle_add1),
but for me, I can not find any details about them (the ISA
documents only give a summary description
101 - 200 of 614 matches
Mail list logo
