Thanks for the response.
I don't think section 3.1 applies to 8-bit accesses. That is
specifically about reserved locations, and neither offset 0x38 nor 0x39
are reserved, so I think it's a matter of whether 32-bit access is
required or not.
>From what I usually see in ARM documentation, 32-bit a
Adding the link script.
** Attachment added: "linkscript.ld"
https://bugs.launchpad.net/qemu/+bug/1809546/+attachment/5224337/+files/linkscript.ld
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https://bugs.launchpad.net/bugs/18
Public bug reported:
The bug is present in QEMU 2.8.1 and, if my analysis is correct, also on
master.
I first noticed that a PL011 UART driver, which is fine on real
hardware, fails to enable the RX interrupt in the IMSC register when
running in QEMU. However, the problem only comes up if the cod
