[Qemu-devel] [V17 0/4] AMD IOMMU

. David Kiarie (4): hw/pci: Prepare for AMD IOMMU hw/i386/trace-events: Add AMD IOMMU trace events hw/i386: Introduce AMD IOMMU hw/i386: AMD IOMMU IVRS table hw/acpi/aml-build.c |2 +- hw/i386/Makefile.objs |1 + hw/i386/acpi-build.c| 76 ++- hw/i386

Re: [Qemu-devel] [V2 0/6] AMD IOMMU interrupt remapping

On Mon, Aug 15, 2016 at 7:32 PM, David Kiarie <davidkiar...@gmail.com> wrote: > Hello all, > > The following patchset implements AMD-Vi interrupt remapping logic and > hooks it onto existing IR infrastucture. > > I have bundled this patchset together with the "Explici

[Qemu-devel] [V2 4/6] hw/iommu: AMD IOMMU interrupt remapping

Introduce AMD IOMMU interrupt remapping and hook it onto the existing interrupt remapping infrastructure Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/amd_iommu.c | 244 +++- hw/i386/amd_iommu.h | 4 +- 2 files change

[Qemu-devel] [V2 5/6] hw/acpi: report IOAPIC on IVRS

Report IOAPIC via IVRS which effectively allows linux AMD-Vi driver to enable interrupt remapping Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/acpi-build.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 49bd183..c

[Qemu-devel] [V2 2/6] hw/i386: enforce SID verification

Platform device are now able to make interrupt request with explicit SIDs hence we can safely expect triggered AddressSpace ID to match the requesting ID Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/intel_iommu.c | 77 ++--

[Qemu-devel] [V2 6/6] hw/iommu: share common code between IOMMUs

Enabling interrupt remapping with kernel_irqchip=on should result in an error for both VT-d and AMD-Vi Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/intel_iommu.c | 9 - hw/i386/x86-iommu.c | 8 2 files changed, 8 insertions(+), 9 deletions(-) diff

[Qemu-devel] [V2 0/6] AMD IOMMU interrupt remapping

ID and a PCI device if present which enables platform devices like IOAPIC to make interrupt requests using an explicit SID as required by both VT-d and AMD-Vi. David Kiarie (6): hw/msi: Allow platform devices to use explicit SID hw/i386: enforce SID verification hw/iommu: Prepare for

[Qemu-devel] [V2 1/6] hw/msi: Allow platform devices to use explicit SID

maintaining compatility with the original code which mainly dealt with PCI devices. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/intel_iommu.c | 3 +++ hw/i386/kvm/pci-assign.c | 12 hw/intc/ioapic.c | 25 +--

[Qemu-devel] [V2 3/6] hw/iommu: Prepare for AMD IOMMU interrupt remapping

Introduce macros and trace events for use in AMD IOMMU interrupt remapping Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/amd_iommu.h | 38 -- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/hw/i386/amd_iommu.h b/h

[Qemu-devel] [V16 3/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V16 1/4] hw/pci: Prepare for AMD IOMMU

Introduce PCI macros from for use by AMD IOMMU Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- include/hw/pci/pci.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 929ec2f..5ff92de 100644 --- a/include/hw/pci

[Qemu-devel] [V16 2/4] hw/i386/trace-events: Add AMD IOMMU trace events

Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/trace-events | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index b4882c1..592de3a 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@

[Qemu-devel] [V16 0/4] AMD IOMMU

but to the 'host' (l1 guest). You can still go ahead pass command line parameter 'iommu=pt iommu=1' and try to pass a device to L2 guest. This can also done without passing any iommu related parameters to the kernel. David Kiarie (4): hw/pci: Prepare for AMD IOMMU hw/i386/trace-events: Add AMD IOMMU trace

Re: [Qemu-devel] [V1 2/4] hw/iommu: AMD IOMMU interrupt remapping

On Fri, Aug 12, 2016 at 11:08 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > On 11.08.2016 00:42, David Kiarie wrote: > >> Introduce AMD IOMMU interrupt remapping and hook it onto > > >> +static inline int amdvi_ir_pass(MSIMessage *src, M

Re: [Qemu-devel] [V1 3/4] hw/acpi: report IOAPIC on IVRS

On Fri, Aug 12, 2016 at 11:14 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > On 11.08.2016 00:42, David Kiarie wrote: > >> Report IOAPIC via IVRS which effectively allows linux AMD-Vi >> driver to enable interrupt remapping >> >> Si

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Fri, Aug 12, 2016 at 10:10 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi David, > > On 02.08.2016 13:39, David Kiarie wrote: > >> Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. >> The IOMMU does basic translation, error check

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Thu, Aug 11, 2016 at 11:23 AM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi, > > > On 02.08.2016 13:39, David Kiarie wrote: > >> +static void amdvi_writeq_raw(AMDVIState *s, uint64_t val, hwaddr addr) >> +{+ >> +static void amd

Re: [Qemu-devel] [V1 0/4] AMD-Vi Interrupt Remapping

On Thu, Aug 11, 2016 at 9:39 AM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi David, > > On 11.08.2016 00:42, David Kiarie wrote: > >> Hello all, >> >> The following patchset adds AMD-Vi interrupt remapping logic >> to Qemu and

[Qemu-devel] [V1 2/4] hw/iommu: AMD IOMMU interrupt remapping

Introduce AMD IOMMU interrupt remapping and hook it onto the existing interrupt remapping infrastructure Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/amd_iommu.c | 226 +++- hw/i386/amd_iommu.h | 2 + 2 files change

[Qemu-devel] [V1 4/4] hw/iommu: share common between IOMMUs

Enabling interrupt remapping with kernel_irqchip=on should result in error for both VT-d and AMD-Vi Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/intel_iommu.c | 9 - hw/i386/x86-iommu.c | 8 2 files changed, 8 insertions(+), 9 deletions(-) diff --gi

Re: [Qemu-devel] [V1 0/4] AMD-Vi Interrupt Remapping

On Wed, Aug 10, 2016 at 10:42 PM, David Kiarie <davidkiar...@gmail.com> wrote: Sorry, forgot to cc Peter. Hello all, > > The following patchset adds AMD-Vi interrupt remapping logic > to Qemu and hooks it onto existing interrupt remapping infrastructure.It > has > a depend

[Qemu-devel] [V1 3/4] hw/acpi: report IOAPIC on IVRS

Report IOAPIC via IVRS which effectively allows linux AMD-Vi driver to enable interrupt remapping Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/acpi-build.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 49bd183..d

[Qemu-devel] [V1 1/4] hw/iommu: Prepare for AMD IOMMU interrupt remapping

Introduce macros and trace events for use in AMD IOMMU interrupt remapping Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/amd_iommu.h | 72 hw/i386/trace-events | 7 + 2 files changed, 79 insertions(+) diff --gi

[Qemu-devel] [V1 0/4] AMD-Vi Interrupt Remapping

aq/qemu IR David Kiarie (4): hw/iommu: Prepare for AMD IOMMU interrupt remapping hw/iommu: AMD IOMMU interrupt remapping hw/acpi: report IOAPIC on IVRS hw/iommu: share common between IOMMUs hw/i386/acpi-build.c | 2 + hw/i386/amd_iommu

Re: [Qemu-devel] [V15 0/4] AMD IOMMU

On Tue, Aug 9, 2016 at 11:27 PM, David Kiarie <davidkiar...@gmail.com> wrote: > Hi all, > > This patchset adds basic AMD IOMMU emulation support to Qemu. > > Change since v14 >-MMIO register reading/write bug fix [Peter] >-Endian-ness issue fix[Peter] >

Re: [Qemu-devel] [RFC 1/2] hw/msi: Allow platform devices to use explicit SID

On Wed, Aug 10, 2016 at 8:41 AM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 09, 2016 at 05:32:16PM +0300, David Kiarie wrote: > > When using IOMMU platform devices like IOAPIC are required to make > > interrupt remapping requests using explicit SID.We affil

Re: [Qemu-devel] [RFC 2/2] hw/i386: enforce SID verification

On Wed, Aug 10, 2016 at 8:49 AM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 09, 2016 at 05:32:17PM +0300, David Kiarie wrote: > > [...] > > > @@ -2252,14 +2250,17 @@ static MemTxResult vtd_mem_ir_write(void > *opaque, hwaddr addr, > > { > >

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Wed, Aug 10, 2016 at 5:08 AM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 09, 2016 at 03:52:07PM +0300, David Kiarie wrote: > > [...] > > > > > +if (dma_memory_write(_space_memory, s->evtlog_len + > > > s->evtlog_tail, > > &

[Qemu-devel] [V15 2/4] hw/i386/trace-events: Add AMD IOMMU trace events

Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/trace-events | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index b4882c1..592de3a 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@

[Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V15 1/4] hw/pci: Prepare for AMD IOMMU

Introduce PCI macros from for use by AMD IOMMU Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- include/hw/pci/pci.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 929ec2f..5ff92de 100644 --- a/include/hw/pci

[Qemu-devel] [V15 0/4] AMD IOMMU

. This can also done without passing any iommu related parameters to the kernel. David Kiarie (4): hw/pci: Prepare for AMD IOMMU hw/i386/trace-events: Add AMD IOMMU trace events hw/i386: Introduce AMD IOMMU hw/i386: AMD IOMMU IVRS table hw/acpi/aml-build.c |2 +- hw/i386

Re: [Qemu-devel] [RFC 2/2] hw/i386: enforce SID verification

On Tue, Aug 9, 2016 at 9:41 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > > > On 09.08.2016 19:32, David Kiarie wrote: > >> Platform device are now able to make interrupt request with >> explicit SIDs hence we can safely expect trigger

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > [...] > > > +/* external write */ > > +static void amdvi_writew(AMDVIState *s, hwaddr addr, uint16_t val) > > +{ > >

[Qemu-devel] [RFC 2/2] hw/i386: enforce SID verification

Platform device are now able to make interrupt request with explicit SIDs hence we can safely expect triggered AddressSpace ID to match the requesting ID Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/intel_iommu.c | 82 +++-

[Qemu-devel] [RFC 0/2] Explicit SID for IOAPIC

effects as far as I can tell. David Kiarie (2): hw/msi: Allow platform devices to use explicit SID hw/i386: enforce SID verification hw/i386/intel_iommu.c | 82 --- hw/i386/kvm/pci-assign.c | 12 -- hw/intc/ioapic.c

[Qemu-devel] [RFC 1/2] hw/msi: Allow platform devices to use explicit SID

maintaining compatility with the original code which mainly dealt with PCI devices. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/kvm/pci-assign.c | 12 hw/intc/ioapic.c | 28 hw/misc/ivshmem.c

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 4:01 PM, Valentine Sinitsyn < valentine.sinit...@gmail.com> wrote: > Hi all, > > On 09.08.2016 17:52, David Kiarie wrote: > >> >> >> On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu <pet...@redhat.com >> <mailto:pet...@redhat.com&

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > [...] > > > +/* invalidate internal caches for devid */ > > +typedef struct QEMU_PACKED { > > +#ifdef HOST_WOR

Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote: > > [...] > > Hi Peter. Most of your comments are valid thought some are subjective :-). I'm covering most if not all of them on next version (

Re: [Qemu-devel] [PULL v5 29/57] intel_iommu: add SID validation for IR

On Mon, Aug 8, 2016 at 12:06 PM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 02, 2016 at 03:17:20PM +0300, David Kiarie wrote: > > On Tue, Aug 2, 2016 at 3:12 PM, Peter Xu <pet...@redhat.com> wrote: > > > > > On Tue, Aug 02, 2016 at 02:58:55PM +0300

Re: [Qemu-devel] [V15 1/4] hw/pci: Prepare for AMD IOMMU

On Mon, Aug 8, 2016 at 12:01 PM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 02, 2016 at 11:39:04AM +0300, David Kiarie wrote: > > Introduce PCI macros from for use by AMD IOMMU > > > > Signed-off-by: David Kiarie <davidkiar...@gmail.com> > > --- >

Re: [Qemu-devel] [PULL v5 29/57] intel_iommu: add SID validation for IR

On Tue, Aug 2, 2016 at 3:16 PM, Jan Kiszka <jan.kis...@siemens.com> wrote: > On 2016-08-02 13:58, David Kiarie wrote: > > > > > > On Tue, Aug 2, 2016 at 1:28 PM, Peter Xu <pet...@redhat.com > > <mailto:pet...@redhat.com>> wrote: > > > >

Re: [Qemu-devel] [PULL v5 29/57] intel_iommu: add SID validation for IR

On Tue, Aug 2, 2016 at 3:12 PM, Peter Xu <pet...@redhat.com> wrote: > On Tue, Aug 02, 2016 at 02:58:55PM +0300, David Kiarie wrote: > > > Sure. David, so do you like to do it or I cook this patch? :) > > > > If there are no objections I will look at this employing J

Re: [Qemu-devel] [PULL v5 29/57] intel_iommu: add SID validation for IR

On Tue, Aug 2, 2016 at 1:28 PM, Peter Xu wrote: > On Tue, Aug 02, 2016 at 10:46:13AM +0200, Jan Kiszka wrote: > > On 2016-08-02 10:36, Peter Xu wrote: > > > On Mon, Aug 01, 2016 at 06:39:05PM +0200, Jan Kiszka wrote: > > > > > > [...] > > > > > >>> static MemTxResult

[Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V15 2/4] hw/i386/trace-events: Add AMD IOMMU trace events

Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/trace-events | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index b4882c1..592de3a 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@

[Qemu-devel] [V15 1/4] hw/pci: Prepare for AMD IOMMU

Introduce PCI macros from for use by AMD IOMMU Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- include/hw/pci/pci.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 929ec2f..d47e0e6 100644 --- a/include/

[Qemu-devel] [V15 4/4] hw/i386: AMD IOMMU IVRS table

Add IVRS table for AMD IOMMU. Generate IVRS or DMAR depending on emulated IOMMU. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/acpi/aml-build.c | 2 +- hw/i386/acpi-build.c| 76 - hw/i386/x86-iommu.c

[Qemu-devel] [V15 0/4] AMD IOMMU

are basically passes-through but to the 'host' (l1 guest). You can still go ahead pass command line parameter 'iommu=pt iommu=1' and try to pass a device to L2 guest. This can also done without passing any iommu related parameters to the kernel. David Kiarie (4): hw/pci: Prepare for AMD IOMMU hw

[Qemu-devel] Question on Qemu IOAPIC ID

Hello all, I, working on AMD IOMMU interrupt remapping would like to ask some questions on Qemu IOAPIC id. I currently have a problem in that Linux AMD IOMMU driver expects at least one IOAPIC on the chipset to have ID 0xa0 while Qemu IOAPIC id is always 0. I am faced with two options -Change

Re: [Qemu-devel] [PATCH v11 14/28] intel_iommu: Add support for PCI MSI remap

On Tue, Jul 5, 2016 at 11:19 AM, Peter Xu wrote: > This patch enables interrupt remapping for PCI devices. > > To play the trick, one memory region "iommu_ir" is added as child region > of the original iommu memory region, covering range 0xfeeX (which is > the address range

Re: [Qemu-devel] [PATCH v10 27/26] intel_iommu: disallow kernel-irqchip=on with IR

On Fri, Jun 24, 2016 at 10:10 AM, Peter Xu wrote: > When user specify "kernel-irqchip=on", throw error and then quit. > > Signed-off-by: Peter Xu > --- > > One more patch for this series. Without this one, guest kernel will > possibly hang. This is not user

Re: [Qemu-devel] [PATCH v11 04/28] x86-iommu: q35: generalize find_add_as()

On Mon, Jul 11, 2016 at 9:49 AM, Peter Xu <pet...@redhat.com> wrote: > On Mon, Jul 11, 2016 at 08:46:12AM +0300, David Kiarie wrote: >> On Mon, Jul 11, 2016 at 8:32 AM, Peter Xu <pet...@redhat.com> wrote: >> > On Sat, Jul 09, 2016 at 10:14:48AM +0200, Jan Kiszka wr

Re: [Qemu-devel] [V13 3/4] hw/i386: Introduce AMD IOMMU

On Fri, Jul 8, 2016 at 7:30 PM, Alex Williamson <alex.william...@redhat.com> wrote: > On Fri, 8 Jul 2016 11:18:22 +0300 > David Kiarie <davidkiar...@gmail.com> wrote: > >> Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU. >> The IOMMU does basic tr

Re: [Qemu-devel] [PATCH v11 04/28] x86-iommu: q35: generalize find_add_as()

On Mon, Jul 11, 2016 at 8:32 AM, Peter Xu wrote: > On Sat, Jul 09, 2016 at 10:14:48AM +0200, Jan Kiszka wrote: >> On 2016-07-05 10:19, Peter Xu wrote: >> > Remove VT-d calls in common q35 codes. Instead, we provide a general >> > find_add_as() for x86-iommu type. >> > >> >

[Qemu-devel] [V13 2/4] hw/i386/trace-events: Add AMD IOMMU trace events

Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/trace-events | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ea77bc2..a2f529e 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@

[Qemu-devel] [V13 3/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V13 1/4] hw/pci: Prepare for AMD IOMMU

Introduce PCI macros from for use by AMD IOMMU Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- include/hw/pci/pci.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 9ed1624..959d05b 100644 --- a/include/

[Qemu-devel] [V13 0/4] AMD IOMMU

to the kernel. David Kiarie (4): hw/pci: Prepare for AMD IOMMU hw/i386/trace-events: Add AMD IOMMU trace events hw/i386: Introduce AMD IOMMU hw/i386: AMD IOMMU IVRS table hw/acpi/aml-build.c |2 +- hw/i386/Makefile.objs |1 + hw/i386/acpi-build.c| 102 +++- hw/i386

Re: [Qemu-devel] [V12 4/4] hw/i386: AMD IOMMU IVRS table

On Mon, Jul 4, 2016 at 11:33 PM, Michael S. Tsirkin <m...@redhat.com> wrote: > On Wed, Jun 15, 2016 at 03:21:52PM +0300, David Kiarie wrote: >> Add IVRS table for AMD IOMMU. Generate IVRS or DMAR >> depending on emulated IOMMU. >> >> Signed-off-by: Dav

Re: [Qemu-devel] [V12 3/4] hw/i386: Introduce AMD IOMMU

On Mon, Jul 4, 2016 at 8:41 AM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2016-07-04 07:06, David Kiarie wrote: >> On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka <jan.kis...@web.de> wrote: >>> On 2016-06-15 14:21, David Kiarie wrote: >>>> + >>

Re: [Qemu-devel] [V12 3/4] hw/i386: Introduce AMD IOMMU

On Mon, Jul 4, 2016 at 8:41 AM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2016-07-04 07:06, David Kiarie wrote: >> On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka <jan.kis...@web.de> wrote: >>> On 2016-06-15 14:21, David Kiarie wrote: >>>> +static uint64_t

Re: [Qemu-devel] [V12 3/4] hw/i386: Introduce AMD IOMMU

On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2016-06-15 14:21, David Kiarie wrote: >> + >> +/* System Software might never read from some of this fields but anyways */ > > No read-modify-write accesses observed in the field? And fiel

Re: [Qemu-devel] [V11 2/4] hw/i386: ACPI IVRS table

On Tue, May 24, 2016 at 10:06 AM, Valentine Sinitsyn <valentine.sinit...@gmail.com> wrote: > Hi all, > > > On 24.05.2016 11:54, Peter Xu wrote: >> >> On Sun, May 22, 2016 at 01:21:52PM +0300, David Kiarie wrote: >> [...] >>> >>> +static void &

Re: [Qemu-devel] [V12 0/4] AMD IOMMU

On Wed, Jun 15, 2016 at 5:26 PM, Eduardo Habkost <ehabk...@redhat.com> wrote: > On Wed, Jun 15, 2016 at 03:21:48PM +0300, David Kiarie wrote: >> Hi all, >> >> This patchset adds basic AMD IOMMU emulation support to Qemu. >> >> Changes since V11 >>

[Qemu-devel] [V12 3/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We also advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V12 1/4] hw/pci: Prepare for AMD IOMMU

Introduce PCI macros from linux headers for use by AMD IOMMU Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- include/hw/pci/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 4420f47..ac376c5 100644 --- a/include/hw/pci

[Qemu-devel] [V12 0/4] AMD IOMMU

guest. This can also done without passing any iommu related parameters to the kernel. For convinience: [1] https://github.com/aslaq/qemu/tree/v12 David Kiarie (4): hw/pci: Prepare for AMD IOMMU trace-events: Add AMD IOMMU trace events hw/i386: Introduce AMD IOMMU hw/i386: AMD IOMMU IVRS

[Qemu-devel] [V12 2/4] trace-events: Add AMD IOMMU trace events

Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- trace-events | 29 + 1 file changed, 29 insertions(+) diff --git a/trace-events b/trace-events index 2f14205..340d019 100644 --- a/trace-events +++ b/trace-events @@ -2164,3 +2164,32 @@ e1000e_cfg_support_

Re: [Qemu-devel] [RFC] hw/i386: Composite Bus and PCI device

On Fri, Jun 10, 2016 at 8:30 AM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2016-06-08 17:25, Eduardo Habkost wrote: >> On Wed, Jun 08, 2016 at 01:00:32PM +0300, David Kiarie wrote: >>> Sample composite SysBus and PCI device similar to AMD IOMMU setup >>> >>&

Re: [Qemu-devel] [RFC] Allow AMD IOMMU to have both SysBusDevice and PCIDevice properties.

On Thu, Jun 9, 2016 at 4:23 PM, Marcel Apfelbaum wrote: > On 06/07/2016 10:12 PM, Eduardo Habkost wrote: >> >> Hi, >> > > [...] > >> [...] >>> >>> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c >>> index 04aae89..431eaed 100644 >>> --- a/hw/i386/pc_q35.c >>> +++

[Qemu-devel] [RFC] AMD IOMMU: emulate multiple devices

/gmane.comp.emulators.qemu/413018 David Kiarie (1): hw/i386: Composite Bus and PCI device hw/i386/compositedevice.c | 113 ++ 1 file changed, 113 insertions(+) create mode 100644 hw/i386/compositedevice.c -- 2.1.4

[Qemu-devel] [RFC] hw/i386: Composite Bus and PCI device

Sample composite SysBus and PCI device similar to AMD IOMMU setup Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/i386/compositedevice.c | 113 ++ 1 file changed, 113 insertions(+) create mode 100644 hw/i386/compositedevice.c diff

Re: [Qemu-devel] [RFC] Allow AMD IOMMU to have both SysBusDevice and PCIDevice properties.

. > > On Sun, Jun 05, 2016 at 07:54:33PM +0300, David Kiarie wrote: >> Signed-off-by: David Kiarie <davidkiar...@gmail.com> >> --- >> hw/acpi/aml-build.c |2 +- >> hw/i386/amd_iommu.c | 1471 >>

[Qemu-devel] [RFC] Allow AMD IOMMU to have both SysBusDevice and PCIDevice properties.

Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/acpi/aml-build.c |2 +- hw/i386/amd_iommu.c | 1471 +++ hw/i386/amd_iommu.h | 348 ++ hw/i386/kvm/pci-assign.c|2 +- hw/i386/pc_q35.c

[Qemu-devel] [RFC] AMD IOMMU: emulate multiple devices

in this patch and review the design. Also, some of the changes here are not related to the above issue. Looking forward to your comments! David Kiarie (1): Allow AMD IOMMU to have both SysBusDevice and PCIDevice properties. hw/acpi/aml-build.c |2 +- hw/i386/amd_iommu.c

Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR

On Mon, May 30, 2016 at 12:16 PM, Peter Xu <pet...@redhat.com> wrote: > On Mon, May 30, 2016 at 11:54:52AM +0300, David Kiarie wrote: >> On Mon, May 30, 2016 at 11:14 AM, Peter Xu <pet...@redhat.com> wrote: >> > On Mon, May 30, 2016 at 07:56:16AM +0200, Jan Kiszka wr

Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR

On Mon, May 30, 2016 at 11:14 AM, Peter Xu <pet...@redhat.com> wrote: > On Mon, May 30, 2016 at 07:56:16AM +0200, Jan Kiszka wrote: >> On 2016-05-30 07:45, Peter Xu wrote: >> > On Sun, May 29, 2016 at 11:21:35AM +0300, David Kiarie wrote: >> > [...] >> >&g

Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR

On Sun, May 29, 2016 at 11:20 AM, David Kiarie <davidkiar...@gmail.com> wrote: > On Tue, May 17, 2016 at 10:15 AM, Peter Xu <pet...@redhat.com> wrote: >> Several data structs are defined to better support the rest of the >> patches: IRTE to parse remapping table entr

Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR

On Tue, May 17, 2016 at 10:15 AM, Peter Xu wrote: > Several data structs are defined to better support the rest of the > patches: IRTE to parse remapping table entries, and IOAPIC/MSI related > structure bits to parse interrupt entries to be filled in by guest > kernel. > >

Re: [Qemu-devel] [V11 1/4] hw/i386: Introduce AMD IOMMU

On Tue, May 24, 2016 at 3:35 PM, Peter Xu <pet...@redhat.com> wrote: > On Sun, May 22, 2016 at 01:21:51PM +0300, David Kiarie wrote: > > [...] > >> +#define DEBUG_AMD_AMDVI >> +#ifdef DEBUG_AMD_AMDVI >> +enum { >> +DEBUG_GENERAL, DEBUG_CAPAB, D

Re: [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class

On Tue, May 24, 2016 at 2:02 PM, David Kiarie <davidkiar...@gmail.com> wrote: > On Tue, May 24, 2016 at 1:40 PM, Jan Kiszka <jan.kis...@web.de> wrote: >> On 2016-05-23 23:48, Marcel Apfelbaum wrote: >>> On 05/23/2016 08:06 PM, David Kiarie wrote: >>>>

Re: [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class

On Tue, May 24, 2016 at 1:40 PM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2016-05-23 23:48, Marcel Apfelbaum wrote: >> On 05/23/2016 08:06 PM, David Kiarie wrote: >>> On Tue, May 17, 2016 at 10:15 AM, Peter Xu <pet...@redhat.com> wrote: >>>> Introducing

Re: [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class

On Tue, May 17, 2016 at 10:15 AM, Peter Xu wrote: > Introducing parent class for intel-iommu devices named "x86-iommu". This > is preparation work to abstract shared functionalities out from Intel > and AMD IOMMUs. Currently, only the parent class is introduced. It does >

[Qemu-devel] GSoC 2016: Student Introduction

Hello, My name is David Kiarie. I am a student who has been selected to work with Qemu as part of GSoC. My project entails completing the current AMD IOMMU implementation work (getting the current patches merged) and adding interrupt remapping. I will also try to add more features if time allows

[Qemu-devel] [V11 3/4] hw/core: provision for overriding emulated IOMMU

Added an enum, subject to review, to machine properties which it used to override iommu emulated from Intel to AMD. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/core/machine.c | 29 ++--- include/hw/boards.h | 1 + include/h

[Qemu-devel] [V11 4/4] hw/pci-host: Emulate AMD IOMMU

Add AMD IOMMU emulation support to q35 chipset Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/pci-host/q35.c | 25 ++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 70f897e..26fea0e 100644 --

[Qemu-devel] [V11 2/4] hw/i386: ACPI IVRS table

Add IVRS table for AMD IOMMU. Generate IVRS or DMAR depending on emulated IOMMU. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/acpi/aml-build.c | 2 +- hw/i386/acpi-build.c| 93 +++-- include/hw/acpi/acpi-defs.

[Qemu-devel] [V11 1/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We also advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V11 0/4] AMD IOMMU

parameter 'iommu=pt iommu=1' and try to pass a device to L2 guest. This can also done without passing any iommu related parameters to the kernel. David Kiarie (4): hw/i386: Introduce AMD IOMMU hw/i386: ACPI IVRS table hw/core: provision for overriding emulated IOMMU hw/pci-host: Emulate

Re: [Qemu-devel] [V10 1/4] hw/i386: Introduce AMD IOMMU

On Sun, May 15, 2016 at 10:29 PM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2016-05-09 14:15, David Kiarie wrote: >> + Thanks for review and testing! >> +/* go to the next lower level */ >> +pte_addr = pte & AMDVI_DEV_PT_ROOT_MASK; >>

[Qemu-devel] [V10 4/4] hw/pci-host: Emulate AMD IOMMU

Add AMD IOMMU emulation support to q35 chipset Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/pci-host/q35.c | 25 ++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 70f897e..26fea0e 100644 --

[Qemu-devel] [V10 1/4] hw/i386: Introduce AMD IOMMU

translation as it is the q35 interrupt region. We also advertise features that are not yet implemented to please the Linux IOMMU driver. IOTLB aims at implementing commands on real IOMMUs which is essential for debugging and may not offer any performance benefits. Signed-off-by: David Kiarie <davidk

[Qemu-devel] [V10 2/4] hw/i386: ACPI IVRS table

Add IVRS table for AMD IOMMU. Generate IVRS or DMAR depending on emulated IOMMU. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/acpi/aml-build.c | 2 +- hw/i386/acpi-build.c| 93 +++-- include/hw/acpi/acpi-defs.

[Qemu-devel] [V10 3/4] hw/core: provision for overriding emulated IOMMU

Added an enum, subject to review, to machine properties which it used to override iommu emulated from Intel to AMD. Signed-off-by: David Kiarie <davidkiar...@gmail.com> --- hw/core/machine.c | 29 ++--- include/hw/boards.h | 1 + include/h

[Qemu-devel] [V10 0/4] AMD IOMMU

a device to L2 guest. This can also done without passing any iommu related parameters to the kernel. David Kiarie (4): hw/i386: Introduce AMD IOMMU hw/i386: ACPI IVRS table hw/core: provision for overriding emulated IOMMU hw/pci-host: Emulate AMD IOMMU hw/acpi/aml-build.c |2

Re: [Qemu-devel] [V9 0/4] AMD IOMMU

On Wed, May 4, 2016 at 2:05 PM, Valentine Sinitsyn <valentine.sinit...@gmail.com> wrote: > On 04.05.2016 16:02, David Kiarie wrote: >> >> >> >> On 04/05/16 13:58, Valentine Sinitsyn wrote: >>> >>> On 04.05.2016 15:51, David Kiarie wrote: &

Re: [Qemu-devel] [PATCH v6 08/26] intel_iommu: provide helper function vtd_get_iommu

On Thu, May 5, 2016 at 6:25 AM, Peter Xu wrote: > Moves acpi_get_iommu() under VT-d to make it a public function. > > Signed-off-by: Peter Xu > --- > hw/i386/acpi-build.c | 7 +-- > hw/i386/intel_iommu.c | 13 + >

Re: [Qemu-devel] [V9 0/4] AMD IOMMU

On 04/05/16 13:58, Valentine Sinitsyn wrote: On 04.05.2016 15:51, David Kiarie wrote: On Wed, May 4, 2016 at 10:39 AM, Valentine Sinitsyn <valentine.sinit...@gmail.com> wrote: Hi everyone, On 04.05.2016 12:05, David Kiarie wrote: On Wed, May 4, 2016 at 9:12 AM, Jan Kiszka &l

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