On Mon, Aug 12, 2024 at 10:48:40AM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Fri, Aug 9, 2024 at 8:14 PM Ethan Chen wrote:
> >
> > On Thu, Aug 08, 2024 at 02:01:13PM +1000, Alistair Francis wrote:
> > >
> > > On Mon, Jul 15, 2024
On Mon, Aug 12, 2024 at 10:47:33AM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Fri, Aug 9, 2024 at 8:11 PM Ethan Chen wrote:
> >
> > On Thu, Aug 08, 2024 at 02:23:56PM +1000, Alistair Francis wrote:
> > >
> > > On Mon, Jul 15, 2024
On Thu, Aug 08, 2024 at 02:01:13PM +1000, Alistair Francis wrote:
>
> On Mon, Jul 15, 2024 at 8:15 PM Ethan Chen via wrote:
> >
> > - Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt
> > machine
> > to protect all regions of s
On Thu, Aug 08, 2024 at 02:23:56PM +1000, Alistair Francis wrote:
>
> On Mon, Jul 15, 2024 at 8:13 PM Ethan Chen via wrote:
> >
> > To enable system memory transactions through the IOPMP, memory regions must
> > be moved to the IOPMP downstream and then replac
On Thu, Aug 08, 2024 at 01:56:35PM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Mon, Jul 15, 2024 at 7:58 PM Ethan Chen via wrote:
> >
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://gi
On Thu, Aug 08, 2024 at 02:25:04PM +1000, Alistair Francis wrote:
>
> On Mon, Jul 15, 2024 at 8:15 PM Ethan Chen via wrote:
> >
> > The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and
> > specifies the CPU's RRID.
> >
> > Signed
On Thu, Aug 08, 2024 at 01:56:35PM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Mon, Jul 15, 2024 at 7:58 PM Ethan Chen via wrote:
> >
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://gi
- Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt machine
to protect all regions of system memory, and configures RRID of CPU.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 5 +++
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c| 63 +
The iopmp_dma_rw() function performs memory read/write operations to system
memory with support for IOPMP. It sends transaction information to the IOPMP
for partial hit detection.
Signed-off-by: Ethan Chen
---
hw/misc/riscv_iopmp.c | 68 +++
include/hw/mis
The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and
specifies the CPU's RRID.
Signed-off-by: Ethan Chen
---
hw/misc/riscv_iopmp.c | 6 ++
include/hw/misc/riscv_iopmp.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/misc/riscv_iopmp.c b/hw/misc/riscv
To enable system memory transactions through the IOPMP, memory regions must
be moved to the IOPMP downstream and then replaced with IOMMUs for IOPMP
translation.
The iopmp_setup_system_memory() function copies subregions of system memory
to create the IOPMP downstream and then replaces the specifi
Allow memory regions to have different behaviors for read and fetch
operations.
For example, the RISC-V IOPMP could raise an interrupt when the CPU
tries to fetch from a non-executable region.
If the fetch operation for a memory region is not implemented, the read
operation will still be used for
If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be
multiple entries within the same page. To obtain the correct result, pass
the original address to the IOMMU.
Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when
there are multiple entries in the same
Support basic functions of IOPMP specification v0.9.1 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
The IOPMP checks whether memory access from a device or CPU is valid.
This implementation uses an IOMMU to modify the address space accessed
b
Signed-off-by: Ethan Chen
---
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 +++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fb7eebde52..2946fec20c 100644
--- a/target/riscv/cpu_cfg.h
+++
This series implements basic functions of IOPMP specification v0.9.1 rapid-k
model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.
The issue of CPU
; Thanks,
> > Ethan
> >
> > On Fri, Jun 21, 2024 at 03:54:15PM +1000, Alistair Francis wrote:
> > > On Wed, Jun 12, 2024 at 1:25 PM Ethan Chen via
> > > wrote:
> > > >
> > > > If a requestor device is connected to the IOPMP
, Alistair Francis wrote:
> On Wed, Jun 12, 2024 at 1:25 PM Ethan Chen via wrote:
> >
> > If a requestor device is connected to the IOPMP device, its memory access
> > will
> > be checked by the IOPMP rule.
> >
> > - Add 'iopmp=on' option to add an i
On Mon, Jun 17, 2024 at 02:09:34PM +0200, Stefan Weil wrote:
> [EXTERNAL MAIL]
>
> Am 12.06.24 um 05:17 schrieb Ethan Chen via:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iop
On Mon, Jun 17, 2024 at 07:28:33PM +0800, LIU Zhiwei wrote:
>
> On 2024/6/12 11:17, Ethan Chen wrote:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
> >
> > IOPMP check memory
On Thu, Jun 13, 2024 at 05:26:03PM +0800, LIU Zhiwei wrote:
>
> Hi Ethan,
>
> On 2024/6/12 11:17, Ethan Chen wrote:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
> >
> > IOPM
On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote:
> [EXTERNAL MAIL]
>
> It is the preparation patch for upcoming RISC-V wgChecker device.
>
> Since RISC-V wgChecker could permit access in RO/WO permission, the
> IOMMUMemoryRegion could return different section for read & write
> access. Th
On Wed, Jun 12, 2024 at 01:43:41PM +0100, Peter Maydell wrote:
>
> On Wed, 12 Jun 2024 at 10:02, Ethan Chen via wrote:
> >
> > Allow the memory region to have different behaviors for read and fetch
> > operations.
> >
> > For example RISCV IOPMP will rai
If the IOMMU granularity is smaller than TARGET_PAGE size, there may have
multiple entries in the same page. Pass the origin address to IOMMU to get
correct result
Similar to the RISCV PMP solution, TLB_INVALID_MASK will be set when there have
multiple entries in the same page to check the IOMMU o
Allow the memory region to have different behaviors for read and fetch
operations.
For example RISCV IOPMP will raise interrupt when cpu try to fetch a
non-excutable region.
If fetch operation of a memory region is not implemented, it still uses the
read operation for fetch.
Signed-off-by: Ethan
Support basic functions of IOPMP specification v0.9.1 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
IOPMP check memory access from device is valid or not. This implementation uses
IOMMU to change address space that device access. There are th
If a requestor device is connected to the IOPMP device, its memory access will
be checked by the IOPMP rule.
- Add 'iopmp=on' option to add an iopmp device and make the Generic PCI Express
Bridge connect to IOPMP.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 6
hw/riscv/Kc
Due to changing the referenced specification version, this patch has changed
a lot in this version.
This series implements basic functions of IOPMP specification v0.9.1 rapid-k
model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
When IOPMP is enabled, mem
Hi Dainel,
Sorry for the delayed response. I've been busy over the past two months.
I plan to submit the next version of the patch within two weeks.
Thanks,
Ethan Chen
On Mon, May 27, 2024 at 09:09:49AM -0300, Daniel Henrique Barboza wrote:
> Hi Ethan,
>
>
> Did you send v7 already and I someh
On Wed, Feb 14, 2024 at 11:34:55AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 2/7/24 06:34, Ethan Chen wrote:
> > Support specification Version 1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
> >
>
If a source device is connected to the IOPMP device, its memory
transaction will be checked by the IOPMP rule.
When using RISC-V virt machine option "iopmp=on", the generic PCIe host
bridge connects to IOPMP. The PCI devices on the bridge will connect to
IOPMP with default source id(SID) from PCI
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw/Kconfi
This series implements IOPMP specification v1.0.0-draft4 rapid-k model and add
IOPMP device to RISC-V virt machine.
Patch 1 add config STREAM make other device can reuse /hw/core/stream.c, IOPMP
implementation will use it. Patch 2 implement IOPMP deivce. Patch 3 add IOPMP
device to RISC-V virt mac
Support specification Version 1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
The memory transaction from source devices connected to IOPMP will be
checked by IOPMP rule. The method of connecting the source devi
On Mon, Jan 22, 2024 at 04:01:12PM +1000, Alistair Francis wrote:
> On Thu, Dec 21, 2023 at 4:38 PM Ethan Chen wrote:
> >
> > On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> > > On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via
> > > w
If a source device is connected to the IOPMP device, its memory
transaction will be checked by the IOPMP rule.
When using RISC-V virt machine option "iopmp=on", the generic PCIe host
bridge connects to IOPMP. The PCI devices on the brigde will connets to
IOPMP with default source id(SID) from PCI
Support specification Version 1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
The memory transaction from source devices connected to IOPMP will be
checked by IOPMP rule. The method of connecting the source devi
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw/Kconfi
This series implements IOPMP specification v1.0.0-draft4 rapid-k model and add
IOPMP device to RISC-V virt machine.
Patch 1 add config STREAM make other device can reuse /hw/core/stream.c, IOPMP
implementation will use it. Patch 2 implement IOPMP deivce. Patch 3 add IOPMP
device to RISC-V virt mac
On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
> >
> > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-n
On Mon, Dec 18, 2023 at 02:04:06PM +1000, Alistair Francis wrote:
> On Wed, Nov 22, 2023 at 3:35 PM Ethan Chen via wrote:
> >
> > Support specification Version 1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-n
On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
> >
> > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-n
Ping again.
On Tue, Dec 05, 2023 at 03:48:07PM +0800, Ethan Chen wrote:
> Ping.
> https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/
>
> On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote:
> > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> >
Ping.
https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/
On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote:
> This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv
If a source device is connected to the IOPMP device, its memory access will be
checked by the IOPMP rule.
- Add 'iopmp=on' option to add an iopmp device and a dma device which is
connected to the iopmp to machine. This option is assumed to be "off"
- Add 'iopmp_cascade=on' option to add second i
Make other device can use /hw/core/stream.c by select this config.
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw/Kconfig
index 9ca7b38c31..e4d153dce7
ATCDMAC300 is a direct memory access controller (DMAC) which transfers data
efficiently between devices on the AMBA AXI4 bus.
ATCDMAC300 supports up to 8 DMA channels. Each DMA channel provides a set of
registers to describe the intended data transfers
To support RISC-V IOPMP, a memory access dev
Support specification Version 1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
IOPMP check memory access from deivce is valid or not. This implementation uses
IOMMU to change address space that device access. The
This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt
platform. This DMA device is connected to the IO
On Tue, Nov 21, 2023 at 03:28:13PM +1000, Alistair Francis wrote:
> On Tue, Nov 21, 2023 at 3:24 PM Alistair Francis wrote:
> >
> > On Tue, Nov 14, 2023 at 7:49 PM Ethan Chen via
> > wrote:
> > >
> > > Make other device can use /hw/core/stream.c by select
On Tue, Nov 21, 2023 at 03:22:18PM +1000, Alistair Francis wrote:
> On Tue, Nov 14, 2023 at 7:48 PM Ethan Chen via wrote:
> >
> > - Add 'iopmp=on' option to enable a iopmp device and a dma device
> > connect to the iopmp device
> > - Add 'iopmp_ca
On Tue, Nov 14, 2023 at 02:50:21PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 11/14/23 06:47, Ethan Chen wrote:
> > - Add 'iopmp=on' option to enable a iopmp device and a dma device
> > connect to the iopmp device
> > - Add 'iopmp_cascade=on' option to enable iopmp cascading.
> >
> > Signe
Support specification Version 1.0.0-draft4 rapid-k model.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig | 4 +
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp.c | 967 ++
include/hw/misc/riscv_iopm
Signed-off-by: Ethan Chen
---
hw/dma/Kconfig | 4 +
hw/dma/atcdmac300.c | 566
hw/dma/meson.build | 1 +
include/hw/dma/atcdmac300.h | 180
4 files changed, 751 insertions(+)
create mode 100644 hw/dma/atcdmac300.
This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt
platform. This DMA devce is connected to the IOPMP and has the functionalities
required by IOPMP, including:
- Support specify source-id (SID)
- Support as
- Add 'iopmp=on' option to enable a iopmp device and a dma device
connect to the iopmp device
- Add 'iopmp_cascade=on' option to enable iopmp cascading.
Signed-off-by: Ethan Chen
---
hw/riscv/Kconfig| 2 ++
hw/riscv/virt.c | 72 +++--
include
Make other device can use /hw/core/stream.c by select this config.
Signed-off-by: Ethan Chen
---
hw/core/Kconfig | 3 +++
hw/core/meson.build | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/core/Kconfig b/hw/core/Kconfig
index 9397503656..628dc3d883 100644
--- a/hw/core/Kconfig
+++
On Tue, Nov 07, 2023 at 10:53:40AM +, Peter Maydell wrote:
> On Tue, 7 Nov 2023 at 03:02, Ethan Chen wrote:
> >
> > On Mon, Nov 06, 2023 at 10:34:41AM +, Peter Maydell wrote:
> > > What AXI bus signals? You already get address and size in the
> > > actual memory transaction, they don't nee
On Mon, Nov 06, 2023 at 10:34:41AM +, Peter Maydell wrote:
> On Mon, 6 Nov 2023 at 01:57, Ethan Chen wrote:
> >
> > On Fri, Nov 03, 2023 at 10:34:28AM +, Peter Maydell wrote:
> > > On Fri, 3 Nov 2023 at 03:29, Ethan Chen wrote:
> > > >
> > > > On Thu, Nov 02, 2023 at 01:53:05PM +, Pet
On Fri, Nov 03, 2023 at 10:34:28AM +, Peter Maydell wrote:
> On Fri, 3 Nov 2023 at 03:29, Ethan Chen wrote:
> >
> > On Thu, Nov 02, 2023 at 01:53:05PM +, Peter Maydell wrote:
> > > On Thu, 2 Nov 2023 at 13:49, Peter Xu wrote:
> > > >
> > > > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan
On Thu, Nov 02, 2023 at 01:53:05PM +, Peter Maydell wrote:
> On Thu, 2 Nov 2023 at 13:49, Peter Xu wrote:
> >
> > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote:
> > > Signed-off-by: Ethan Chen
> > > ---
> > > include/exec/memattrs.h | 6 ++
> > > 1 file changed, 6 insertions
On Thu, Nov 02, 2023 at 09:49:17AM -0400, Peter Xu wrote:
> On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote:
> > Signed-off-by: Ethan Chen
> > ---
> > include/exec/memattrs.h | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/include/exec/memattrs.h b/include/exec/me
Signed-off-by: Ethan Chen
---
include/exec/memattrs.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d04170aa27..fc15e5d7d3 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -64,6 +64,12 @@ typedef struct MemTx
Support specification Version 1.0.0-draft4 rapid-k model.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp.c | 902 ++
include/hw/misc/riscv_iopmp.h | 330 +
4 files
This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt
platform. This DMA devce is connected to the IOPMP and has the functionalities
required by IOPMP, including:
- Support specify source-id (SID)
- Support as
Signed-off-by: Ethan Chen
---
hw/dma/Kconfig | 3 +
hw/dma/atcdmac300.c | 460
hw/dma/meson.build | 1 +
include/hw/dma/atcdmac300.h | 171 ++
4 files changed, 635 insertions(+)
create mode 100644 hw/dma/atcdmac30
- Add 'iopmp=on' option to enable a iopmp device and a dma device
connect to the iopmp device
- Add 'iopmp_cascade=on' option to enable iopmp cascading.
Signed-off-by: Ethan Chen
---
hw/riscv/Kconfig| 2 ++
hw/riscv/virt.c | 68 +
include
On Mon, Oct 30, 2023 at 11:02:30AM -0400, Peter Xu wrote:
> On Mon, Oct 30, 2023 at 02:00:54PM +0800, Ethan Chen wrote:
> > On Fri, Oct 27, 2023 at 12:13:50PM -0400, Peter Xu wrote:
> > > Add cc list.
> > >
> > > On Fri, Oct 27, 2023 at 12:02:24PM -0400, Peter Xu wrote:
> > > > On Fri, Oct 27, 202
On Fri, Oct 27, 2023 at 12:13:50PM -0400, Peter Xu wrote:
> Add cc list.
>
> On Fri, Oct 27, 2023 at 12:02:24PM -0400, Peter Xu wrote:
> > On Fri, Oct 27, 2023 at 11:28:36AM +0800, Ethan Chen wrote:
> > > On Thu, Oct 26, 2023 at 10:20:41AM -0400, Peter Xu wrote:
> > > > Could you elaborate why is
On Thu, Oct 26, 2023 at 10:20:41AM -0400, Peter Xu wrote:
> Could you elaborate why is that important? In what use case?
I was not involved in the formulation of the IOPMP specification, but I'll try
to explain my perspective. IOPMP use the same the idea as PMP. "The matching
PMP entry must match
I found that after add size information it is still not enough for IOPMP to
reject partially hit error. Access is separated in flatview_read_continue and
lost the start address information. I will fix it in next version.
Address start, address end will be added to MemTxAttr, translate_size wil
On Wed, Oct 25, 2023 at 04:56:22PM +0200, David Hildenbrand wrote:
> On 25.10.23 07:14, Ethan Chen wrote:
> > IOMMU have size information during translation.
> >
>
> Can you add some more information why we would want this and how the backend
> can do "better" things with the size at hand?
>
With
On Wed, Oct 25, 2023 at 11:14:42AM -0400, Peter Xu wrote:
> On Wed, Oct 25, 2023 at 01:14:26PM +0800, Ethan Chen wrote:
> > Signed-off-by: Ethan Chen
> > ---
> > system/physmem.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/system/physmem.c b/system/phy
- Add 'iopmp=on' option to enable iopmp
- Add 'iopmp_cascade=on' option to enable iopmp cascading.
Signed-off-by: Ethan Chen
---
hw/riscv/Kconfig| 2 ++
hw/riscv/virt.c | 72 +++--
include/hw/riscv/virt.h | 10 +-
3 files changed, 81 inser
Signed-off-by: Ethan Chen
---
include/exec/memattrs.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d04170aa27..e27b4fab00 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -64,6 +64,9 @@ typedef struct MemTxAttr
Signed-off-by: Ethan Chen
---
system/physmem.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/system/physmem.c b/system/physmem.c
index fc2b0fee01..53b6ab735c 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -432,8 +432,13 @@ static MemoryRegionSection
addres
IOMMU have size information during translation.
Signed-off-by: Ethan Chen
---
include/exec/memory.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 9087d02769..5520b7c8c0 100644
--- a/include/exec/memory.h
+++ b/include
Signed-off-by: Ethan Chen
---
hw/dma/Kconfig | 3 +
hw/dma/atcdmac300.c | 435
hw/dma/meson.build | 1 +
include/hw/dma/atcdmac300.h | 171 ++
4 files changed, 610 insertions(+)
create mode 100644 hw/dma/atcdmac30
This series implements IOPMP specification v1.0.0-draft4 rapid-k model:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt platform.
This DMA devce is connected to the IOPMP and has the function
Support specification Version 1.0.0-draft4 rapid-k model.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp.c | 881 ++
include/hw/misc/riscv_iopmp.h | 322 +
4 files
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