cd3f8a 100644
> --- a/hw/block/m25p80_sfdp.h
> +++ b/hw/block/m25p80_sfdp.h
> @@ -24,4 +24,6 @@ extern uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
> extern uint8_t m25p80_sfdp_w25q256(uint32_t addr);
> extern uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
>
> +extern uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
> +
> #endif
> --
> 2.35.1
>
b/hw/block/m25p80_sfdp.h
> @@ -21,4 +21,6 @@ extern uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
> extern uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
> extern uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
>
> +extern uint8_t m25p80_sfdp_w25q256(uint32_t addr);
(optional
tern uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
>
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 220dbc8fb327..8ba9d732a323 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -347,7
"qemu/osdep.h"
> +#include "qemu/host-utils.h"
> +#include "m25p80_sfdp.h"
> +
> +#define define_sfdp_read(model) \
> +uint8_t m25p80_sfdp_##model(uint32_t addr)\
> +{
nt8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
>
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 6b120ce65212..52df24d24751 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -240,7 +240,8 @@
d so
might be that you can switch to just INFO and _ext_id 0 above (might be the
same in the previous patch with the similar flash). Otherwise looks good to
me:
Reviewed-by: Francisco Iglesias
> + .sfdp_read = m25p80_sfdp_mx25l25635f },
> { INFO("mx25l25655e", 0xc22619,
On [2022 Jul 22] Fri 08:36:02, Cédric Le Goater wrote:
> A mx25l25635f chip model is generally found on these machines. It's
> newer and uses 4B opcodes which is better to exercise the support in
> the Linux kernel.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Fra
tern' in above hdr if we like (also the other patches),
either way:
Reviewed-by: Francisco Iglesias
> +
> +
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 13e7b28fd2b0..028b026d8ba2 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@
Provide the Micron Xccela flash mt35xu01g with Octal command support.
Signed-off-by: Francisco Iglesias
---
hw/block/m25p80.c | 57 +++
1 file changed, 57 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index a8d2519141..79e26424ec
On [2022 Sep 09] Fri 23:12:48, Vikram Garhwal wrote:
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> MAINTAINERS | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1729c090
From: Francisco Iglesias
Connect ZynqMP's USB controllers.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-zynqmp.c | 36
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 39 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx
s->needed_bytes = 2;
> +if (s->write_enable) {
> +if (get_man(s) == MAN_NUMONYX) {
> +s->needed_bytes = 2;
> + } else if (get_man(s) == MAN_MICRON) {
> +s->needed_bytes += get_addr_length(s);
> +
the same values)
Otherwise:
Reviewed-by: Francisco Iglesias
Best regards,
Francisco Iglesias
>
> Signed-off-by: Anton Kochkov
> Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123
> ---
> hw/net/can/xlnx-zynqmp-can.c | 32
> 1
RDSFDP command giving access to
> a private SFDP area under the flash. This area now needs to be
> populated with the flash device characteristics, using a new
> 'sfdp_read' handler under FlashPartInfo.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> -
On [2022 Jul 08] Fri 09:45:52, Iris Chen wrote:
> Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
> ---
> Cosmetic suggestions addressed.
>
> hw/block/m25p80.c | 102 --
> 1 file changed, 90 insertions(+), 12 deletions(
Hi Iris
On [2022 Jul 06] Wed 19:16:26, Iris Chen wrote:
> Signed-off-by: Iris Chen
A couple of suggestions below if you would like to go for a v3 but otherwise:
Reviewed-by: Francisco Iglesias
Thanks,
Best regards,
Francisco Iglesias
> ---
> Addressing all comments.
>
On [2022 Jul 01] Fri 14:23:17, Cédric Le Goater wrote:
> On 7/1/22 13:40, Francisco Iglesias wrote:
> > Hi Iris,
> >
> > Looks good, a couple of minor comments below!
> >
> > On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
> > > Signed-off-by: Iris Chen
s->data[0] |= (!!s->top_bottom_bit) << 5;
> +}
> +if (s->pi->flags & SNOR_F_HAS_SR_BP3_BIT6) {
> +s->data[0] |= (!!s->block_protect3) << 6;
> +}
>
> if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
> s->data[0] |= (!!s->quad_enable) << 6;
> @@ -1553,6 +1598,11 @@ static void m25p80_reset(DeviceState *d)
>
> s->wp_level = true;
> s->status_register_write_disabled = false;
> +s->block_protect0 = false;
> +s->block_protect1 = false;
> +s->block_protect2 = false;
> +s->block_protect3 = false;
> +s->top_bottom_bit = false;
We need to place above ones in a subsection in the vmstate (similar to the your
previous patch).
Looks good to me otherwise!
Thanks!
Best regards,
Francisco Iglesias
>
> reset_memory(s);
> }
> --
> 2.30.2
>
>
On [2022 Jun 28] Tue 17:52:50, Cédric Le Goater wrote:
> Alistair, Francisco,
>
> On 6/22/22 11:45, Francisco Iglesias wrote:
> > On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote:
> > > From: Iris Chen
> > >
> > > Signed-off-by: Iris Chen
> >
On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote:
> From: Iris Chen
>
> Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
> ---
> Fixed .needed for subsection and suggestions from Francisco
>
> hw/block/m25p80.c | 82 ++--
/* StandBy state SO shall be HiZ */
0xFF should be enough here (since we are dealing with 8 bits, e.g.
m25p80_transfer8). More safe is probably to return 0 though and see this as if
a pulldown was connected to the line instead (this because r has been default
to 0 and was the most likely return
Hi Iris,
On [2022 Jun 17] Fri 15:02:45, Iris Chen wrote:
> Signed-off-by: Iris Chen
> ---
> Thanks everyone for your comments. This is a v3 patch that addresses all
> suggestions (moving write_enable to decode_new_cmd).
> I am waiting on some feedback from Dan's (dz4l...@gmail.com) patch
>
*s = M25P80(d);
>
> +s->wp_level = true;
> + s->status_register_write_disabled = false;
> +
> reset_memory(s);
> }
>
> @@ -1601,6 +1636,8 @@ static const VMStateDescription vmstate_m25p80 = {
> VMSTATE_UINT8(needed_bytes, Flash),
>
.8c4f6eb06b6 100644
> --- a/hw/timer/slavio_timer.c
> +++ b/hw/timer/slavio_timer.c
> @@ -405,7 +405,7 @@ static void slavio_timer_init(Object *obj)
> tc->timer_index = i;
>
> s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc,
> -
; +++ b/hw/block/m25p80.c
> @@ -1558,6 +1558,7 @@ static int m25p80_pre_save(void *opaque)
>
> static Property m25p80_properties[] = {
> /* This is default value for Micron flash */
> +DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index b3c8ce973c..8
vision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 076457b270..b3c8ce973c 100644
--- a/include/hw/pci/pcie_host.h
+++ b/incl
Hi,
This series attempts to correct a couple of defines inside pcie_host.h.
Best regards,
Francisco Iglesias
Changelog:
v1->v2:
* Went from RFC to patch proposal
* Added more meat on the commit message of patch 1
Francisco Iglesias (2):
include/hw/pci/pcie_host: Corr
Hi Michael,
On [2022 Apr 11] Mon 17:12:47, Michael S. Tsirkin wrote:
> On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> > According to [1] address bits 27 - 20 are mapped to the bus number (the
> > TLPs bus number field is 8 bits).
> >
> > [1] PCI
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
On [2022 Apr 04] Mon 16:46:42, Peter Maydell wrote:
> Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
> delete the device entirely.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> hw/intc/exyn
On Wed, Apr 06, 2022 at 06:43:03PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the CRL (Clock Reset LPD) to the Versal SoC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw
On Wed, Apr 06, 2022 at 06:43:02PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add a model of the Xilinx Versal CRL.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/misc/meson.build | 1
On Wed, Apr 06, 2022 at 06:43:01PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
> subsystem.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
>
On Wed, Apr 06, 2022 at 06:43:00PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Create an APU CPU Cluster. This is in preparation to add the RPU.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> h
On [2022 Apr 02] Sat 22:45:23, Pavel Pisa wrote:
> Signed-off-by: Pavel Pisa
Reviewed-by: Francisco Iglesias
> ---
> docs/system/devices/can.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/system/devices/can.rst b/docs/system/devic
On [2022 Apr 01] Fri 12:06:31, Tong Ho wrote:
> This adds required initialization of Error * variable.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-bbram.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw
On [2022 Apr 01] Fri 00:20:17, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the 4 TTC timers on the ZynqMP.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h | 4
>
On [2022 Apr 01] Fri 00:20:16, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Break out header file to allow embedding of the the TTC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> incl
0x559a21bf3442 in object_class_foreach_tramp
> /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
>
> Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read
> transfer through a class method")
> Signed-off-by: Peter Maydell
Revie
; 10, 1024, ER_4K) },
> +{ INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K) },
Reviewed-by: Francisco Iglesias
> };
>
> typedef enum {
> --
> 2.34.1
>
>
es removing one stray useless setting of
> minimum_version_id_old in a VMStateDescription with no load_state_old
> function, which crept in after the global weeding-out of them in
> commit 17e313406126.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
&g
'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for
avoiding the situation where one of the models incorrectly deasserts an
interrupt asserted from the other model (which will result in that the IRQ
is lost and will not reach guest SW).
Signed-off-by: Francisco Iglesias
On Mon, Jan 31, 2022 at 12:12:06AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the ZynqMP APU Control device.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 +++-
>
On Mon, Jan 31, 2022 at 12:12:01AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add unimplemented SERDES area.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 +-
> hw/arm/x
+qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
> +/* CPU_POWER_STATUS is used to connect to INTC redirect. */
> +qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
> + "CPU_POWER_STATUS", 4);
> +/* wfi_in is us
On Mon, Jan 31, 2022 at 12:12:04AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the ZynqMP CRF - Clock Reset FPD device.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h
> +.read = register_read_memory,
> +.write = register_write_memory,
> +.endianness = DEVICE_LITTLE_ENDIAN,
> +.valid = {
> +.min_access_size = 4,
> + .max_access_size = 4,
> +},
> +};
> +
> +static void crf_init(Object *obj)
> +{
> +Xlnx
On Thu, Jan 27, 2022 at 05:27:55PM +, Peter Maydell wrote:
> On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias
> wrote:
> >
> > Hi,
> >
> > This series attempts to add support for Xilinx Versal's PMC SLCR
> > (system-level control registers) and OSPI f
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 +++--
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c | 28
of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Changelog:
v6 ->
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/arm/xlnx-versal.h | 20 ++
hw/arm/xlnx-versal.c | 93
2 files
(and signals).
This patch adds a class 'read' method for allowing to start read transfers
from peripherals embedding and controlling the Xilinx CSU DMA engine as in
above scenario.
Signed-off-by: Francisco Iglesias
---
include/hw/dma/xlnx_csu_dma.h | 19 +--
hw/dma/xlnx_csu_dma.c
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
hw/ssi/xlnx-versal-ospi.c | 1853 +
hw/ssi/meson.build|1 +
3 files changed, 1965
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
---
include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 78 ++
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e4b3a4bcdf..6797a270e4 100644
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
Reviewed-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5
hw/arm/xlnx-versal.c | 71 +++-
2 files changed, 75 insertions(+), 1 deletion
On [2022 Jan 18] Tue 23:01:42, Luc Michel wrote:
> Hi Francisco!
>
> On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> > An option on real hardware when embedding a DMA engine into a peripheral
> > is to make the peripheral control the engine through a custom DMA
Hi Luc,
All the suggestions and corrections look good to me so brought them in in
v7!
Thank you very much reviewing!
Best regards,
Francisco Iglesias
On [2022 Jan 18] Tue 22:46:32, Luc Michel wrote:
> Hi Francisco,
>
> Impressive beast :-) Nicely done. Maybe I would h
of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Changelog:
v5 ->
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 243 +
docs/devel/index.rst | 1 +
3 files changed, 245 insertions
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 93
include/hw/arm/xlnx-versal.h | 20 ++
2 files
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1856 +
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
3 files changed, 1968
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6ccdec7f02..0e31569d65 100644
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
signaling will be read and caught through the DMA engine
model's register API and signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl-if.c | 30 +++
hw/dma/meson.build | 1 +
include/hw/dma/dma-ctrl-if.h | 58
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c | 28 ++--
include/hw/arm/xlnx-versal.h | 5 +++--
3 files changed
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 71 +++-
include/hw/arm/xlnx-versal.h | 5
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/hw/arm
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446
On [2022 Jan 07] Fri 16:07:17, Peter Maydell wrote:
> On Tue, 14 Dec 2021 at 11:04, Francisco Iglesias
> wrote:
> >
> > Also, since being the author, list myself as maintainer for the file.
> >
> > Signed-off-by: Francisco Igles
On Fri, Dec 10, 2021 at 12:21:26PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:41, Francisco Iglesias
> wrote:
> >
> > Also, since being the author, list myself as maintainer for the file.
> >
> > Signed-off-by: Francisco Iglesias
> > ---
&
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 93
include/hw/arm/xlnx-versal.h | 20 ++
2 files changed, 113 insertions(+)
diff
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..e52cc94840 100644
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/dma
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 234 +
docs/devel/index.rst | 1 +
3 files changed, 236 insertions
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 71 +++-
include/hw/arm/xlnx-versal.h | 5
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/hw/arm
signaling will be read and caught through the DMA engine
model's register API and signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl-if.c | 30 ++
hw/dma/meson.build | 1 +
include/hw/dma/dma-ctrl-if.h | 51
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1855 +
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
3 files changed, 1967
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx
of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Changelog:
v4 ->
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446
include/hw/misc/xlnx
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
On Fri, Dec 10, 2021 at 04:02:22PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias
> wrote:
> >
> > Add a model of Xilinx Versal's OSPI flash memory controller.
> >
> > Signed-off-by: Francisco Iglesias
>
>
>
>
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c | 28 ++--
include/hw/arm/xlnx-versal.h | 5 +++--
3 files changed, 30 insertions(+), 5
On Fri, Dec 10, 2021 at 03:16:59PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias
> wrote:
> >
> > Connect Versal's PMC SLCR (system-level control registers) model.
> >
> > Signed-off-by: Francisco Iglesias
> > diff --git a/inclu
On Fri, Dec 10, 2021 at 03:11:41PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias
> wrote:
> >
> > Add a model of Versal's PMC SLCR (system-level control registers).
> >
> > Signed-off-by: Francisco Iglesias
> > Signed-off-by: Ed
of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Changelog:
v3 ->
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 320 +
docs/devel/index.rst | 1 +
3 files changed, 322 insertions
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..e52cc94840 100644
--- a/MAINTAINERS
+++ b
signaling will be read and catched through the DMA engine
model's register API and signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl-if.c | 31 +++
hw/dma/meson.build | 1 +
include/hw/dma/dma-ctrl-if.h | 72
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 88
include/hw/arm/xlnx-versal.h | 20 ++
2 files
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw
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