rotection and Translation */
> [CSR_SATP] = { "satp", smode, read_satp,write_satp },
>
> +/* Supervisor-Level Interrupts (AIA) */
> +[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
> +
> /* Supervisor-Level High-Half CSRs (AIA) */
> [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> @@ -2454,6 +2607,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HVIPRIO1]= { "hviprio1",aia_hmode, read_hviprio1,
> write_hviprio1 },
> [CSR_HVIPRIO2]= { "hviprio2",aia_hmode, read_hviprio2,
> write_hviprio2 },
>
> +/* VS-Level Interrupts (H-extension with AIA) */
> +[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
> +
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
On Wed, Jan 12, 2022 at 1:18 AM Anup Patel wrote:
>
>
> On Mon, Jan 10, 2022 at 6:38 PM Frank Chang
> wrote:
> >
> > Anup Patel 於 2021年12月30日 週四 下午8:38寫道：
> >>
> >> From: Anup Patel
> >>
> >> The AIA spec defines programmable 8-bit
-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> +[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
> write_hviprio1h },
> [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
> write_hviprio2h },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
} else if (irq == IRQ_S_GEXT) {
> +iprio = IPRIO_DEFAULT_SGEXT;
> +} else if (irq == IRQ_S_EXT || irq == IRQ_S_TIMER ||
> + irq == IRQ_S_SOFT) {
> +iprio = IPRIO_DEFAULT_S;
> +} else if (irq == IRQ_M_EXT || irq == IRQ_M_TIMER ||
ty
number p.
For a major interrupt that defaults to a higher priority than machine
external interrupts,
setting its priority number to a nonzero value lowers its priority.
For a major interrupt that defaults to a lower priority than machine
external interrupts,
setting its priority number to a nonzero value
space_stl_le(_space_memory, addr,
> + eiid, MEMTXATTRS_UNSPECIFIED, );
> +if (result != MEMTX_OK) {
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for "
> + "hart_index=%d guest_index=%d eiid=%d\n",
&g
SCVAPLICState *aplic,
> +uint32_t irq, bool pending)
> +{
> +uint32_t sourcecfg, sm;
> +
> +if ((irq <= 0) || (aplic->num_irqs <= irq)) {
> + return;
> +}
> +
> +sourcecfg = aplic->sourcecfg[irq];
> +i
ret = -EINVAL;
> +bool set, pend, virt;
> +target_ulong priv, isel, vgein, xlen, nval, wmask;
> +
> +/* Translate CSR number for VS-mode */
> +csrno = aia_xlate_vs_csrno(env, csrno);
> +
> +/* Decode register details from CSR number */
> +virt = set =
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 8 insertions(+), 4 deletions
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
From: Frank Chang
For vector widening and narrowing floating-point instructions, we should
use require_scale_rvf() instead of require_rvf() to check whether the
correspond RVF/RVD is enabled if either source or destination
floating-point operand is double-width of SEW. Otherwise, illegal
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use
On Wed, Dec 29, 2021 at 10:43 AM Frank Chang wrote:
> 於 2021年12月29日 週三 上午10:13寫道：
>
>> From: Frank Chang
>>
>> For vector widening and narrowing floating-point instructions, we should
>> use require_scale_rvf() instead of require_rvf() to check whether the
&g
於 2021年12月29日 週三 上午10:13寫道：
> From: Frank Chang
>
> For vector widening and narrowing floating-point instructions, we should
> use require_scale_rvf() instead of require_rvf() to check whether the
> correspond RVF/RVD is enabled if either source or destination
> floating-point
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e98860a09..2b54c64f56 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -636,6 +636,7 @@ static Property
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/riscv
From: Frank Chang
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
---
target/riscv/insn_trans
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 01239620ca..38cd11a8ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -636,6 +636,7 @@ static Property
From: Frank Chang
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
---
target/riscv/insn_trans
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
1 file changed, 25 insertions(+), 7 deletions(-)
diff
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 27 +++--
1 file changed, 25
From: Frank Chang
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c| 4 ++--
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 2 +-
target/riscv/translate.c | 2 ++
5 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/target
From: Frank Chang
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +
1 file changed, 13 insertions
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 5 -
target/riscv/csr.c| 6 +-
target/riscv/translate.c | 2 ++
5 files changed, 16 insertions(+), 2 deletions(-)
diff --git
From: Frank Chang
In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
This patchset implements Zve32f and Zve64f extensions.
The port
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv
From: Frank Chang
For vector widening and narrowing floating-point instructions, we should
use require_scale_rvf() instead of require_rvf() to check whether the
correspond RVF/RVD is enabled if either source or destination
floating-point operand is double-width of SEW. Otherwise, illegal
From: Frank Chang
In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit
is not set to 1 correclty when the assigned SD image size is larger
than 2GB (SDHC). This will cause the SD card to be indentified as SDSC
incorrectly. CCS bit should be set to 1 if we are using SDHC.
Also
From: Frank Chang
In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit
is not set to 1 correclty when the assigned SD image size is larger
than 2GB (SDHC). This will cause the SD card to be indentified as SDSC
incorrectly. CCS bit should be set to 1 if we are using SDHC.
Also
w_left > 0) {
> +irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> +counter->irq_overflow_left;
> +timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at);
> +counter->irq_overflow_left = 0;
> +
From: Frank Chang
SEW has the limitation which cannot exceed ELEN.
Widening instructions have a destination group with EEW = 2*SEW
and narrowing instructions have a source operand with EEW = 2*SEW.
Both of the instructions have the limitation of: 2*SEW <= ELEN.
Signed-off-by: Frank Ch
From: Frank Chang
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file
From: Frank Chang
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1
From: Frank Chang
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check
From: Frank Chang
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first
From: Frank Chang
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 22 -
target/riscv/insn32.decode | 15 ---
target/riscv/insn_trans/trans_rvv.c.inc | 59 +
target/riscv/vector_helper.c
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 ++--
target/riscv/insn32.decode | 4 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 4 ++--
4 files
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 27 +
2 files changed, 29 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv
From: Frank Chang
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/fpu_he
From: Frank Chang
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-
From: Frank Chang
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.c.inc | 23 ---
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Frank Chang
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 11 ++--
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +---
target/riscv/vector_helper.c| 12 ++--
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 12 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 18 +-
target/riscv/internals.h| 9 +
3 files changed, 24 insertions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aed230e1ad..cc95b69255
From: Frank Chang
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 20
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++---
target/riscv/vector_helper.c| 52
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 6 --
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.c.inc | 2 --
target/riscv/vector_helper.c| 7 ---
4 files
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 10 --
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 16
From: Frank Chang
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.c.inc | 40 +
target/riscv/vector_helper.c| 21
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 +++---
target/riscv/insn32.decode | 12 +++
target/riscv/insn_trans/trans_rvv.c.inc | 42 -
target/riscv
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +
1 file changed, 22
From: Frank Chang
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c| 4
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 277a5e4120..71d7b1e879 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 16 ++
target/riscv/insn32.decode
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/gdbstub.c | 184 +
3 files changed
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7d8441d1f2..92a0e6fe51
From: Frank Chang
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 2 +
target
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.
From: Frank Chang
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 67 +++
target/riscv/insn32.decode | 21 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 110 +---
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.c.inc | 9 --
target/riscv/vector_helper.c| 205
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 14 +
target/riscv/insn32.decode | 8
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ac5162aeb..ab274dcde1
From: Frank Chang
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.c.inc | 25 +
2 files changed, 29
From: Frank Chang
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 129 ++--
target/riscv/insn32.decode | 43 ++-
target/riscv/insn_trans/trans_rvv.c.inc | 376
target/riscv/vector_helper.c
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 27 -
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 62 +++--
target/riscv/vector_helper.c| 14 +-
2 files changed, 40 insertions(+), 36 deletions(-)
diff
From: Frank Chang
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 27 ++---
target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 92a0e6fe51..f61eaf7c6b
From: Frank Chang
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 8
1 file changed, 4
From: Frank Chang
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 21
target/riscv/insn32.decode | 22
target/riscv/insn_trans/trans_rvv.c.inc | 68
From: Frank Chang
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/
From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 26 ++---
target/riscv/insn32.decode | 14 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 33 +++
target/riscv
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 715 +---
1 file changed, 507 insertions(+), 208 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a3f1101cd6..7548b71efd 100644
--- a/target/riscv
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW
From: Frank Chang
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 35 +---
target/riscv
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