up the ELF to have it appear as
an R5900 program afterwards?
DMULT within an R5900 ELF would still be tested, as intended, even if
there might be some additional non-R5900 instructions in it as well (which
R5900/QEMU is supposed to accept anyway, no?).
On Friday, 12 March 2021, Philippe Mathieu-Daudé wrote
On Friday, 12 March 2021, Maciej W. Rozycki wrote:
> On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
>
> > >>> Is there any way we can do this with a distro that isn't Gentoo
> > >>> so that we can get a container build that is fast enough to be
> > >>> useful for CI ?
> >
> > Using the
On Friday, 12 March 2021, Philippe Mathieu-Daudé wrote:
> Now than SQ is properly implemented, we can move the RDHWR
> kludge required to have usermode working with recent glibc.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: { RDHWR_user } (rth)
>
> Fredrik, I'm not understanding fully
On Tue, Feb 16, 2021 at 01:21:34PM +0100, Maciej W. Rozycki wrote:
> > > I would do this as
> > >
> > > {
> > > RDHWR_user 01 0 . . 0 111011 @rd_rt
> > > SQ 01 . . @ldst
> > > }
> >
> > Both rd and rt have fixed values, as
On Mon, Feb 15, 2021 at 01:01:52PM -0800, Richard Henderson wrote:
> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> > +/*
> > + * The TX79-specific instruction Store Quadword
> > + *
> > + * ++---+---++
> > + * | 01 | base |
On Sun, Feb 14, 2021 at 06:59:11PM +0100, Philippe Mathieu-Daudé wrote:
> Test BusyBox on the R5900 CPU with 2 different binaries:
>
> - o32 32-bit (statically linked)
> - o32 64-bit (dynamically linked, uses multimedia instructions)
R5900/libc update:
Gnu libc for o32 was merged some time ago
On Mon, Feb 15, 2021 at 11:59:57AM +, Daniel P. Berrangé wrote:
> On Sun, Feb 14, 2021 at 06:59:02PM +0100, Philippe Mathieu-Daudé wrote:
> > Add a Docker image providing cross toolchain for the MIPS R5900 CPU
> > (used on the Sony PS2).
> >
> > This image is based on Gentoo and the toolchain
On Thu, Dec 17, 2020 at 05:10:24PM +0100, Philippe Mathieu-Daudé wrote:
> On 12/17/20 11:40 AM, Laurent Vivier wrote:
> > Le 19/11/2020 à 17:17, Philippe Mathieu-Daudé a écrit :
> >> o32 ABI syscalls start at offset 4000.
> >>
> >> Signed-off-by: Philippe Mathieu-Daudé
> >> ---
> >>
On Sun, Dec 13, 2020 at 04:23:23PM +0100, Philippe Mathieu-Daudé wrote:
> I noticed GCC merged your patch,
By the way, the fairly new -mfix-r5900 option (implied with mipsr5900el)
is required for the R5900 hardware short loop erratum[1]. I've made a
simple tool to scan ELF objects for
On Sun, Dec 13, 2020 at 04:23:23PM +0100, Philippe Mathieu-Daudé wrote:
> On 12/12/20 5:04 PM, Fredrik Noring wrote:
> > I may be able to help on the TX79 that is an R5900, but unless commit
> > 823f2897bdd7 ("target/mips: Disable R5900 support") is reverted, it
>
On Thu, Nov 19, 2020 at 04:45:29PM +, Maciej W. Rozycki wrote:
> On Thu, 19 Nov 2020, Philippe Mathieu-Daudé wrote:
>
> > MIPS o32 ABI on 64-bit CPUs looks like a ILP32-on-64bit data
> > model, allowing 64-bit arithmetic and data movement instructions.
> >
> > This is the default ABI used by
On Fri, Nov 20, 2020 at 10:08:44PM +0100, Philippe Mathieu-Daudé wrote:
> Add an entry for the TCG core related to Toshiba TXx9.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Adding Fredrik Noring in case he wants to be notified of changes,
> patch conditional to his approv
On Sat, Nov 14, 2020 at 07:23:10PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Fredrik and Aleksandar,
>
> On Fri, Jan 18, 2019 at 6:10 PM Aleksandar Markovic
> wrote:
> >
> > From: Fredrik Noring
> >
> > The 32 R5900 128-bit registers are split into two
On Fri, Nov 13, 2020 at 10:39:42AM +0100, Philippe Mathieu-Daudé wrote:
> On 2/27/19 3:00 PM, Aleksandar Markovic wrote:
> > From: Mateja Marjanovic
> >
> > Set up MMI code to be compiled only for TARGET_MIPS64. This is
> > needed so that GPRs are 64 bit, and combined with MMI registers,
> >
Hi Philippe,
[ My apologies for the late reply, somehow this thread was treated as spam. ]
On Thu, Nov 19, 2020 at 06:13:20PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Maciej,
>
> On 11/19/20 5:45 PM, Maciej W. Rozycki wrote:
> > On Thu, 19 Nov 2020, Philippe Mathieu-Daudé wrote:
> >
> >> MIPS
Hi Aleksandar,
> Sorry, I have to disagree with this.
It was, without a doubt, entirely clear that the o32 ABI was going to stay
in after this MMI patch series. In other words, this series does not imply
the removal of o32. This is obvious, as discussed previously, since the o32
ABI is currently
Hi Aleksandar,
> Awesome!
>
> I am especially happy with your choice of naming "mmr" (MultiMedia
> Registers) for these fieilds, since that is what they really are (and they
> are certainly not "gprs"). Right on the money!
Great, thanks!
> > For HI1 and LO1 only? I'm asking since HI0 and LO0
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsn32r5900/Makefile | 3 +-
tests/tcg/mips/mipsn32r5900/lq.c | 111 +++
2 files changed, 113 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsn32r5900/lq.c
diff --git a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsn32r5900/Makefile | 25 +++
tests/tcg/mips/mipsn32r5900/pcpyuld.c | 46 +++
2 files changed, 71 insertions(+)
create mode 100644 tests/tcg/mips/mipsn32r5900/Makefile
create mode 100644 tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsn32r5900/Makefile | 1 +
tests/tcg/mips/mipsn32r5900/sq.c | 105 +++
2 files changed, 106 insertions(+)
create mode 100644 tests/tcg/mips/mipsn32r5900/sq.c
diff --git a/tests/tcg/mips/mipsn32r5900/Makefile
b
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 46 -
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8c350729bc..79505bb6c2 100644
--- a/target/mips/translate.c
+++ b/target
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 40faf9cb36..8c350729bc 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 44 +++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 79505bb6c2..1c7c649d36 100644
--- a/target/mips/translate.c
+++ b
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9d5150ec8b..40faf9cb36 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
The 32 R5900 128-bit MMRs are split into two 64-bit halves: the lower
halves are the GPRs and the upper halves are accessible by the R5900-
specific multimedia instructions.
Signed-off-by: Fredrik Noring
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 14 --
2 files
The R5900 MMIs operate on 128-bit registers that will be split into
two halves: lower 64-bit GPRs and upper 64-bit MMRs. The MMIs will
therefore be left unimplemented in 32-bit mode with the o32 ABI.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 28
1
build
configurations
{gcc,clang} x -m64 x mips{,64}el-{linux-user,softmmu}
{gcc,clang} x -m64 x mipsn32el-linux-user
in addition successfully completing the R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
cd tests/tcg/mips/mipsn32r5900 && make check
F
Hi Aleksandar,
> - Suggestion: The next MIPS pull request is scehuled for Friday,
> Jan 18, 2018. It would be fantastic if you could prepare the
> following by Jan 14:
>
> * Add 32 TCGv_i64 registers that would represent higher halves
> of R5900 general purpose registers.
Done!
> * Add
Hi Aleksandar,
> Glad to see you back!
Likewise!
> Yes, one can say this is a step towards reenabling R5900 support.
Great!
> At this moment I have a question a suggestion for you:
>
> - Question: Do you have somewhere link to n32 R5900 toolchain, or
> similar thing that would enable me to
Thanks Aleksandar!
> > From: Fredrik Noring
> > Subject: [PATCH v2 09/12] tests/tcg/mips: Test R5900 three-operand MADDU1
>
> Reviewed-by: Aleksandar Markovic
>
> This patch is selected for integration in the next MIPS pull request
> scheduled shortly.
Hi Maciej,
> Of course you can instead just set the default manually by using
> `--with-llsc' when configuring GCC or specify `-mllsc' explicitly in
> CFLAGS with a compiler that has been already built without that set by
> default.
There are ways to pass such flags to the crossdev command,
Hi Alex,
> This fails to build glibc, but doesn't exactly give much info:
>
>* Log: /var/log/portage/cross-mipsr5900el-unknown-linux-gnu-binutils.log
>* Emerging cross-binutils ...[
> ok ]
>* Log:
>
or the R5900 too. The
special --without-llsc default for the R5900 is therefore not applicable
in that case.
Reviewed-by: Maciej W. Rozycki
2018-11-12 Fredrik Noring
gcc/
* config.gcc: Update with-llsc defaults for MIPS r5900.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@266038 1
Hi Philippe,
On Tue, Nov 13, 2018 at 11:51:54PM +0100, Philippe Mathieu-Daudé wrote:
> On Tue, Nov 13, 2018 at 8:29 PM Philippe Mathieu-Daudé
> wrote:
> > On Tue, Nov 13, 2018 at 8:08 PM Aleksandar Markovic
> > wrote:
> > >
> > > From: Aleksandar Markovic
> > >
> > > Disable R5900 support.
Hi Aleksandar,
> Tx79 mentions the opposite: that DDIV, DDIVU, DMULT, DMULTU are not
> included in R5900 set.
>
> I think that the best solution that you exclude DDIV, DDIVU, DMULT, DMULTU
> in a separate patch - there is no document to support their inclusion.
As Maciej noted, the 64-bit MIPS
Hi Aleksandar,
> > The R5900 reports itself as MIPS III ...
>
> This is very unclear. What do you mean by this? How does R5900 do that? I
> can't find any trace of such intentions in R5900 docs.
In QEMU, we have previously defined the R5900 as MIPS III by
#define CPU_R5900 (CPU_MIPS3 |
Hi Aleksandar,
> Fredrik, do you know by any chance if a document exists that would justify
> inclusion of non-R5900 DMULT, DMULTU, DDIV, DDIVU in R5900 executables by
> gcc for R5900? Is it included by cross-gcc or by native gcc, or by both?
>
> I think gcc folks must have had a good reason for
The R5900 reports itself as MIPS III but does not implement DMULT.
Verify that DMULT is emulated properly in user mode by multiplying
two 64-bit numbers to produce a 128-bit number.
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsn32r5900/Makefile | 25 +
tests/tcg/mips
Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
supporting the n32 ABI.
Signed-off-by: Fredrik Noring
---
linux-user/mips64/target_elf.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h
index ec55d8542a
-m64 x mipsn32el-linux-user
in addition successfully completing the R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
cd tests/tcg/mips/mipsn32r5900 && make check
Fredrik Noring (2):
linux-user/mips: Support the n32 ABI for the R5900
tests/tcg/mips: Test
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c3ed4c21ce..007dfd2975 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28329,8
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 45ad70c097..c3ed4c21ce 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
instead of the generic decode_opc_special_legacy.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 54 ++---
1 file
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 65 +
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target
O 32-bit truncation with the MIPS64 DSP ASE
- Decode special R5900 opcodes in decode_opc_special_tx79
- Guard check_insn_opc_user_only with INSN_R5900 check
- Guard check_insn with INSN_R5900 check
Fredrik Noring (6):
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
tar
ber")
Cc: Jia Liu
Reported-by: Maciej W. Rozycki
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 36
1 file changed, 4 insertions(+), 32 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3ddd70043a..19ae7d2f1c 1006
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 51 -
1 file changed, 40 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b
Hi Aleksandar,
> I think the following code would be even better:
>
> case OPC_SC:
> check_insn(ctx, ISA_MIPS2);
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> if (ctx->insn_flags & INSN_R5900) {
> check_insn_opc_user_only(ctx, INSN_R5900);
> }
>
Hi Aleksandar,
> I am glad that you want to include QEMU disas support for R5900 - this
> area usually gets forgotten.
>
> But, as you can see, this MIPS feature is partially broken - it doesn't
> handle well overlapping opcodes, and the field "membership" is not taken
> into account at all. I
Thank you for your review, Aleksandar,
> For LL, SC, LLD and SCD instructions, there is a need to properly insulate
> their R5900 versions too, similar to this:
>
> case OPC_SC:
> if(ctx->insn_flags & INSN_R5900) {
> check_insn_opc_user_only(ctx, INSN_R5900);
> }
Thanks for checking this, Maciej,
[ Cc-ing Jia Liu, who added MIPS ASE DSP support in commit 4133498f8e532f
"Use correct acc value to index cpu_HI/cpu_LO rather than using a fix
number", in case there are known ISA deviations. ]
> However `gen_HILO' looks wrong to me as it'll truncate the
Thank you for your reviews, Philippe and Richard,
> > +switch (opc) {
> > +case TX79_MMI_MFHI1:
> > +#if defined(TARGET_MIPS64)
> > +tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[1]);
> > +#else
> > +tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
> > +#endif
>
> You do not need this
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 67 ++---
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 65 +
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips
This series amends the R5900 support with the following changes:
- MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead
of the generic gen_HILO.
- DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Fredrik Noring (2):
target/mips: Fix
Hi Peter,
> From the other side of things, as a submaintainer around release
> time there's often a lot of work to do and it's easy to confuse
> different patchsets or forget the status of them, so it's useful
> to have a patch series which is exactly the set of patches that
> the submitter
Hi Aleksandar,
> It is now code freeze before 3.1, the code base is being stabilized, and
> only important fixes are allowed to be integrated - so, in that light, a
> separate patch, or a small series, that addresses only concerns from the
> original mail of this thread is needed. Such series
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/madd.c | 43 +
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/madd.c | 45 +++
2 files changed, 46 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/madd.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Signed-off-by: Fredrik Noring
---
disas/mips.c | 8
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index d73d4094d8..9f01fda8bd 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct mips_opcode
/* ST Microelectronics Loongson 2F
y: Fredrik Noring
Tested-by: Fredrik Noring
---
target/mips/translate.c | 58 +
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 624e53644d..4808cb49c3 100644
--- a/target/mips/transla
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
--- a/tests/tcg/mips
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Tested-by: Fredrik Noring
Signed-off-by: Fredrik Noring
---
disas/mips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/mips.c b/disas/mips.c
index 97f661a37e..d73d4094d8 100644
--- a/disas/mips.c
+++ b/di
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4808cb49c3..57b17ad8f6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5021,7
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/maddu.c | 37 +++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Disassemble the R5900 instructions DIV1, DIVU1, MFLO1, MTLO1, MFHI1,
MTHI1, MULT1 and MULTU1. The opcodes for MADD1 and MADDU1 clash with
the opcodes for CLZ and CLO, resulting in incorrect disassembly. They
are therefore omitted here.
Signed-off-by: Fredrik Noring
---
disas/mips.c | 12
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 65 +
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6e5a8a2565..624e53644d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27992,7
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 67 ++---
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b
https://wiki.qemu.org/File:C790.pdf>.
Changes in v2:
- Drop rejected rename of ASE_MMI to ASE_TOSHIBA_MMI
- Generate R5900 DIV1 and DIVU1 in gen_div1_tx79
- Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79
Fredrik Noring (10):
target/mips: Generate R5900 MFLO1, MFHI1, MTLO1 and
[ Philippe and Emilio -- thank you for cc-ing me. Good catch, since I'm
not subscribed to the QEMU mailing list. Changes to the R5900 emulation
are certainly of interest. ]
Hi Aleksandar, Philippe,
On Thu, Nov 01, 2018 at 03:31:54PM +0100, Philippe Mathieu-Daudé wrote:
> Cc'ing Fredrik.
>
> On
Hi Aleksandar,
> Without TARGET_MIPS64, we can't say we emulate R5900 - we are emulating
> some other CPU that never existed.
>
> Convince me that I am wrong.
R5900 O32 is usable. The R5900 toolchain is not yet ready for N32. Regarding
your proposal to rename TX79_MMI to MMI: what other ISAs do
Hi Aleksandar,
> This series renames MMI-related code elements so that they do not
> contain TX79 substring. Tx79 is one of CPUs that support MMI ASE.
> Opcodes and other code elements should be as generic as possible,
> and should not contain CPU name if they are supported by multiple
> CPUs. In
Hi Maciej,
> I'm not sure if every single random vendor-specific instruction (or a
> bunch of) deserves its own ASE designation, be it internal or externally
> exposed. I think the MMI set being a substantial architectural feature
> makes sense to be shown in /proc/cpuinfo (in Linux), but I
Hi Maciej,
> > Is the membership field intended to be used? The opcodes for CLZ and CLO
> > clash with the R5900 opcodes for MADD1 and MADDU1, resulting in incorrect
> > disassembly of MADD1 and MADDU1. For example:
> >
> > 0x70853020 madd1 a2,a0,a1 disassembles into clz a2 or a1,a0
> >
Disassemble the R5900 instructions DIV1, DIVU1, MFLO1, MTLO1, MFHI1,
MTHI1, MULT1 and MULTU1.
Signed-off-by: Fredrik Noring
---
disas/mips.c | 12
1 file changed, 12 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 9f01fda8bd..eddfb59325 100644
--- a/disas/mips.c
+++ b
Several vendors have multimedia instruction (MMI) sets and other
extensions of various kinds. ASE vendor namespaces make it clear these
are not generic architectural features and also avoid name clashes.
Reported-by: Maciej W. Rozycki
Signed-off-by: Fredrik Noring
---
target/mips/mips-defs.h
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index add6203c5a..208a15c0c1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4813,7
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Tested-by: Fredrik Noring
Signed-off-by: Fredrik Noring
---
disas/mips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/mips.c b/disas/mips.c
index 97f661a37e..d73d4094d8 100644
--- a/disas/mips.c
+++ b/di
Amend definition for MIPS ISAs in disassembler with R5900.
Signed-off-by: Fredrik Noring
---
disas/mips.c | 8
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index d73d4094d8..9f01fda8bd 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/madd.c | 45 +++
2 files changed, 46 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/madd.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8547a6e6f6..18167df26d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26100,7
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/maddu.c | 37 +++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
the R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
Reference:
[1] "Toshiba TX System RISC TX79 Core Architecture", Toshiba Corporation,
section B.3.2, p. B-4, <https://wiki.qemu.org/File:C790.pdf>.
Fredrik Noring (9):
target/mips: Rename ASE_MMI to ASE_T
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/madd.c | 43 +
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips
y: Fredrik Noring
Tested-by: Fredrik Noring
---
target/mips/translate.c | 58 +
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 18167df26d..add6203c5a 100644
--- a/target/mips/transla
Hi Richard,
> > Option 3: Extend the mips_opcode::membership field.
>
> It's trivial to extend the field to uint64_t.
Is the membership field intended to be used? The opcodes for CLZ and CLO
clash with the R5900 opcodes for MADD1 and MADDU1, resulting in incorrect
disassembly of MADD1 and
Hi Philippe,
> The three-operand MADD and MADDU are specific to the
> Toshiba TX19/TX39/TX79 cores.
>
> The "32-Bit TX System RISC TX39 Family Architecture manual"
> is available at https://wiki.qemu.org/File:DSAE0022432.pdf
>
> Signed-off-by: Philippe Mathieu-Daudé
I'm queueing your MADD and
Hi Philippe,
On Wed, Oct 24, 2018 at 12:57:32PM +0200, Philippe Mathieu-Daudé wrote:
> Increase the size of 'membership' holder size to 64 bits. This is
> needed for future extensions since existing bits are almost all used.
> (This change is related to f9c9cd63e3),
I'm queueing your patch to
Hi Peter, Aleksandar,
> Hi: I get compile errors on 32-bit hosts:
>
> /home/petmay01/qemu-for-merges/disas/mips.c:615:35: error: large
> integer implicitly truncated to unsigned type [-Werror=overflow]
> #define INSN_5900 0x1
>^
>
Hi Maciej,
> target/mips/translate.c:4888:38: error: passing argument 3 of
> ‘tcg_gen_add2_i32’ from incompatible pointer type
> [-Werror=incompatible-pointer-types]
> tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
> ^~
Would
Hi Maciej,
> I have no authority to approve such a change for the kernel, but it looks
> reasonable to me and I will support you with it, with one reservation
> however. As this is an ISA extension in the vendor-specific space, I
> think it belongs to a vendor-specific namespace, so as to
Hi Aleksandar,
> Pull request with 32 patches from this series is already sent, and I would
> like to avoid sending v2 of that request. Let's wait for some time until
> the pull request is hopefully accepted. There will be most likely another
> one at the beginning of the next week.
>
> We are
Many thanks, Aleksandar,
> I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> the overall MIPS for QEMU design.
Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
even if it is a vendor-specific architecture extension that normally
isn't counted as an
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/madd.c | 43 +
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/divu1.c | 48 +++
2 files changed, 49 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/divu1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate_init.inc.c | 59
1 file changed, 59 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index acab097820..07a6c81e68 100644
--- a/target/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 3 ++-
tests/tcg/mips/mipsr5900/mflohi1.c | 35 ++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsr5900/mflohi1.c
diff --git a/tests/tcg/mips/mipsr5900
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
--- a/tests/tcg/mips
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