Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8
regardless of whether virtualization (EL2) is enabled or not.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm
On Thu, Apr 23, 2015 at 6:34 AM, Edgar E. Iglesias edgar.igles...@gmail.com
wrote:
On Thu, Apr 23, 2015 at 12:28:43PM +0100, Peter Maydell wrote:
On 23 April 2015 at 12:24, Edgar E. Iglesias edgar.igles...@gmail.com
wrote:
Maybe we can consider YIELD instead of NOP when has_work() is true
On Thu, Apr 23, 2015 at 9:30 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 23 April 2015 at 15:26, Greg Bellows greg.bell...@linaro.org wrote:
Good catch Edgar, we shouldn't trap if we are going into a low-power
state.
You mean if we are not going into a low-power state.
Yes
On Thu, Apr 23, 2015 at 9:51 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 23 April 2015 at 15:41, Greg Bellows greg.bell...@linaro.org wrote:
Ok it sounds like the primary concern is the performance impact of
constantly trapping wfe to EL2 (in which case HCR must be set to cause
On Thu, Apr 23, 2015 at 5:10 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 23 April 2015 at 04:37, Edgar E. Iglesias edgar.igles...@gmail.com
wrote:
I had a comment on the trapping of WFX, I recall not checking for
has_work was causing a lot of exception round-trips when running
. This is id_pfr1[7:4].
+ * registers as well. These are id_pfr1[7:4] and
id_aa64pfr0[15:12].
*/
cpu-id_pfr1 = ~0xf0;
+cpu-id_aa64pfr0 = ~0xf000;
}
register_cp_regs_for_features(cpu);
--
2.3.4
Reviewed-by: Greg Bellows greg.bell...@linaro.org
Extend the ARM disassemble context to take a target exception EL instead of a
boolean enable. This change reverses the polarity of the check making a value
of 0 indicate floating point enabled (no exception).
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/cpu.h | 63
code from arm_excp_target_el() was merged in where needed and the
function removed.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Remove need for MAX in aarch64_cpu_do_interrupt. Other changed eliminated
the need for it,
---
target-arm/cpu.c| 61
Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the
current EL. Support includes using the different TCR format as well as checks to
insure TTBR1 is not used when in EL2 or EL3.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 45
Adds a utility function for creating a WFx exception syndrome
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/internals.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/internals.h b/target-arm
Add support for trapping WFI and WFE instructions to the proper EL when
SCTLR/SCR/HCR settings apply.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Replace check loop with simpler if checks.
- Changed WFx syncdrome function to take bool
- Changed return of uint32_t to int
Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 24 +++-
1 file changed, 19 insertions(+), 5
zero entries
- Broke out TCR changes into their own patch and added support for handling the
lack of TTBR1
- Simplified wfx checking
- General comment cleanup
Greg Bellows (9):
target-arm: Add exception target el infrastructure
target-arm: Extend helpers to route exceptions
target-arm: Update
Adds CPTR_EL2/3 system registers definitions and access function.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v2 - v3
- Broke out cptr and cpacr access functions
- Added HCPTR register entry as alias of CPTR_EL2
- Added HCPTR and CPTR_EL2 no_el2 register entries.
- Fixed cptr_access
Updated the various helper routines to set the target EL as needed using a
dedicated function.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Add utility function for determining the target exception EL.
- Replaced uses of MAX with the above function when setting the target
for callers to specify
the EL to which the exception should be routed. Extended the helper to set
the newly added CPU state exception target el.
Added a function for setting the target exception EL and updated calls to
helpers
to call it.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
On Wed, Apr 22, 2015 at 1:16 PM, Sergey Fedorov serge.f...@gmail.com
wrote:
On 22.04.2015 10:09, Greg Bellows wrote:
Add a utility function for choosing the correct TTBR system register
based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg
On Thu, Apr 16, 2015 at 12:51 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 March 2015 at 19:10, Greg Bellows greg.bell...@linaro.org wrote:
Updated the various helper routines to set the target EL as needed.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm
On Thu, Apr 16, 2015 at 1:00 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 March 2015 at 19:10, Greg Bellows greg.bell...@linaro.org wrote:
Adds CPTR_EL2/3 system registers definitions and access function.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm
On Thu, Apr 16, 2015 at 1:03 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 March 2015 at 19:10, Greg Bellows greg.bell...@linaro.org wrote:
Add a utility function for choosing the correct TTBR system register
based on
the specified MMU index. Add use of function on physical
On Thu, Apr 16, 2015 at 1:22 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 March 2015 at 19:10, Greg Bellows greg.bell...@linaro.org wrote:
Add support for trapping WFI and WFE instructions to the proper EL when
SCTLR/SCR/HCR settings apply.
Signed-off-by: Greg Bellows
On Thu, Apr 16, 2015 at 12:50 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 March 2015 at 19:10, Greg Bellows greg.bell...@linaro.org wrote:
Add a CPU state exception target EL field that will be used for
communicating
the EL to which an exception should be routed.
Add
On Thu, Apr 16, 2015 at 12:52 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 March 2015 at 19:10, Greg Bellows greg.bell...@linaro.org wrote:
Updated the interrupt handling to utilize and report through the target
EL
exception field. This includes consolidating and cleaning up
GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement
Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Change GICState security extension property from a uint8 type to bool
---
hw/intc/arm_gic.c
aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Fix issue with EOIR writes involving AckCtl. AckCtl is ignored on EOIR
group 1 interrupts when non-secure. Group 1 interrupts are only ignored when
secure and AckCTl is clear.
---
hw/intc/arm_gic.c | 15
.
EnableGroup0 (Bit [1]) in GICv1 is IMPDEF. Since this bit (Enable
Non-secure) is present in the integrated IC of the Cortex-A9 MPCore,
which implements the GICv1 profile, we support this bit in GICv1 too.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Rework gic_set_cpu_control() and gic_get_cpu_control() to close gap on
handling GICv1 wihtout security extensions.
- Fix use of incorrect control index in update.
---
hw/intc/arm_gic.c| 82
From: Fabian Aggeler aggel...@ethz.ch
Grouping (GICv2) and Security Extensions change the behaviour of reads
of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/intc
access to a register.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/intc/arm_gic.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index cdf7408..e0bce6e 100644
--- a/hw/intc/arm_gic.c
+++ b
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Fix issue in gic_update_with_grouping() using the wrong combination of
flag and CPU control bank for checking if group 1 interrupts are enabled.
---
hw/intc/arm_gic.c | 87 +-
hw
Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Fix issue in gic_acknowledge_irq() where the GICC_CTLR_S_ACK_CTL flag is
applied without first checking whether the read is secure or non-secure.
Secure reads of IAR when AckCtl is 0 return a spurious ID
/arm_gic: add gic_update() for grouping
Greg Bellows (1):
hw/arm/virt.c: Wire FIQ between CPU GIC
hw/arm/vexpress.c| 2 +
hw/arm/virt.c| 2 +
hw/intc/arm_gic.c| 498 ---
hw/intc/arm_gic_common.c
From: Fabian Aggeler aggel...@ethz.ch
For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/intc/arm_gic.c | 17
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/arm/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 565f573..f3326cf 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -386,6
From: Fabian Aggeler aggel...@ethz.ch
Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/intc/arm_gic.c| 3 +++
include/hw/intc
.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Fix ABPR read handling when security extensions are not present
- Fix BPR write to take into consideration the minimum value written to ABPR
and restrict BPR-ABPR mirroring to GICv2
From: Fabian Aggeler aggel...@ethz.ch
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/arm/vexpress.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/vexpress.c b/hw
of the existence of
Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v1 - v2
- Add clarifying comments to gic_dist_readb/writeb on interrupt group register
update
- Swap GIC_SET_GROUP0/1 macro logic. Setting
From: Fabian Aggeler aggel...@ethz.ch
GICs with Security Extensions restrict the non-secure view of the
interrupt priority and priority mask registers.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/intc/arm_gic.c | 66
From: Fabian Aggeler aggel...@ethz.ch
Prepare to split gic_update() in two functions, one for GICs with
interrupt grouping and one without grouping (existing).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/intc/arm_gic.c | 11
Add support for trapping WFI and WFE instructions to the proper EL when
SCTLR/SCR/HCR settings apply.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/op_helper.c | 75 +++---
1 file changed, 71 insertions(+), 4 deletions(-)
diff
Adds a utility function for creating a WFx exception syndrome
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/internals.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/internals.h b/target-arm/internals.h
index bb171a7..8dc2e2b 100644
--- a/target-arm
code from arm_excp_target_el() was merged in where needed and the
function removed.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/cpu.c| 61 +
target-arm/cpu.h| 7 +++---
target-arm/helper-a64.c | 2 +-
target
Adds CPTR_EL2/3 system registers definitions and access function.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/cpu.h| 18 +-
target-arm/helper.c | 43 ++-
2 files changed, 59 insertions(+), 2 deletions(-)
diff
Updated the various helper routines to set the target EL as needed.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/op_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 72a973a..aa175b5 100644
--- a/target
Initial patchset adding support for trapping to an EL other than EL1. Support
includes changes to interfaces to allow specification of the target EL. Also
includes the addition of the ARMv8 CPTR system registers used for controlling
the trapping of features.
Greg Bellows (7):
target-arm: Add
CPU state exception target el. Updated calls to helpers to
include target EL, minimally the current el, which gets upgraded as needed.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/cpu.h | 1 +
target-arm/helper.h| 2 +-
target-arm/op_helper.c | 3
Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 44
1 file changed, 32
On Mon, Mar 23, 2015 at 12:05 PM, Alex Bennée alex.ben...@linaro.org wrote:
From: Peter Maydell peter.mayd...@linaro.org
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env-banked_spsr[1]
On Tue, Mar 17, 2015 at 10:26 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
On 17 March 2015 at 17:24, Greg Bellows greg.bell...@linaro.org wrote:
On Tue, Mar 10, 2015 at 12:18 PM, Peter Maydell
peter.mayd...@linaro.org wrote:
The A32 encoding of LDM distinguishes LDM (user) from LDM
);
}
-if ((insn (1 22)) !user) {
+if (exc_return) {
/* Restore CPSR from SPSR. */
tmp = load_cpu_field(spsr);
gen_set_cpsr(tmp, CPSR_ERET_MASK);
--
1.9.1
Reviewed-by: Greg Bellows greg.bell...@linaro.org
On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée alex.ben...@linaro.org wrote:
For migration to work we need to sync all of the register state. This is
especially noticeable when GCC starts using FP registers as spill
registers even with integer programs.
Signed-off-by: Alex Bennée
.
+ */
uint32_t spsr;
/* Banked registers. */
--
2.3.0
Otherwise...
Reviewed-by: Greg Bellows greg.bell...@linaro.org
On Mon, Mar 9, 2015 at 8:26 AM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Wed, Mar 04, 2015 at 02:35:52PM +, Alex Bennée wrote:
From: Christoffer Dall christoffer.d...@linaro.org
The current code was negatively indexing the cpu state array and not
synchronizing banked spsr
On Wed, Mar 4, 2015 at 8:35 AM, Alex Bennée alex.ben...@linaro.org wrote:
While observing KVM traces I can see additional IRQ calls on pretty much
every MMIO access which is just plain inefficient. Only update the QEMU
IRQ level if something has actually changed from last time. Otherwise we
, strerror(ret));
+return -1;
+}
+}
+#endif
} else {
if (!write_list_to_cpustate(cpu)) {
return -1;
--
2.3.1
Besides these the above nits...
Reviewed-by: Greg Bellows greg.bell...@linaro.org
, translate_priority);
--
2.3.1
Reviewed-by: Greg Bellows greg.bell...@linaro.org
Just saw that Ard sent out a similar fix. Disregard this patch if we
decide to go with his (
1425402380-10488-1-git-send-email-ard.biesheu...@linaro.org).
Greg
On Tue, Mar 3, 2015 at 1:02 PM, Greg Bellows greg.bell...@linaro.org
wrote:
Fixes issue when combining CPU features and smp
Fixes issue when combining CPU features and smp. The issue is caused by
parse_feature's use of strtok which modifies the input feature string that is
needed for each smp CPU pass. This patch restores the feature string for each
pass.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
hw/arm
fix...
Reviewed-by: Greg Bellows greg.bell...@linaro.org
property handling in virt.c
- Removed unnecessary kernel load changes
Greg Bellows (4):
target-arm: Add CPU property to disable AArch64
target-arm: Add feature parsing to virt
target-arm: Add 32/64-bit register sync
target-arm: Add AArch32 guest support to KVM64
hw/arm/virt.c
Added machvirt parsing of feature keywords added to the -cpu command line
option. Parsing occurs during machine initialization.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v3 - v4
- Fix misspelling
v1 - v2
- Fix multiple property
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v7 - v8
- Fix dynamic cast object
v4 - v5
- Fix target check
v3 - v4
- Add check that to make sure KVM64 is only being
disabled.
$ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off
Also adds stripping of features from CPU model string in acquiring the ARM CPU
by name.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v4 - v5
- Fix error
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v6 - v7
On Thu, Feb 12, 2015 at 5:10 PM, Edgar E. Iglesias edgar.igles...@gmail.com
wrote:
On Thu, Feb 12, 2015 at 02:49:06PM +0800, Greg Bellows wrote:
Added support for running an AArch32 guest on a AArch64 KVM host.
Support has
only been added to the QEMU machvirt machine. The addition of CPU
));
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
--
1.9.1
Reviewed-by: Greg Bellows greg.bell...@linaro.org
disabled.
$ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off
Also adds stripping of features from CPU model string in acquiring the ARM CPU
by name.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v4 - v5
- Fix error message.
v3 - v4
- Switch from using strtok
interrupt handler setting of aarch64
v1 - v2
- Replaced custom property parsing with use of generic CPU property parser
- Added CPU property registration
- Fixed mulitple property handling in virt.c
- Removed unnecessary kernel load changes
Greg Bellows (4):
target-arm: Add CPU property to disable
Added machvirt parsing of feature keywords added to the -cpu command line
option. Parsing occurs during machine initialization.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v3 - v4
- Fix misspelling
v1 - v2
- Fix multiple property
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v4 - v5
- Rework sync routines a bit more.
v3 - v4
- Rework
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v4 - v5
- Fix target check
v3 - v4
- Add check that to make sure KVM64 is only being used on AArch64 family
unnecessary kernel load changes
Greg Bellows (4):
target-arm: Add CPU property to disable AArch64
target-arm: Add feature parsing to virt
target-arm: Add 32/64-bit register sync
target-arm: Add AArch32 guest support to KVM64
hw/arm/virt.c | 20 -
target-arm/cpu.c| 5
disabled.
$ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off
Also adds stripping of features from CPU model string in acquiring the ARM CPU
by name.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v4 - v5
- Fix error
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v4 - v5
- Fix target check
v3 - v4
- Add check that to make sure
disabled.
$ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off
Also adds stripping of features from CPU model string in acquiring the ARM CPU
by name.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v4 - v5
- Fix error
Greg Bellows (4):
target-arm: Add CPU property to disable AArch64
target-arm: Add feature parsing to virt
target-arm: Add 32/64-bit register sync
target-arm: Add AArch32 guest support to KVM64
hw/arm/virt.c | 20 -
target-arm/cpu.c| 5 +-
target-arm/cpu.h
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v5 - v6
- Add r14 set in 32_to_64
- Reorder conditionals
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v4 - v5
- Fix target check
v3 - v4
- Add check that to make sure
Added machvirt parsing of feature keywords added to the -cpu command line
option. Parsing occurs during machine initialization.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v3 - v4
- Fix misspelling
v1 - v2
- Fix multiple property
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v6 - v7
Added machvirt parsing of feature keywords added to the -cpu command line
option. Parsing occurs during machine initialization.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v3 - v4
- Fix misspelling
v1 - v2
- Fix multiple property
On Tue, Feb 10, 2015 at 10:03 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 10 February 2015 at 10:50, Greg Bellows greg.bell...@linaro.org
wrote:
Adds registration and get/set functions for enabling/disabling the
AArch64
execution state on AArch64 CPUs. By default AArch64
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v3 - v4
- Rework sync routines to cover various exception
disabled.
$ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off
Also adds stripping of features from CPU model string in acquiring the ARM CPU
by name.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v3 - v4
- Switch from using strtok to g_strsplit
- Add disablement
Added machvirt parsing of feature keywords added to the -cpu command line
option. Parsing occurs during machine initialization.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
v3 - v4
- Fix misspelling
v1 - v2
- Fix multiple property
interrupt handler setting of aarch64
v1 - v2
- Replaced custom property parsing with use of generic CPU property parser
- Added CPU property registration
- Fixed mulitple property handling in virt.c
- Removed unnecessary kernel load changes
Greg Bellows (4):
target-arm: Add CPU property to disable
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
v3 - v4
- Add check that to make sure KVM64 is only being used on AArch64 family of
machines.
- Relocate register sync
On Tue, Feb 10, 2015 at 10:13 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 10 February 2015 at 10:50, Greg Bellows greg.bell...@linaro.org
wrote:
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions
On Tue, Feb 10, 2015 at 10:16 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 10 February 2015 at 10:50, Greg Bellows greg.bell...@linaro.org
wrote:
Add 32-bit to/from 64-bit register synchronization on register gets and
puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off
On Fri, Feb 6, 2015 at 8:34 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
This patchset fixes a collection of warnings emitted by the clang
undefined behaviour sanitizer in the course of booting an AArch64
Linux guest to a shell prompt. These are all various kinds of bad
shift (shifting
On Tue, Feb 3, 2015 at 12:54 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 January 2015 at 23:58, Greg Bellows greg.bell...@linaro.org wrote:
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions
On Tue, Feb 3, 2015 at 12:54 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 January 2015 at 23:58, Greg Bellows greg.bell...@linaro.org wrote:
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions
On Tue, Feb 3, 2015 at 3:21 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Tue, Feb 3, 2015 at 10:15 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 3 February 2015 at 19:14, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 January 2015 at 23:58, Greg Bellows greg.bell
On Tue, Feb 3, 2015 at 1:14 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 January 2015 at 23:58, Greg Bellows greg.bell...@linaro.org wrote:
Adds registration and get/set functions for enabling/disabling the
AArch64
execution state on AArch64 CPUs. By default AArch64 execution
;
+a = float64_squash_input_denormal(a, fpst);
+b = float64_squash_input_denormal(b, fpst);
+
a = float64_chs(a);
if ((float64_is_infinity(a) float64_is_zero(b)) ||
(float64_is_infinity(b) float64_is_zero(a))) {
--
1.9.1
Reviewed-by: Greg Bellows
{
-return get_phys_addr_v5(env, address, access_type, is_user,
phys_ptr,
+return get_phys_addr_v5(env, address, access_type, mmu_idx,
phys_ptr,
prot, page_size);
}
}
--
1.9.1
Reviewed-by: Greg Bellows greg.bell...@linaro.org
On Wed, Jan 28, 2015 at 4:30 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 28 January 2015 at 21:37, Greg Bellows greg.bell...@linaro.org wrote:
+/* Return true if the translation regime is using LPAE format page
tables
*/
+static inline bool regime_using_lpae_format(CPUARMState
On Wed, Jan 28, 2015 at 4:34 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 28 January 2015 at 21:57, Greg Bellows greg.bell...@linaro.org wrote:
After getting through patch 9, I wonder if the TB NS bit can also be
removed
as it is implied in the MMU index.
No, because for a 32-bit
On Fri, Jan 23, 2015 at
12:20 PM, Peter Maydell peter.mayd...@linaro.org wrote:
Now we have the mmu_idx in get_phys_addr(), use it correctly to
determine the behaviour of virtual to physical address translations,
rather than using just an is_user flag and the current CPU state.
Some TODO
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