On Thu, 2 Nov 2023 10:24:28 +1000
Gavin Shan wrote:
> From: Philippe Mathieu-Daudé
>
> For target/alpha, the default CPU model name is "ev67". The default
> CPU model is used when no matching CPU model is found. The conditions
> to fall back to the default CPU model can be combined so that
On Thu, 2 Nov 2023 10:24:29 +1000
Gavin Shan wrote:
> From: Philippe Mathieu-Daudé
>
> Let CPUClass::class_by_name() handlers to return abstract classes,
> and filter them once in the public cpu_class_by_name() method.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Gavin Shan
>
On Fri, 3 Nov 2023 15:26:22 +
Peter Maydell wrote:
> On Fri, 3 Nov 2023 at 15:21, Peter Maydell wrote:
> >
> > From: Udo Steinberg
> >
> > Documentation for using the GAS in ACPI tables to report debug UART
> > addresses at
> >
On Fri, 13 Oct 2023 11:51:24 +0100
Salil Mehta wrote:
> ACPI GED(as described in the ACPI 6.2 spec) can be used to generate ACPI
> events
> when OSPM/guest receives an interrupt listed in the _CRS object of GED. OSPM
> then maps or demultiplexes the event by evaluating _EVT method.
>
> This
On Fri, 13 Oct 2023 11:51:25 +0100
Salil Mehta wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based
> on
> PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects
being placed in PCI0 context is no the
On Fri, 13 Oct 2023 11:51:27 +0100
Salil Mehta wrote:
> ACPI GED shall be used to convey to the guest kernel about any CPU
> hot-(un)plug
> events. Therefore, existing ACPI GED framework inside QEMU needs to be
> enhanced
> to support CPU hotplug state and events.
>
This is a part of hw
On Fri, 13 Oct 2023 11:51:23 +0100
Salil Mehta wrote:
> ACPI CPU hotplug related initialization should only happen if ACPI_CPU_HOTPLUG
> support has been enabled for particular architecture. Add
> cpu_hotplug_hw_init()
> stub to avoid compilation break.
merge this with 4/9 that actually
On Fri, 13 Oct 2023 11:51:21 +0100
Salil Mehta wrote:
> KVM vCPU creation is done once during the initialization of the VM when Qemu
> thread is spawned. This is common to all the architectures.
is it really true fox x86?
>
>
On Wed, 18 Oct 2023 18:38:33 +0100
Salil Mehta wrote:
> Hello,
> Can we assume that every machine type will have all the features which a
> GED Device can multiplex present together? like will Memory and CPU
> Hotplug makes sense for all the type of machines?
>
> If answer is no, then
On Sat, 21 Oct 2023 00:54:56 +0100
Salil Mehta wrote:
> Hi Bernhard,
>
> On 19/10/2023 11:33, Bernhard Beschow wrote:
> >
> >
> > Am 18. Oktober 2023 17:38:33 UTC schrieb Salil Mehta
> > :
> >> Hello,
> >
> > Hi Salil,
> >
> >> Can we assume that every machine type will have all the
On Fri, 13 Oct 2023 11:51:20 +0100
Salil Mehta wrote:
> Virtual CPU hotplug support is being added across various architectures[1][3].
> This series adds various code bits common across all architectures:
>
> 1. vCPU creation and Parking code refactor [Patch 1]
> 2. Update ACPI GED framework to
On Wed, 25 Oct 2023 09:54:07 +
Salil Mehta wrote:
> > From: David Hildenbrand
> > Sent: Wednesday, October 25, 2023 10:32 AM
> > To: Salil Mehta ; Igor Mammedov
> > ; Salil Mehta
> >
> > On 25.10.23 11:16, Salil Mehta wrote:
> > > Hi Igor,
&g
On Wed, 18 Oct 2023 17:48:36 +0100
Salil Mehta wrote:
> Hi Alex,
>
> On 18/10/2023 16:41, Alex Bennée wrote:
> >
> > Salil Mehta writes:
> >
> >> Hello,
> >>
> >> Came across below code excerpt in x86/microvm code and wanted to know
> >> why 'has_hotpluggable_cpus' flag has been set to
On Wed, 18 Oct 2023 09:32:47 +0100
David Woodhouse wrote:
> On Wed, 2023-10-18 at 09:32 +0200, Igor Mammedov wrote:
> > On Mon, 16 Oct 2023 16:19:08 +0100
> > David Woodhouse wrote:
> >
> > > From: David Woodhouse
> > >
> >
> &g
On Mon, 16 Oct 2023 16:19:08 +0100
David Woodhouse wrote:
> From: David Woodhouse
>
is this index a user (guest) visible?
> There's no need to force the user to assign a vdev. We can automatically
> assign one, starting at xvda and searching until we find the first disk
> name that's unused.
On Tue, 19 Sep 2023 15:12:13 +0800
Zhao Liu wrote:
> Hi Igor,
>
> On Fri, Sep 15, 2023 at 03:29:07PM +0200, Igor Mammedov wrote:
> > Date: Fri, 15 Sep 2023 15:29:07 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH 15/16] tests: bios-tables-test: Add test f
On Thu, 14 Sep 2023 19:45:59 -0700
wrote:
> From: Ankit Agrawal
>
> To add the memory in the guest as NUMA nodes, it needs the PXM node index
> and the total count of nodes associated with the memory. The range of
> proximity domains are communicated to the VM as part of the guest ACPI
>
On Fri, 15 Sep 2023 15:25:09 +0100
Jonathan Cameron via wrote:
> On Thu, 14 Sep 2023 19:45:56 -0700
> wrote:
>
> > From: Ankit Agrawal
> >
> > The CPU cache coherent device memory can be added as a set of
> > NUMA nodes distinct from the system memory nodes. The Qemu currently
> > do not
On Thu, 14 Sep 2023 19:45:58 -0700
wrote:
> From: Ankit Agrawal
>
> During bootup, Linux kernel parse the ACPI SRAT to determine the PXM ids.
> This allows for the creation of NUMA nodes for each unique id.
>
> Insert a series of the unique PXM ids in the VM SRAT ACPI table. The
> range of
On Fri, 15 Sep 2023 09:48:08 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Sep 05, 2023 at 02:56:46PM +0800, Zhao Liu wrote:
> > Hi Michael,
> >
> > On Fri, Sep 01, 2023 at 12:55:33PM +0300, Michael Tokarev wrote:
> > > Date: Fri, 1 Sep 2023 12:55:33 +0300
> > > From: Michael Tokarev
> > >
o
>confirm this field could correctly calculate threads per sockets.
>
> 2. Confirm that field calculation could correctly recognize the
>difference between "-smp maxcpus" and "-smp cpus".
>
> Suggested-by: Igor Mammedov
&g
o
>confirm this field could correctly calculate threads per sockets.
>
> 2. Confirm that field calculation could correctly recognize the
>difference between "-smp maxcpus" and "-smp cpus".
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
Ack
34c3 ("hw/smbios: Fix
> core count in type4"), add the "die" level in "-smp" as the more
> general topology case.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
Acked-by: Igor Mammedov
PS:
I'd still explain in commit message relations betw
On Fri, 25 Aug 2023 11:36:07 +0800
Zhao Liu wrote:
copy/past mistake in subj?
shouldn't it be for 'smbios type4 count'?
> From: Zhao Liu
>
> Following the guidelines in tests/qtest/bios-tables-test.c, this
> is step 5 and 6.
>
> Changes in the tables:
> FACP:
>
> +/*
> + * Intel ACPI
On Fri, 25 Aug 2023 11:36:09 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
> type4").
>
> Test the core count field of type4 table for multiple sockets/dies case.
>
> Suggested-by: Igor M
On Fri, 25 Aug 2023 11:36:06 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
> calculation").
>
> Test the count of type4 tables for multiple sockets case.
>
> Suggested-by: Igor M
et_threads_per_socket()
>
> Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
> threads per socket").
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
Acked-by: Igor Mammedov
> ---
> tests/unit/test-smp-parse.c | 67 +++
On Fri, 8 Sep 2023 17:55:12 +0100
Daniel P. Berrangé wrote:
> On Fri, Sep 08, 2023 at 04:48:46PM +0200, Igor Mammedov wrote:
> > On Fri, 8 Sep 2023 14:45:24 +0200
> > Tim Wiederhake wrote:
> >
> > > Synchronizing the list of cpu features and models with
On Mon, 11 Sep 2023 11:43:00 +0200
Philippe Mathieu-Daudé wrote:
> On 11/9/23 01:28, Gavin Shan wrote:
> > Hi Philippe,
> >
> > On 9/8/23 21:22, Philippe Mathieu-Daudé wrote:
> >> Add a field to return the QOM type name of a CPU class.
> >>
> >> Signed-off-by: Philippe Mathieu-Daudé
> >> ---
On Fri, 8 Sep 2023 14:45:24 +0200
Tim Wiederhake wrote:
> Synchronizing the list of cpu features and models with qemu is a recurring
> task in libvirt. For x86, this is done by reading qom-list-properties for
> max-x86_64-cpu and manually filtering out everthing that does not look like
> a
On Fri, 8 Sep 2023 16:17:31 +0200
Igor Mammedov wrote:
> On Fri, 8 Sep 2023 14:45:26 +0200
> Tim Wiederhake wrote:
>
> > Fix a copy-paste-mistake in the FEAT_VMX_EPT_VIPD_CAPS cpuid leaf.
> > The mistake became apparent as there were two features with the same name
&
On Fri, 8 Sep 2023 14:45:27 +0200
Tim Wiederhake wrote:
> The mistake became apparent as there were two features with the same name
> in this cpuid leaf. The names are now in line with the documentation from
> https://kernel.org/doc/html/latest/virt/kvm/x86/cpuid.html
I'd describe what
On Fri, 8 Sep 2023 14:45:26 +0200
Tim Wiederhake wrote:
> Fix a copy-paste-mistake in the FEAT_VMX_EPT_VIPD_CAPS cpuid leaf.
> The mistake became apparent as there were two features with the same name
> in this cpuid leaf. The names are now in line with SDM volume 3, appendix A,
> section 10.
On Fri, 8 Sep 2023 14:45:25 +0200
Tim Wiederhake wrote:
> Add the missing feature names for two bits in the FEAT_VMX_EPT_VPID_CAPS
> cpuid leaf. "vmx-ept-uc" is currently unused, but "vmx-ept-wb" is enabled
> for multiple cpu models.
>
> Signed-off-by:
On Tue, 5 Sep 2023 16:43:54 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Sep 05, 2023 at 07:45:12PM +0200, Marcello Sylverster Bauer wrote:
> > Hi Michael,
> >
> > On 9/5/23 18:44, Michael S. Tsirkin wrote:
> > > On Tue, Sep 05, 2023 at 05:05:33PM +0200, Marcello Sylverster Bauer
> > > wrote:
On Wed, 30 Aug 2023 17:34:12 +1000
Gavin Shan wrote:
> Hi Igor,
>
> On 8/29/23 19:03, Igor Mammedov wrote:
> > On Tue, 29 Aug 2023 16:28:45 +1000
> > Gavin Shan wrote:
> >> On 8/29/23 00:46, Igor Mammedov wrote:
> >>> On Mon, 31 Jul 2
On Wed, 30 Aug 2023 10:03:33 +
"Liu, Jing2" wrote:
> Hi Cédric，
>
> On 8/29/2023 10:04 PM, Cédric Le Goater wrote:
> > On 8/22/23 09:29, Jing Liu wrote:
> > > Guests typically enable MSI-X with all of the vectors masked in the
> > > MSI-X vector table. To match the guest state of device,
On Tue, 1 Aug 2023 13:00:02 -0400
"Annie.li" wrote:
> Hi Igor,
>
> On 7/14/2023 10:04 AM, Igor Mammedov wrote:
> > On Fri, 7 Jul 2023 13:43:36 -0400
> > "Annie.li" wrote:
> >
> >> Hi Igor,
> >>
> >> Revisiting this th
On Tue, 22 Aug 2023 18:49:48 +0200
Thomas Huth wrote:
> The virtio-iommu device might be missing in the QEMU binary (e.g. in
> downstream RHEL builds), so let's better check for its availability first
> before using it.
>
> Signed-off-by: Thomas Huth
Acked-by: Igor Mammedov
On Tue, 29 Aug 2023 16:28:45 +1000
Gavin Shan wrote:
> Hi Igor,
>
> On 8/29/23 00:46, Igor Mammedov wrote:
> > On Mon, 31 Jul 2023 15:07:30 +1000
> > Gavin Shan wrote:
> >> On 7/27/23 19:00, Igor Mammedov wrote:
> >>> On Thu, 27 Jul 2
On Mon, 31 Jul 2023 15:07:30 +1000
Gavin Shan wrote:
> On 7/27/23 19:00, Igor Mammedov wrote:
> > On Thu, 27 Jul 2023 15:16:18 +1000
> > Gavin Shan wrote:
> >
> >> On 7/27/23 09:08, Richard Henderson wrote:
> >>> On 7/25/23 17:32, Gav
On Mon, 28 Aug 2023 16:45:30 +0800
LIU Zhiwei wrote:
> Some times we want to know what is the really mean of one cpu option.
> For example, in RISC-V, we usually specify a cpu in this way:
> -cpu rv64,v=on
>
> If we don't look into the source code, we can't get the ISA extensions
> of this -cpu
On Fri, 11 Aug 2023 17:26:24 +0200
David Hildenbrand wrote:
[...]
> Nowadays, "-mem-path" always defaults to MAP_PRIVATE. For the original
> hugetlb use case, it's still good enough. For anything else, I'm not so
> sure.
We can deprecate -mem-path and direct users to use explicitly
defined
On Wed, 9 Aug 2023 21:20:48 +0800
"Wen, Qian" wrote:
> On 8/9/2023 7:14 PM, Igor Mammedov wrote:
> > On Wed, 9 Aug 2023 18:27:32 +0800
> > Qian Wen wrote:
> >
> >> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
> &g
On Mon, 7 Aug 2023 22:31:35 +0800
Zhao Liu wrote:
> Hi Igor,
>
> On Mon, Aug 07, 2023 at 12:11:29PM +0200, Igor Mammedov wrote:
> > Date: Mon, 7 Aug 2023 12:11:29 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH v2 2/3] hw/smbios: Fix thread count in type4
>
On Wed, 9 Aug 2023 18:27:32 +0800
Qian Wen wrote:
> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
> Vol2:
>
> Bits 23-16: Maximum number of addressable IDs for logical processors in
> this physical package.
>
> When launching the VM with -smp 256, the value written to
On Tue, 1 Aug 2023 15:38:32 -0400
Stefan Berger wrote:
> On 7/31/23 23:02, Joelle van Dyne wrote:
> > On Mon, Jul 17, 2023 at 6:42 AM Igor Mammedov wrote:
> >>
> >> On Fri, 14 Jul 2023 13:21:33 -0400
> >> Stefan Berger wrote:
> >>
On Mon, 7 Aug 2023 13:06:47 +0300
Michael Tokarev wrote:
> 07.08.2023 12:56, Igor Mammedov wrote:
> > On Sat, 5 Aug 2023 09:00:41 +0300
> > Michael Tokarev wrote:
[...]
> The whole thing - provided the preparational patch a1d027be95
> "machine: Add helpers to ge
On Sat, 5 Aug 2023 09:00:41 +0300
Michael Tokarev wrote:
> 05.08.2023 08:58, Michael Tokarev wrote:
>
> > 196ea60a73 hw/smbios: Fix core count in type4
> > 7298fd7de5 hw/smbios: Fix thread count in type4
> > d79a284a44 hw/smbios: Fix smbios_smp_sockets caculation
>
> plus this one:
>
>
On Thu, 20 Jul 2023 15:15:13 +0800
xianglai li wrote:
> Turn on CPU hot-(un)plug custom for loongarch in the configuration file
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
> Cc: Ani Sinha
> Cc: Paolo Bonzini
>
plug
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
> Cc: Ani Sinha
> Cc: Paolo Bonzini
> Cc: Richard Henderson
> Cc: Eduardo Habkost
> Cc: Marcel Apfelbaum
> Cc: "Philippe Mathieu-Daudé"
> Cc:
separate patches to introduce socket/core/thread support
with proper documentation/pointers to specs as to how arch_id
should be calculated.
And once that is ready, add hotplug on top of it.
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Ig
On Thu, 20 Jul 2023 15:15:09 +0800
xianglai li wrote:
> Introduce new functions to destroy CPU address space resources
s/functions/function/
> for cpu hot-(un)plug.
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
>
On Thu, 20 Jul 2023 15:15:11 +0800
xianglai li wrote:
> 1.Add the Unrealize function to the Loongarch CPU for cpu hot-(un)plug
> 2.Add CPU topology-related properties to the Loongarch CPU for cpu
> hot-(un)plug
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Micha
skimmed through, it looks good to me
see nit below
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
> Cc: Ani Sinha
> Cc: Paolo Bonzini
> Cc: Richard Henderson
> Cc: Eduardo Habkost
> Cc: Marcel Apfelbaum
> Cc: &quo
inerface of the build cpus AML
^^^ typo
> function to accept both IO/MEMORY type regions and update the _CRS object
> correspondingly.
try to reformat commit message to less than 80 character per line
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Mich
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
> Cc: Ani Sinha
> Cc: Paolo Bonzini
> Cc: Richard Henderson
> Cc: Eduardo Habkost
> Cc: Marcel Apfelbaum
> Cc: "Philippe Mathieu-Daudé"
> Cc: Yanan Wang
On Thu, 27 Jul 2023 16:29:19 +0530
Sunil V L wrote:
> On Mon, Jul 24, 2023 at 05:32:54PM +0200, Igor Mammedov wrote:
> > On Wed, 12 Jul 2023 22:09:37 +0530
> > Sunil V L wrote:
> >
> > > PCIe High MMIO base is actually dynamic and fixed at
> > &g
On Thu, 27 Jul 2023 15:16:18 +1000
Gavin Shan wrote:
> On 7/27/23 09:08, Richard Henderson wrote:
> > On 7/25/23 17:32, Gavin Shan wrote:
> >> -static const char *q800_machine_valid_cpu_types[] = {
> >> +static const char * const q800_machine_valid_cpu_types[] = {
> >>
On Wed, 26 Jul 2023 10:11:44 +0200
David Hildenbrand wrote:
> On 25.07.23 18:01, ThinerLogoer wrote:
> >
> > At 2023-07-25 19:42:30, "David Hildenbrand" wrote:
> >> Hi,
> >>
> >> patch subject should start with "softmmu/physmem: Open ..."
> >
> > Sorry I am newbie to the patch submission
On Tue, 25 Jul 2023 22:20:36 +0530
Sunil V L wrote:
> On Mon, Jul 24, 2023 at 05:18:59PM +0200, Igor Mammedov wrote:
> > On Wed, 12 Jul 2023 22:09:34 +0530
> > Sunil V L wrote:
> >
> > > The functions which add fw_cfg and virtio to DSDT are same for ARM
On Mon, 24 Jul 2023 16:14:22 +0100
Peter Maydell wrote:
> On Mon, 24 Jul 2023 at 16:06, Igor Mammedov wrote:
> > I've seen others asking why you print type name instead of shorter cpu-model
> > used on CLI. To do that would make you write a patch to implement reverse
> >
On Wed, 12 Jul 2023 22:09:37 +0530
Sunil V L wrote:
> PCIe High MMIO base is actually dynamic and fixed at
> run time based on the RAM configured. Currently, this is
> not part of the memmap and kept in separate static variable
> in virt.c. However, ACPI code also needs this information
> to
On Wed, 12 Jul 2023 22:09:34 +0530
Sunil V L wrote:
> The functions which add fw_cfg and virtio to DSDT are same for ARM
> and RISC-V. So, instead of duplicating in RISC-V, move them from
> hw/arm/virt-acpi-build.c to common aml-build.c.
>
> Signed-off-by: Sunil V L
> ---
>
On Tue, 18 Jul 2023 20:31:39 +1000
Gavin Shan wrote:
> Hi Igor,
>
> On 7/17/23 22:44, Igor Mammedov wrote:
> > On Fri, 14 Jul 2023 13:56:00 +0100
> > Peter Maydell wrote:
> >
> >> On Fri, 14 Jul 2023 at 12:50, Igor Mammedov wrote:
> >&
On Tue, 18 Jul 2023 16:11:42 +1000
Gavin Shan wrote:
> Hi Igor,
>
> On 7/14/23 22:07, Igor Mammedov wrote:
> > On Thu, 13 Jul 2023 15:45:00 +1000
> > Gavin Shan wrote:
> >
> >> The CPU type invalidation logic in machine_run_board_init() is
> &g
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
--- a/tests/qtest/bios
Expected change is that _ADR object is removed from
hostbridge descriptor in DSDT for PC and Q35 machines.
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 37 --
tests/data/acpi/pc/DSDT | Bin 6836 -> 6830 bytes
tests/d
.BSEL */
+Local0 [One] = ASUN /* \_SB_.PCI0.S18_.ASUN */
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 --
tests/data/acpi/pc/DSDT | Bin 6488 -> 6836 bytes
tests/data/acpi/pc/DSDT.acpierst|
hat having _ADR has a negative effects
OSes manage to tolerate that, but there is no point of
having it there. (only pc/q35 has it hostbridge description,
while others (microvm/arm) don't)
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 37 +
1 file changed, 37 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..8911b10650 100644
--- a/tests/qtest
e or shows incorrect value.
Fix it by doing assignment of BSEL/ASUN values to package
elements manually after package declaration.
Fix was tested with: WS2012r2, WS2022, RHEL9
Fixes: 467d099a2985 (x86: acpi: _DSM: use Package to pass parameters)
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-bui
, WS2012R2, WS2022, WinXPsp3
PS:
WinXP boots (but it doesn't expose device properties so I have no idea
how to check 'PCI Label Id' or if it's even supported there)
Igor Mammedov (6):
tests: acpi: x86: whitelist expected blobs
x86: acpi: workaround Windows not handling name references in Package
On Fri, 14 Jul 2023 11:49:03 -0700
Joelle van Dyne wrote:
> On Fri, Jul 14, 2023 at 11:41 AM Stefan Berger wrote:
> >
> >
> >
> > On 7/14/23 14:22, Stefan Berger wrote:
> > > On 7/14/23 13:04, Joelle van Dyne wrote:
> > >> On Fri, Jul 14, 2023 at 7:51 AM Stefan Berger
> > >> wrote:
> >
On Fri, 14 Jul 2023 00:09:26 -0700
Joelle van Dyne wrote:
> This SysBus variant of the CRB interface supports dynamically locating
> the MMIO interface so that Virt machines can use it. This interface
> is currently the only one supported by QEMU that works on Windows 11
> ARM64. We largely
On Fri, 14 Jul 2023 10:29:31 -0700
Joelle van Dyne wrote:
> On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger wrote:
> >
> >
> >
> >
> > I don't know whether we would want multiple devices. tpm_find() usage is
> > certainly not prepared for multiple devices.
> Sorry, "multiple TPM interfaces"
On Fri, 14 Jul 2023 00:09:23 -0700
Joelle van Dyne wrote:
> TPM needs to know its own base address in order to generate its DSDT
> device entry.
>
> Signed-off-by: Joelle van Dyne
> ---
> hw/arm/virt.c | 37 +
> 1 file changed, 37 insertions(+)
>
> diff
On Fri, 14 Jul 2023 00:09:21 -0700
Joelle van Dyne wrote:
> Since this device is gated to only build for targets with the PC
> configuration, we should use the ISA bus like with TPM TIS.
does it affect migration in any way?
From guest pov it looks like there a new ISA device will appear
and
On Fri, 14 Jul 2023 13:21:33 -0400
Stefan Berger wrote:
> On 7/14/23 03:09, Joelle van Dyne wrote:
> > This logic is similar to TPM TIS ISA device. Since TPM CRB can only
> > support TPM 2.0 backends, we check for this in realize.
> >
> > Signed-off-by: Joelle van Dyne
>
> This patch
On Fri, 14 Jul 2023 13:56:00 +0100
Peter Maydell wrote:
> On Fri, 14 Jul 2023 at 12:50, Igor Mammedov wrote:
> >
> > On Thu, 13 Jul 2023 12:59:55 +0100
> > Peter Maydell wrote:
> >
> > > On Thu, 13 Jul 2023 at 12:52, Marcin Juszkiewicz
> > > wr
On Mon, 17 Jul 2023 10:32:33 +0200
Claudio Fontana wrote:
> Hello Igor,
>
> thanks for getting back to me on this,
>
> On 7/14/23 11:51, Igor Mammedov wrote:
> > On Wed, 5 Jul 2023 10:12:40 +0200
> > Claudio Fontana wrote:
> >
> >> Hi
On Fri, 7 Jul 2023 13:43:36 -0400
"Annie.li" wrote:
> Hi Igor,
>
> Revisiting this thread and have more questions, please clarify, thank you!
>
> On 9/20/2021 3:53 AM, Igor Mammedov wrote:
> > On Fri, 6 Aug 2021 16:18:09 -0400
> > &qu
On Thu, 13 Jul 2023 15:45:00 +1000
Gavin Shan wrote:
> The CPU type invalidation logic in machine_run_board_init() is
> independent enough. Lets factor it out into helper validate_cpu_type().
> Since we're here, the relevant comments are improved a bit.
>
> No functional change intended.
>
>
On Thu, 13 Jul 2023 15:45:01 +1000
Gavin Shan wrote:
> There is a generic CPU type invalidation in machine_run_board_init()
^
using that throughout the series is confusing to me.
Perhaps use original phrase 'valid cpu types' with appropriate rephrasing
would be
On Thu, 13 Jul 2023 12:59:55 +0100
Peter Maydell wrote:
> On Thu, 13 Jul 2023 at 12:52, Marcin Juszkiewicz
> wrote:
> >
> > W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
> >
> > > I see this isn't a change in this patch, but given that
> > > what the user specifies is not
On Wed, 5 Jul 2023 10:12:40 +0200
Claudio Fontana wrote:
> Hi all, partially resurrecting an old thread.
>
> I've seen how for Epyc something special was done in the past in terms of
> apicid assignments based on topology, which was then reverted apparently,
> but I wonder if something more
.
>
>Similar to core count, also use a new helper to fix this.
>
> [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg05402.html
> [2]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06071.html
> [3]: https://mail.gnu.org/archive/html/qemu-devel/2023-0
On Tue, 4 Jul 2023 19:20:00 +0530
Ani Sinha wrote:
> > On 04-Jul-2023, at 6:18 PM, Igor Mammedov wrote:
> >
> > On Tue, 4 Jul 2023 21:02:09 +0900
> > Akihiko Odaki wrote:
> >
> >> On 2023/07/04 20:59, Ani Sinha wrote:
> >>>
> &
On Tue, 4 Jul 2023 21:22:14 +0900
Akihiko Odaki wrote:
> The current implementers of ARI are all SR-IOV devices. The ARI next
> function number field is undefined for VF .
^
add a reference to a spec (spec name, rev, chapter) where it's declared
so
On Tue, 4 Jul 2023 21:02:09 +0900
Akihiko Odaki wrote:
> On 2023/07/04 20:59, Ani Sinha wrote:
> >
> >
> >> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
> >>
> >> On 2023/07/04 20:25, Ani Sinha wrote:
> >>> PCI Express ports only have one slot, so PCI Express devices can only be
> >>>
On Tue, 4 Jul 2023 20:50:49 +0900
Akihiko Odaki wrote:
> On 2023/07/04 20:38, Igor Mammedov wrote:
> > On Sat, 1 Jul 2023 16:28:30 +0900
> > Akihiko Odaki wrote:
> >
> >> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
> >>> On Fri, Jun 30, 202
On Tue, 4 Jul 2023 16:55:55 +0530
Ani Sinha wrote:
> This change is cosmetic. A comment is added explaining why we need to check
> for
> the availability of function 0 when we hotplug a device.
>
> CC: m...@redhat.com
> Signed-off-by: Ani Sinha
> ---
> hw/pci/pci.c | 12 +---
> 1
On Sun, 2 Jul 2023 21:02:27 +0900
Akihiko Odaki wrote:
> The current implementers of ARI are all SR-IOV devices. The ARI next
> function number field is undefined for VF. The PF should end the linked
> list formed with the field by specifying 0.
this should also describe compat behavior
On Sat, 1 Jul 2023 16:28:30 +0900
Akihiko Odaki wrote:
> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
> > On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
> >> On 2023/06/30 19:37, Ani Sinha wrote:
> >>>
> >>>
> On 30-Jun-2023, at 3:30 PM, Michael S. Tsirkin wrote:
>
a pcie-to-pci bridge
> which can then be directly attached to the root bus (pcie.0).
>
> Fix the test and simplify it.
>
> CC: m...@redhat.com
> CC: imamm...@redhat.com
> CC: Michael Labiuk
>
> Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
> ---
> test
On Tue, 27 Jun 2023 08:23:25 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Jun 27, 2023 at 01:58:49PM +0200, Igor Mammedov wrote:
> > On Tue, 27 Jun 2023 15:23:04 +0530
> > Ani Sinha wrote:
> >
> > > > On 27-Jun-2023, at 2:32 PM, Igor Mammedov wrote:
On Tue, 27 Jun 2023 15:23:04 +0530
Ani Sinha wrote:
> > On 27-Jun-2023, at 2:32 PM, Igor Mammedov wrote:
> >
> > On Mon, 26 Jun 2023 21:42:44 +0530
> > Ani Sinha wrote:
> >
> >> PCI Express ports only have one slot, so PCI Express devices can only be
On Fri, 16 Jun 2023 11:23:11 +0800
Tao Su wrote:
> The GraniteRapids CPU model mainly adds the following new features based
> on SapphireRapids:
>
> - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
> -
On Mon, 26 Jun 2023 21:42:44 +0530
Ani Sinha wrote:
> PCI Express ports only have one slot, so PCI Express devices can only be
> plugged into slot 0 on a PCIE port. Enforce it.
btw, previously you mentioned ARI.
So if we turn it on, wouldn't this patch actually become regression?
>
> CC:
On Mon, 26 Jun 2023 21:42:43 +0530
Ani Sinha wrote:
> The test attaches a SCSI controller to a non-zero slot and a pcie-to-pci
> bridge
> on slot 0 on the same pcie-root-port. Since a downstream device can be
> attached
> to a pcie-root-port only on slot 0, the above test configuration is not
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