On Tue, 4 Jul 2023 21:02:09 +0900
Akihiko Odaki wrote:
> On 2023/07/04 20:59, Ani Sinha wrote:
> >
> >
> >> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
> >>
> >> On 2023/07/04 20:25, Ani Sinha wrote:
> >>> PCI Express ports only have one slot, so PCI Express devices can only be
> >>>
On Tue, 4 Jul 2023 20:50:49 +0900
Akihiko Odaki wrote:
> On 2023/07/04 20:38, Igor Mammedov wrote:
> > On Sat, 1 Jul 2023 16:28:30 +0900
> > Akihiko Odaki wrote:
> >
> >> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
> >>> On Fri, Jun 30, 202
On Tue, 4 Jul 2023 16:55:55 +0530
Ani Sinha wrote:
> This change is cosmetic. A comment is added explaining why we need to check
> for
> the availability of function 0 when we hotplug a device.
>
> CC: m...@redhat.com
> Signed-off-by: Ani Sinha
> ---
> hw/pci/pci.c | 12 +---
> 1
On Sun, 2 Jul 2023 21:02:27 +0900
Akihiko Odaki wrote:
> The current implementers of ARI are all SR-IOV devices. The ARI next
> function number field is undefined for VF. The PF should end the linked
> list formed with the field by specifying 0.
this should also describe compat behavior
On Sat, 1 Jul 2023 16:28:30 +0900
Akihiko Odaki wrote:
> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
> > On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
> >> On 2023/06/30 19:37, Ani Sinha wrote:
> >>>
> >>>
> On 30-Jun-2023, at 3:30 PM, Michael S. Tsirkin wrote:
>
a pcie-to-pci bridge
> which can then be directly attached to the root bus (pcie.0).
>
> Fix the test and simplify it.
>
> CC: m...@redhat.com
> CC: imamm...@redhat.com
> CC: Michael Labiuk
>
> Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
> ---
> test
On Tue, 27 Jun 2023 08:23:25 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Jun 27, 2023 at 01:58:49PM +0200, Igor Mammedov wrote:
> > On Tue, 27 Jun 2023 15:23:04 +0530
> > Ani Sinha wrote:
> >
> > > > On 27-Jun-2023, at 2:32 PM, Igor Mammedov wrote:
On Tue, 27 Jun 2023 15:23:04 +0530
Ani Sinha wrote:
> > On 27-Jun-2023, at 2:32 PM, Igor Mammedov wrote:
> >
> > On Mon, 26 Jun 2023 21:42:44 +0530
> > Ani Sinha wrote:
> >
> >> PCI Express ports only have one slot, so PCI Express devices can only be
On Fri, 16 Jun 2023 11:23:11 +0800
Tao Su wrote:
> The GraniteRapids CPU model mainly adds the following new features based
> on SapphireRapids:
>
> - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
> -
On Mon, 26 Jun 2023 21:42:44 +0530
Ani Sinha wrote:
> PCI Express ports only have one slot, so PCI Express devices can only be
> plugged into slot 0 on a PCIE port. Enforce it.
btw, previously you mentioned ARI.
So if we turn it on, wouldn't this patch actually become regression?
>
> CC:
On Mon, 26 Jun 2023 21:42:43 +0530
Ani Sinha wrote:
> The test attaches a SCSI controller to a non-zero slot and a pcie-to-pci
> bridge
> on slot 0 on the same pcie-root-port. Since a downstream device can be
> attached
> to a pcie-root-port only on slot 0, the above test configuration is not
On Tue, 27 Jun 2023 13:54:23 +0800
Xiaoyao Li wrote:
> On 6/26/2023 8:56 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:10 +0800
> > Tao Su wrote:
> >
> >> From: Qian Wen
> >>
> >> Emerald Rapids (EMR) is the next generation of Xeon
On Tue, 27 Jun 2023 14:10:17 +0800
Xiaoyao Li wrote:
> On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:09 +0800
> > Tao Su wrote:
> >
> >> From: Lei Wang
> >>
> >> Latest stepping (8) of SapphireRapids has bit 13, 14 a
On Tue, 27 Jun 2023 12:27:19 +0800
Tao Su wrote:
> On Mon, Jun 26, 2023 at 02:39:15PM +0200, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:05 +0800
> > Tao Su wrote:
> >
> > > Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> > &g
On Mon, 26 Jun 2023 19:23:23 +0530
Ani Sinha wrote:
> The test attaches both a SCSI controller and a pcie-to-pci bridge on the same
> pcie-root-port on slot 0.
statement is right only for bridge, while it's still incorrect for storage part
(see add_scsi_controller/add_virtio_disk)
they try to
On Mon, 26 Jun 2023 09:53:40 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Jun 26, 2023 at 03:30:14PM +0200, Igor Mammedov wrote:
> > On Mon, 26 Jun 2023 18:13:05 +0530
> > Ani Sinha wrote:
> >
> > > The test attaches both a SCSI controller and
On Tue, 20 Jun 2023 18:39:54 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> Hi all,
>
> This is my v3 patch series based on 48ab886d3da4f ("Merge tag 'pull-
> target-arm-20230619' of https://git.linaro.org/people/pmaydell/qemu-arm
> into staging").
>
> Compared with v2 [1], v3 introduces 2
On Tue, 20 Jun 2023 18:39:57 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> From SMBIOS 3.0 specification, thread count field means:
>
> Thread Count is the total number of threads detected by the BIOS for
> this processor socket. It is a processor-wide count, not a
> thread-per-core count. [1]
>
id calculation errors caused by other modules miss
> topology changes.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
> ---
> v3:
> * The new patch to wrap the calculation of cores/threads per socket.
> ---
> include/hw/boards.h | 12
>
On Mon, 26 Jun 2023 18:13:05 +0530
Ani Sinha wrote:
> The test attaches both a SCSI controller and a pcie-to-pci bridge on the same
> pcie-root-port.
at slot addresses ...
> This is incorrect since only one downstream device can be
> attached to a pcie-root-port.
not true in case of
is possibly related to the same memory core bug.
>
> Link: https://gitlab.com/qemu-project/qemu/-/issues/360
> Signed-off-by: BALATON Zoltan
> Message-Id: <20230607200125.a9988746...@zero.eik.bme.hu>
> Reviewed-by: Michael S. Tsirkin
> Signed-off-by: Michael S. Tsirkin
So
On Fri, 16 Jun 2023 11:23:09 +0800
Tao Su wrote:
> From: Lei Wang
>
> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> fixes.
>
> Add version 2 of SapphireRapids CPU model with those bits enabled also.
On Fri, 16 Jun 2023 11:23:08 +0800
Tao Su wrote:
> Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
> disclosed for fixing security issues, so add those bit definitions
> and feature names.
>
> Signed-off-by: Tao Su
Reviewed-by: Igor Mammedov
> ---
>
On Fri, 16 Jun 2023 11:23:07 +0800
Tao Su wrote:
> MCDT_NO bit indicates HW contains the security fix and doesn't need to
> be mitigated to avoid data-dependent behaviour for certain instructions.
> It needs no hypervisor support. Treat it as supported regardless of what
> KVM reports.
>
>
On Fri, 16 Jun 2023 11:23:10 +0800
Tao Su wrote:
> From: Qian Wen
>
> Emerald Rapids (EMR) is the next generation of Xeon server processor
> after Sapphire Rapids (SPR).
>
> Currently, regarding the feature set that can be exposed to guest, there
> isn't any one new comparing with SPR cpu
On Fri, 16 Jun 2023 11:23:05 +0800
Tao Su wrote:
> Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> non-zero,
Can you clarify when/why that happens?
> guest may report wrong maximum number sub-leaves in leaf
> 07H. So add FEAT_7_1_EDX to adjust feature level.
>
> Fixes:
On Mon, 26 Jun 2023 17:01:29 +0530
Ani Sinha wrote:
> > On 26-Jun-2023, at 4:45 PM, Igor Mammedov wrote:
> >
> > On Thu, 22 Jun 2023 16:02:54 +0530
> > Ani Sinha wrote:
> >
> >> A SCSI controller can be attached to a pcie-to-pci bridge which in t
On Thu, 22 Jun 2023 16:02:54 +0530
Ani Sinha wrote:
> A SCSI controller can be attached to a pcie-to-pci bridge which in turn can be
> attached directly to the root bus (peie.0). There is no need to attach a
> pcie-root-port on the root bus in order to attach the pcie-ro-pci bridge.
> Fix it.
{
> Name (_ADR, Zero) // _ADR: Address
> }
> }
> }
>
> Device (SF8)
> {
> Name (_ADR, 0x001F) // _ADR: Address
> Operat
On Wed, 21 Jun 2023 19:37:21 +0530
Ani Sinha wrote:
> We are going to fix bio-tables-test in the next patch and hence need to
> make sure the acpi tests continue to pass.
>
> Signed-off-by: Ani Sinha
Acked-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test-allowed
inha
Reviewed-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index ed1c69cf01..47ba20b957 100644
> --- a/tests/qtest/bios-ta
On Fri, 23 Jun 2023 06:05:28 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Jun 07, 2023 at 03:57:16PM -0500, Suravee Suthikulpanit wrote:
> > Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> > (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> >
On Wed, 21 Jun 2023 13:24:42 -0400
Joel Upham wrote:
> On Wed, Jun 21, 2023 at 7:28 AM Igor Mammedov wrote:
>
> > On Tue, 20 Jun 2023 13:24:36 -0400
> > Joel Upham wrote:
> >
> > > On Q35 we still need to assign BSEL property to bus(es) for PCI device
> &
On Tue, 20 Jun 2023 13:24:57 -0400
Joel Upham wrote:
> Resetting pci devices after s3 causes guest freezes, as xen usually
> likes to handle resetting devices.
I'd prefer Xen side being fixed instead of hacking reset logic in qemu/q35.
> Signed-off-by: Joel Upham
> ---
> hw/acpi/ich9.c
On Tue, 20 Jun 2023 13:24:37 -0400
Joel Upham wrote:
> This patch allows to use ACPI PCI hotplug functionality for Xen on Q35.
> All added code depends on xen_enabled(), so no functionality change for
> non-Xen usage.
>
> We need to call the acpi_set_pci_info function from ich9_pm_init as well,
On Tue, 20 Jun 2023 13:24:36 -0400
Joel Upham wrote:
> On Q35 we still need to assign BSEL property to bus(es) for PCI device
> add/hotplug to work.
> Extend acpi_set_pci_info() function to support Q35 as well. This patch adds
> new (trivial)
> function find_q35() which returns root PCIBus
On Tue, 20 Jun 2023 12:48:05 +0530
Ani Sinha wrote:
> When a device has an upstream PCIE port, we can only use slot 0. Non-zero
> slots
> are invalid.
> This change ensures that we throw an error if the user
> tries to hotplug a device with an upstream PCIE port to a non-zero slot.
Isn't the
On Fri, 16 Jun 2023 13:06:06 +0530
Ani Sinha wrote:
> > On 15-Jun-2023, at 4:56 PM, Igor Mammedov wrote:
> >
> > On Thu, 15 Jun 2023 10:46:45 +0530
> > Ani Sinha wrote:
> >
> >> PCIE root ports and other upstream ports only allow one device on
On Thu, 15 Jun 2023 10:46:45 +0530
Ani Sinha wrote:
> PCIE root ports and other upstream ports only allow one device on slot 0.
> When hotplugging a device on a pcie root port, make sure that the device
> address passed always represents slot 0. Any other slot value would be
> illegal on a root
On Wed, 14 Jun 2023 18:01:50 +0530
Ani Sinha wrote:
> PCIE root ports only allow one device on slot 0/function 0. When hotplugging a
> device on a pcie root port, make sure that the device address passed is
> always 0x00 that represents slot 0 and function 0. Any other slot value and
> function
On Tue, 13 Jun 2023 13:07:17 +0200 (CEST)
BALATON Zoltan wrote:
> On Tue, 13 Jun 2023, Michael S. Tsirkin wrote:
> > On Tue, Jun 13, 2023 at 09:46:53AM +0200, Bernhard Beschow wrote:
> >> On Mon, Jun 12, 2023 at 3:01 PM Igor Mammedov wrote:
> >>
> >>
On Mon, 12 Jun 2023 17:49:10 +
Bernhard Beschow wrote:
> Am 12. Juni 2023 15:21:19 UTC schrieb Igor Mammedov :
> >On Mon, 12 Jun 2023 16:51:55 +0200
> >Igor Mammedov wrote:
> >
> >> On Sun, 11 Jun 2023 12:34:12 +0200
> >> Bernhard Beschow w
On Mon, 12 Jun 2023 16:51:55 +0200
Igor Mammedov wrote:
> On Sun, 11 Jun 2023 12:34:12 +0200
> Bernhard Beschow wrote:
>
> > I440FX realization is currently mixed with PIIX3 creation. Furthermore, it
> > is
> > common practice to only set properties
On Sun, 11 Jun 2023 12:34:12 +0200
Bernhard Beschow wrote:
> I440FX realization is currently mixed with PIIX3 creation. Furthermore, it is
> common practice to only set properties between a device's qdev_new() and
> qdev_realize(). Clean up to resolve both issues.
>
> Since I440FX spawns a PCI
On Sun, 11 Jun 2023 12:34:04 +0200
Bernhard Beschow wrote:
> Signed-off-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
> ---
> hw/pci-host/i440fx.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-hos
ode
> set this property.
>
> Signed-off-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
> ---
> hw/i386/pc_q35.c | 2 ++
> hw/pci-host/q35.c | 3 +--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 2
On Sun, 11 Jun 2023 12:34:01 +0200
Bernhard Beschow wrote:
> Introduce a macro to avoid copy and pasting strings which can easily
> cause typos.
>
> Suggested-by: Michael S. Tsirkin
> Signed-off-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
> ---
> include/hw/pci/pc
set its own property while preserving encapsulation.
>
> Signed-off-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
> ---
> hw/i386/pc_q35.c | 4 +++-
> hw/pci-host/q35.c | 1 -
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i386/pc_q35.c b
On Sun, 11 Jun 2023 12:33:59 +0200
Bernhard Beschow wrote:
> Fixes the following clangd warning (-Winitializer-overrides):
>
> q35.c:297:19: Initializer overrides prior initialization of this subobject
> q35.c:292:19: previous initialization is here
>
> Settle on native endian which causes
On Mon, 22 May 2023 15:17:17 +0200
Igor Mammedov wrote:
Paolo,
can you pick it up?
> QEMU aborts when default RAM backend should be used (i.e. no
> explicit '-machine memory-backend=' specified) but user
> has created an object which 'id' equals to default RAM backend
> name u
> models. This is necessary to avoid the following message when launching
> a VM with large number of vcpus.
>
>"SMBIOS 2.1 table length 66822 exceeds 65535"
>
> Signed-off-by: Suravee Suthikulpanit
Looks good to me (see comment below for extra cleanup poss
dr 0 instead. Remove the acpi_pm1_cnt_write() function which is used
> only once and does not take addr into account and handle non-zero
> address in acpi_pm_cnt_{read|write}. This fixes ACPI shutdown with
> pegasos2 firmware.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Igor Mammedo
On Thu, 8 Jun 2023 10:51:05 +0800
Zhao Liu wrote:
> On Wed, Jun 07, 2023 at 04:49:34PM +0200, Igor Mammedov wrote:
> > Date: Wed, 7 Jun 2023 16:49:34 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH v2 2/3] hw/smbios: Fix thread count in type4
> > X-Mailer: Cl
On Tue, 6 Jun 2023 21:49:37 -0500
Suravee Suthikulpanit wrote:
> Into a helper function pc_machine_init_smbios() in preparation for
> subsequent code to upgrade default SMBIOS entry point type.
>
> Then, call the helper function from the pc_machine_initfn() to eliminate
> duplicate code in
uld
> return the following error message:
>
> qemu-system-x86_64: kvm_init_vcpu: kvm_get_vcpu failed (xxx): Invalid
> argument
>
> Also, keep max_cpus at 288 for machine version 8.0 and older.
>
> Cc: Igor Mammedov
> Cc: Daniel P. Berrangé
> Cc: Michael S. T
On Tue, 6 Jun 2023 21:49:38 -0500
Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
>
On Thu, 1 Jun 2023 17:29:52 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> From SMBIOS 3.0 specification, core count field means:
>
> Core Count is the number of cores detected by the BIOS for this
> processor socket. [1]
>
> Before 003f230e37d7 ("machine: Tweak the order of topology members in
On Thu, 1 Jun 2023 17:29:51 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> From SMBIOS 3.0 specification, thread count field means:
>
> Thread Count is the total number of threads detected by the BIOS for
> this processor socket. It is a processor-wide count, not a
> thread-per-core count. [1]
>
On Thu, 1 Jun 2023 17:29:50 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> Here're 2 mistakes:
> 1. 003f230e37d7 ("machine: Tweak the order of topology members in struct
>CpuTopology") changes the meaning of smp.cores but doesn't fix
>original smp.cores uses. And because of the
On Tue, 6 Jun 2023 18:59:48 +0200 (CEST)
BALATON Zoltan wrote:
> On Tue, 6 Jun 2023, Igor Mammedov wrote:
> > On Sun, 28 May 2023 15:57:50 +0200 (CEST)
> > BALATON Zoltan wrote:
> >
> >> On pegasos2 which has ACPI as part of VT8231 south bridge the board
&
ed
> (1024) exceeds the recommended cpus supported by KVM (710)
Also do not forget about TCG where KVM accel is not even in the picture.
> $ uname -srvp
> Linux 5.15.0-71-generic #78-Ubuntu SMP Tue Apr 18 09:00:29 UTC 2023 x86_64
>
> > Also, keep max_cpus at 288 for machine ver
hich defined in the CPUArchId.
>
> CC: Igor Mammedov
> Signed-off-by: Shaoqin Huang
with commit message fixed up
Reviewed-by: Igor Mammedov
> ---
> include/hw/boards.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/boards.h b/include/hw/boa
On Sun, 28 May 2023 15:57:50 +0200 (CEST)
BALATON Zoltan wrote:
> On pegasos2 which has ACPI as part of VT8231 south bridge the board
> firmware writes PM control register by accessing the second byte so
> addr will be 1. This wasn't handled correctly and the write went to
> addr 0 instead. This
On Tue, 6 Jun 2023 09:35:41 +0200
Igor Mammedov wrote:
> On Mon, 5 Jun 2023 16:39:05 -0500
> Suravee Suthikulpanit wrote:
[...]
> > +/* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */
> > +pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
> >
uld
> return the following error message:
>
> qemu-system-x86_64: kvm_init_vcpu: kvm_get_vcpu failed (xxx): Invalid
> argument
>
> Cc: Igor Mammedov
> Cc: Daniel P. Berrangé
> Cc: Michael S. Tsirkin
> Cc: Julia Suvorova
> Signed-off-by: Suravee Suthikulpanit
On Mon, 5 Jun 2023 16:39:04 -0500
Suravee Suthikulpanit wrote:
> In preparation for subsequent code to upgrade default SMBIOS
> entry point type. There is no functional change.
>
> Signed-off-by: Suravee Suthikulpanit
> ---
> hw/i386/pc.c | 12
> hw/i386/pc_piix.c | 9
On Mon, 5 Jun 2023 16:39:05 -0500
Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
>
On Tue, 30 May 2023 00:43:43 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> From SMBIOS 3.0 specification, core count field means:
>
> Core Count is the number of cores detected by the BIOS for this
> processor socket. [1]
>
> Before 003f230e37d7 ("machine: Tweak the order of topology members in
On Mon, 3 Apr 2023 21:19:53 -0400
Dinah Baum wrote:
> Part 1 is a refactor/code motion patch for
> qapi/machine target required for setup of
>
> Part 2 which enables query-cpu-model-expansion
> on all architectures
>
> Part 3 implements the ',help' feature
>
> Limitations:
> Currently only
On Tue, 23 May 2023 14:31:30 +0200
Markus Armbruster wrote:
> Igor Mammedov writes:
>
> > QEMU aborts when default RAM backend should be used (i.e. no
> > explicit '-machine memory-backend=' specified) but user
> > has created an object which 'id' equals to default R
' and exit with
an error, suggesting how to remedy the issue.
Signed-off-by: Igor Mammedov
CC: th...@redhat.com
---
hw/core/machine.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 07f763eb2e..1000406211 100644
--- a/hw/core/machine.c
+++ b/hw/core
120 -> 120 bytes
> tests/data/acpi/q35/APIC.acpihmat | Bin 128 -> 128 bytes
> tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 144 -> 144 bytes
> tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 2478 bytes
> tests/data/acpi/q35/APIC.cphp | Bin 160 -> 160 bytes
> tests/data/acpi/q35/APIC.dimmpxm | Bin 144 -> 144 bytes
> tests/data/acpi/q35/APIC.xapic| Bin 2686 -> 2686 bytes
> 15 files changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Igor Mammedov
2dca3f0d1 (qapi: Rewrite parsing of doc comment section symbols and
> tags)
> Signed-off-by: Markus Armbruster
Fixes build failure for me on RHEL8
Tested-by: Igor Mammedov
> ---
> scripts/qapi/parser.py | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --gi
On Mon, 15 May 2023 16:33:10 -0400
Eric DeVolder wrote:
> Currently i386 QEMU generates MADT revision 3, and reports
> MADT revision 1. Set .revision to 3 to match reality.
>
> Link:
> https://lore.kernel.org/linux-acpi/20230327191026.3454-1-eric.devolder@ora
> cle.com/T/#t
> Signed-off-by:
On Wed, 10 May 2023 10:12:22 +0200
Markus Armbruster wrote:
> To recognize a line starting with a section symbol and or tag, we
> first split it at the first space, then examine the part left of the
> space. We can just as well examine the unsplit line, so do that.
this makes build fail on
On Wed, 10 May 2023 10:08:50 -0500
Eric DeVolder wrote:
> On 5/10/23 03:14, Igor Mammedov wrote:
> > On Fri, 5 May 2023 16:53:22 -0500
> > Eric DeVolder wrote:
> >
> >> Thoughts?
> >
> > I still don't think we need to bump x86 to rev 5 in QEMU
;
> > This is expected as hot unplug did not work in Windows 2008.
> >
> > - RHEL 6.9
> > Kernel 2.6.32-696.el6.x86_64
> > Build Feb 21 2017
> > From dmesg:
> > ACPI: APIC 7ffe32f0 000F0 (v05 BOCHS BXPC0001 BXPC
> > 0001)
On Tue, 9 May 2023 14:44:52 +0800
Yin Wang wrote:
> command "qemu-system-riscv64 -machine virt
> -m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
> would trigger this problem.
> This commit fixes the issue by adding parameter checks.
It seems wrong to apply this to all targets (that
On Tue, 25 Apr 2023 09:32:54 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Apr 25, 2023 at 04:19:12PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> > On 25.04.23 16:07, Vladimir Sementsov-Ogievskiy wrote:
> > > On 25.04.23 15:43, Michael S. Tsirkin wrote:
> > > > On Tue, Apr 25, 2023 at
On Tue, 25 Apr 2023 13:55:55 +0300
Vladimir Sementsov-Ogievskiy wrote:
> On 24.04.23 23:36, Vladimir Sementsov-Ogievskiy wrote:
> > On migration, on target we load local ROM file. But actual ROM content
> > migrates through migration channel. Original ROM content from local
> > file doesn't
On Wed, 19 Apr 2023 02:48:55 +
"zhangying (AZ)" wrote:
> > On Tue, 18 Apr 2023 09:06:30 +
> > "zhangying (AZ)" via wrote:
> >
> > > > On 30.07.20 17:58, Michael S. Tsirkin wrote:
> > > > > macOS uses ACPI UIDs to build the DevicePath for NVRAM boot
> > > > > options, while OVMF
onsider unnecessary.
Acked-by: Igor Mammedov
>
> [1] https://lkml.kernel.org/r/20211027124531.57561-8-da...@redhat.com
>
> Cc: "Michael S. Tsirkin"
> Cc: Stefan Hajnoczi
> Cc: Dr. David Alan Gilbert
> Cc: Igor Mammedov
>
> v1 -> v2:
> - "vhost:
while at
> it.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: David Hildenbrand
> ---
> include/exec/cpu-common.h | 15 +++
> softmmu/physmem.c | 17 -
> 2 files changed, 15 insertions(+), 17 deletions(-)
>
> diff --git a/include/
On Thu, 20 Apr 2023 13:35:58 +0530
Ani Sinha wrote:
> On Tue, Apr 18, 2023 at 10:22 PM Eric DeVolder
> wrote:
> >
> > Currently i386 QEMU generates MADT revision 3, and reports
> > MADT revision 1. ACPI 6.3 introduces MADT revision 5.
> >
> > For MADT revision 4, that introduces ARM GIC
On Wed, 12 Apr 2023 09:18:25 -0300
Fabiano Rosas wrote:
> It is possible to have a build with both TCG and KVM disabled due to
> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
> host.
>
> If we build with --disable-tcg on the aarch64 host, we will end-up
> with a QEMU
6c62e3 ("pcie: expire pending delete")
2)
Fixes: cce8944cc9ef ("qdev-monitor: Forbid repeated device_del")
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
CC: m...@redhat.com
CC: anisi...@redhat.com
CC: jus...@redhat.com
CC: kra...@redhat.com
---
v4:
* massage commit mes
On Thu, 13 Apr 2023 13:50:57 +0800
Gavin Shan wrote:
> On 4/12/23 7:42 PM, Peter Maydell wrote:
> > On Wed, 12 Apr 2023 at 02:08, Gavin Shan wrote:
> >> On 3/27/23 9:26 PM, Igor Mammedov wrote:
> >>> On Fri, 17 Mar 2023 14:25:39 +0800
> >>> G
On Thu, 30 Mar 2023 13:58:22 +0200
Fiona Ebner wrote:
> Am 30.03.23 um 10:22 schrieb Igor Mammedov:
> > On Tue, 28 Mar 2023 14:58:21 +0200
> > Fiona Ebner wrote:
> >
> >> Am 10.06.22 um 09:57 schrieb Michael S. Tsirkin:
> >>> From:
On Tue, 11 Apr 2023 18:00:49 +0200
Igor Mammedov wrote:
> On Tue, 28 Mar 2023 11:59:26 -0400
> Eric DeVolder wrote:
>
> > Currently i386 QEMU generates MADT revision 3, and reports
> > MADT revision 1. ACPI 6.3 introduces MADT revision 5.
> >
> > For MADT re
On Tue, 28 Mar 2023 11:59:26 -0400
Eric DeVolder wrote:
> Currently i386 QEMU generates MADT revision 3, and reports
> MADT revision 1. ACPI 6.3 introduces MADT revision 5.
>
> For MADT revision 4, that introduces ARM GIC structures, which do
> not apply to i386.
>
> For MADT revision 5, the
On Tue, 28 Mar 2023 11:59:25 -0400
Eric DeVolder wrote:
> Currently ARM QEMU generates, and reports, MADT revision 4. ACPI 6.3
> introduces MADT revision 5.
>
> For MADT revision 5, the GICC structure adds an SPE Overflow Interrupt
> field. This new 2-byte field is created from the existing
On Tue, 11 Apr 2023 10:05:01 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Apr 11, 2023 at 04:02:19PM +0200, Igor Mammedov wrote:
> > PS2:
> > Also, I'm working on expanding PCI slots descriptors to PXBs,
> > and more or less that will negate this tables split.
On Fri, 7 Apr 2023 03:37:00 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Apr 06, 2023 at 11:25:47AM +0100, Jonathan Cameron wrote:
> > On Fri, 17 Mar 2023 16:54:36 +
> > Jonathan Cameron via wrote:
> >
> > > Michael Tsirkin raised that we have recently had churn in the
> > >
On Wed, 5 Apr 2023 15:58:31 +0200
David Hildenbrand wrote:
> On 04.04.23 16:36, Peter Xu wrote:
> > On Mon, Apr 03, 2023 at 10:14:21PM +, Alexander Graf wrote:
> >> Add an option for hostmem-file to start the memory object at an offset
> >> into the target file. This is useful if multiple
On Tue, 4 Apr 2023 12:46:45 +0200
Gerd Hoffmann wrote:
> On Tue, Apr 04, 2023 at 10:30:55AM +0200, Igor Mammedov wrote:
> > On Tue, 4 Apr 2023 09:03:59 +0200
> > Gerd Hoffmann wrote:
> >
> > > Hi,
> > >
> > > > > Allowin
, i440fx machines with version 2.2
> and older).
>
> Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
> ---
> hw/i386/acpi-build.c | 6 --
> hw/i386/pc.c | 1 +
> hw/i386/pc_piix.c| 1 +
> include/hw/i386/pc.h | 3 +++
> 4 files changed, 9 insertions(+
On Wed, 5 Apr 2023 06:02:29 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Apr 05, 2023 at 11:38:56AM +0200, Igor Mammedov wrote:
> > On Wed, 5 Apr 2023 04:47:48 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Wed, Apr 05, 2023 at 10:34:4
On Wed, 5 Apr 2023 05:59:06 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Apr 05, 2023 at 11:24:16AM +0200, Igor Mammedov wrote:
> > > > PS:
> > > > See commit message, Windows is not affected as it doesn't
> > > > clear GPE status bits during ACPI
On Wed, 5 Apr 2023 04:47:48 -0400
"Michael S. Tsirkin" wrote:
[...]
> This is arguably a regression but not in this release yes?
> So I don't think it needs to block qemu release.
yep, it's 'old' regression introduced in earlier releases
> Fixes: cce8944cc9ef ("qdev-monitor: Forbid repeated
"pcie: expire pending delete")
2)
Fixes: cce8944cc9ef ("qdev-monitor: Forbid repeated device_del")
Signed-off-by: Igor Mammedov
CC: m...@redhat.com
CC: anisi...@redhat.com
CC: jus...@redhat.com
CC: kra...@redhat.com
---
v3:
* fix typo in comment
* move CC to the main commit mes
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