Re: [RFC 1/1] hw: tpmtisspi: add SPI support to QEMU TPM implementation

Hi Guenter, Not from me at this moment :) Thanks, Iris On Wed, Dec 13, 2023 at 9:39 AM Guenter Roeck wrote: > Hi, > > On Tue, Aug 02, 2022 at 07:32:41PM -0700, Iris Chen wrote: > > From: Iris Chen > > > > Signed-off-by: Iris Chen > > --- > > Are

[RFC 0/1] SPI support in QEMU TPM

From: Iris Chen Hey everyone, Thanks for all your comments on the SPI GPIO model. I am working through them. As for adding support for SPI-based TPMs in QEMU, this RFC patch adds SPI support in the QEMU TPM implementation via tpm_tis_spi.c. The QEMU tree already has support for two connection

[RFC 1/1] hw: tpmtisspi: add SPI support to QEMU TPM implementation

From: Iris Chen Signed-off-by: Iris Chen --- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/Kconfig | 5 + hw/tpm/Kconfig | 5 + hw/tpm/meson.build | 1 + hw/tpm/tpm_tis_spi.c| 311

Re: [RFC 0/3] Add Generic SPI GPIO model

Thanks everyone for the insightful feedback! This is really helpful for me. I am taking a look at all the comments now and will investigate into it. Best, Iris

[RFC 2/3] hw: spi_gpio: add spi gpio model

Signed-off-by: Iris Chen --- hw/ssi/spi_gpio.c | 166 ++ include/hw/ssi/spi_gpio.h | 38 + 2 files changed, 204 insertions(+) create mode 100644 hw/ssi/spi_gpio.c create mode 100644 include/hw/ssi/spi_gpio.h diff --git a/hw/ssi/spi_gpio.c b

[RFC 1/3] hw: m25p80: add prereading ability in transfer8

With SPI-GPIO we don't have the input bits until all 8 bits of the output have been shifted out, so we have to prime the MISO with bogus values (0xFF). Signed-off-by: Iris Chen --- hw/block/m25p80.c| 29 - hw/ssi/ssi.c | 4 include/hw/ssi/ssi.h | 5

[RFC 0/3] Add Generic SPI GPIO model

s for your review and any direction here would be helpful :) Iris Chen (3): hw: m25p80: add prereading ability in transfer8 hw: spi_gpio: add spi gpio model hw: aspeed: hook up the spi gpio model hw/arm/Kconfig| 1 + hw/arm/aspeed.c | 5 ++ hw/block/m25p80.c

[PATCH v3] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

Signed-off-by: Iris Chen --- Cosmetic suggestions addressed. hw/block/m25p80.c | 102 -- 1 file changed, 90 insertions(+), 12 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 50b523e5b1..f3b401cf90 100644 --- a/hw/block/m25p80.c

[PATCH v2] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

Signed-off-by: Iris Chen --- Addressing all comments. In reponse to this comment: "Something wrong will occur if all block_protect[0123] are zeroes", the code actually ignores num_protected_sectors when block_protect_value = 0 which happens when block_protect[0123] are zeroes. You

[PATCH 1/2] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

Signed-off-by: Iris Chen --- hw/block/m25p80.c | 74 +++ 1 file changed, 62 insertions(+), 12 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 50b523e5b1..0156a70f5e 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -38,21

[PATCH 2/2] hw: m25p80: add tests for BP and TB bit write protect

Signed-off-by: Iris Chen --- tests/qtest/aspeed_smc-test.c | 111 ++ 1 file changed, 111 insertions(+) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index 1258687eac..05ce941566 100644 --- a/tests/qtest/aspeed_smc-test.c +++ b/tests

[PATCH 0/2] Add Block Protect (BP) and Top Bottom (TB) bits for write protect

Iris Chen (2): hw: m25p80: Add Block Protect and Top Bottom bits for write protect hw: m25p80: add tests for BP and TB bit write protect hw/block/m25p80.c | 74 +++ tests/qtest/aspeed_smc-test.c | 111 ++ 2 files changed, 173

[PATCH v4] hw: m25p80: add tests for write protect (WP# and SRWD bit)

Signed-off-by: Iris Chen --- Adding Signed Off By tag -- sorry I missed that ! tests/qtest/aspeed_smc-test.c | 62 +++ 1 file changed, 62 insertions(+) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index ec233315e6..7786addfb8 100644

[PATCH v4] hw: m25p80: add WP# pin and SRWD bit for write protection

From: Iris Chen Signed-off-by: Iris Chen --- Fixed .needed for subsection and suggestions from Francisco hw/block/m25p80.c | 82 ++- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index

[PATCH 1/1] hw: m25p80: fixing individual test failure when tests are running in isolation

Signed-off-by: Iris Chen --- tests/qtest/aspeed_smc-test.c | 74 +-- 1 file changed, 63 insertions(+), 11 deletions(-) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index ec233315e6..b1e682db65 100644 --- a/tests/qtest/aspeed_smc

[PATCH 0/1] hw: m25p80: fix aspeed_smc tests failure when run in isolation

flash_reset() between running the tests and make sure the tests do not rely on each other. Thus, I have made changes to the tests so that they now pass individually with no dependencies on each other. Thanks, Iris Iris Chen (1): hw: m25p80: fixing individual test failure when tests are running

[PATCH v3 2/2] hw: m25p80: add tests for write protect (WP# and SRWD bit)

--- Fixing suggestions to move testing related code to a different commit. tests/qtest/aspeed_smc-test.c | 62 +++ 1 file changed, 62 insertions(+) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index ec233315e6..7786addfb8 100644 ---

[PATCH v3 1/2] hw: m25p80: add WP# pin and SRWD bit for write protection

Signed-off-by: Iris Chen --- Thanks everyone for your comments. This is a v3 patch that addresses all suggestions (moving write_enable to decode_new_cmd). I am waiting on some feedback from Dan's (dz4l...@gmail.com) patch regarding adding a STATE_STANDBY state. Currently, all tests

[PATCH v2 2/2] hw: m25p80: add tests for write protect

Signed-off-by: Iris Chen --- Include the tests in a separate patch. Using qtest_set_irq_in() as per review. tests/qtest/aspeed_smc-test.c | 60 +++ 1 file changed, 60 insertions(+) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index

[PATCH v2 1/2] hw: m25p80: add WP# pin and SRWD bit for write protection

From: Iris Chen Signed-off-by: Iris Chen --- Addressed all comments from V1. The biggest change: removed object_class_property_add. hw/block/m25p80.c | 37 +++ tests/qtest/aspeed_smc-test.c | 2 ++ 2 files changed, 39 insertions(+) diff --git

[PATCH 1/1] hw: m25p80: add W# pin and SRWD bit for write protection

From: Iris Chen Add the W# pin and SRWD bit which control the status register write ability. Signed-off-by: Iris Chen --- hw/block/m25p80.c | 72 +++ tests/qtest/aspeed_smc-test.c | 62 ++ 2 files changed, 134 insertions

[PATCH 0/1] hw: m25p80: add W# pin and SRWD bit for write protection

From: Iris Chen Hey everyone, My patch adds the W# pin and SRWD bit which work together to control the status register write ability. Accordingly, when W# is low and SRWD bit is high, hardware protection mode (HPM) is initiated. All other cases result in software protection. Acceptance

[PATCH v3] hw: m25p80: allow write_enable latch get/set

The write_enable latch property is not currently exposed. This commit makes it a modifiable property. Signed-off-by: Iris Chen --- v3: Addressed comments by Peter and Cedric. v2: Ran ./scripts/checkpatch.pl on the patch and added a description. Fixed comments regarding DEFINE_PROP_BOOL. hw

[PATCH v2] hw: m25p80: allow write_enable latch get/set

The write_enable latch property is not currently exposed. This commit makes it a modifiable property using get/set methods. Signed-off-by: Iris Chen --- Ran ./scripts/checkpatch.pl on the patch and added a description. Fixed comments regarding DEFINE_PROP_BOOL. hw/block/m25p80.c

[PATCH 0/1] hw: allow write_enable latch get/set

is set). Thanks, Iris Iris Chen (1): hw: allow write_enable latch get/set hw/block/m25p80.c | 30 ++ tests/qtest/aspeed_smc-test.c | 20 2 files changed, 50 insertions(+) -- 2.30.2

[PATCH 1/1] hw: allow write_enable latch get/set

--- hw/block/m25p80.c | 30 ++ tests/qtest/aspeed_smc-test.c | 20 2 files changed, 50 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 430d1298a8..fb72704e5a 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c

[PATCH 1/1] hw: allow write_enable latch get/set

--- hw/block/m25p80.c | 30 ++ tests/qtest/aspeed_smc-test.c | 20 2 files changed, 50 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 430d1298a8..fb72704e5a 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c

[PATCH 0/1] hw: allow write_enable latch get/set

is set). Thanks, Iris Iris Chen (1): hw: allow write_enable latch get/set hw/block/m25p80.c | 30 ++ tests/qtest/aspeed_smc-test.c | 20 2 files changed, 50 insertions(+) -- 2.30.2