: Bin Meng
Sent: Monday 19 October 2020 09:38
To: Ivan Griffin
Cc: Alistair Francis ; QEMU Trivial
; open list:RISC-V ;
qemu-devel@nongnu.org Developers
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Hi Ivan,
On Mon, Oct 19, 2020 at 4:17 PM Ivan Griffin wrote:
>
>
Hi Bin,
Well spotted with the register map. I grepped it for 0x3702 and didn't find
it, but it seems the address (incorrectly) is 0x0702 in the documentation.
Thanks,
Ivan.
From: Bin Meng
Sent: Monday 19 October 2020 03:05
To: Ivan Griffin
Cc
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
reporting a STORE/AMO Access Fault.
This region is used by the PolarFire SoC port of U-Boot to
interact with the FPGA system controller.
Signed-off-by: Ivan Griffin
---
hw/riscv/microchip_pfsoc.c | 10 ++
include
see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the
FPGA system controller to perform various services.
Cheers,
Ivan
-Original Message-
From: Alistair Francis
Sent: Friday 16 October 2020 17:08
To: Ivan Griffin
Cc: Bin Meng ; QEMU Trivial ;
open list:RISC-V
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
reporting a STORE/AMO Access Fault.
This region is used by the PolarFire SoC port of U-Boot to
interact with the FPGA system controller.
Signed-off-by: Ivan Griffin
---
hw/riscv/microchip_pfsoc.c | 6 ++
include/hw
