[Qemu-devel] [GSOC] Support for AVX within TCG: Work Product Submission

to everyone who made this possible! Best, -Jan Bobek GSOC WORK PRODUCT SUBMISSION TITLE: Support for AVX within TCG DATE: 08/25/2019 AUTHOR: Jan Bobek MENTOR: Richard Henderson I. SUMMARY The goal of this GSoC project was to implement support for AVX instructions in the i386 TCG front-end

[Qemu-devel] [RFC PATCH v4 64/75] target/i386: introduce AVX2 vector instructions to sse-opcode.inc.h

Add all the AVX2 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 362 ++- 1 file changed, 359 insertions(+), 3 deletions(-) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index

[Qemu-devel] [RFC PATCH v4 63/75] target/i386: introduce AVX2 code generators

Introduce code generators required by AVX2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 407 ++-- 1 file changed, 395 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3f4bb40932

[Qemu-devel] [RFC PATCH v4 73/75] target/i386: remove obsoleted helper_mov(l, q)_mm_T0

This helper has been obsoleted by the new code. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 19 --- target/i386/ops_sse_header.h | 4 target/i386/translate.c | 33 - 3 files changed, 56 deletions(-) diff --git a/target

[Qemu-devel] [RFC PATCH v4 72/75] target/i386: convert psadbw helper to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 64 +++- target/i386/ops_sse_header.h | 2 +- target/i386/translate.c | 9 +++-- 3 files changed, 32 insertions(+), 43 deletions

[Qemu-devel] [RFC PATCH v4 71/75] target/i386: convert pmuludq/pmaddwd helpers to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. --- target/i386/ops_sse.h| 27 +-- target/i386/ops_sse_header.h | 4 ++-- target/i386/translate.c | 18 -- 3 files changed, 27 insertions(+), 22 deletions(-) diff --git

[Qemu-devel] [RFC PATCH v4 66/75] target/i386: cleanup leftovers in ops_sse_header.h

Get rid of unused macro definitions that have been left over after removal of obsoleted helpers. --- target/i386/ops_sse_header.h | 28 ++-- 1 file changed, 6 insertions(+), 22 deletions(-) diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h index

[Qemu-devel] [RFC PATCH v4 61/75] target/i386: introduce AVX vector instructions to sse-opcode.inc.h

Add all the AVX vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 779 +++ 1 file changed, 779 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 1359508424

[Qemu-devel] [RFC PATCH v4 58/75] target/i386: introduce AES and PCLMULQDQ vector instructions to sse-opcode.inc.h

Add all the AES and PCLMULQDQ vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index

[Qemu-devel] [RFC PATCH v4 68/75] target/i386: convert ps((l, r)l(w, d, q), ra(w, d)) to helpers to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 357 +-- target/i386/ops_sse_header.h | 30 ++- target/i386/translate.c | 259 +++-- 3 files changed, 306

[Qemu-devel] [RFC PATCH v4 59/75] target/i386: introduce AVX translators

Use the translator macros to define translators required by AVX instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 48 + 1 file changed, 48 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 14117c2993

[Qemu-devel] [RFC PATCH v4 74/75] target/i386: convert pshuf(w, lw, hw, d), shuf(pd, ps) helpers to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 141 --- target/i386/ops_sse_header.h | 12 +-- target/i386/translate.c | 34 - 3 files changed, 119 insertions(+), 68

[Qemu-devel] [RFC PATCH v4 43/75] target/i386: introduce SSE2 code generators

Introduce code generators required by SSE2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 427 +++- 1 file changed, 425 insertions(+), 2 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 43917edc76

[Qemu-devel] [RFC PATCH v4 55/75] target/i386: introduce SSE4.2 vector instructions to sse-opcode.inc.h

Add all the SSE4.2 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 13 + 1 file changed, 13 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 9682cce7ef..f43436213e 100644

[Qemu-devel] [RFC PATCH v4 70/75] target/i386: convert pavgb/pavgw helpers to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 33 + target/i386/ops_sse_header.h | 7 +-- target/i386/translate.c | 20 +--- 3 files changed, 43 insertions

[Qemu-devel] [RFC PATCH v4 69/75] target/i386: convert pmullw/pmulhw/pmulhuw helpers to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 42 ++-- target/i386/ops_sse_header.h | 6 +++--- target/i386/translate.c | 27 +++ 3 files changed, 51

[Qemu-devel] [RFC PATCH v4 60/75] target/i386: introduce AVX code generators

Introduce code generators required by AVX instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 954 1 file changed, 954 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 9b9f0d4ed1..50eab9181c 100644

[Qemu-devel] [RFC PATCH v4 48/75] target/i386: introduce SSSE3 translators

Use the translator macros to define translators required by SSSE3 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index d449a64464..25d3b969b1 100644 --- a/target/i386

[Qemu-devel] [RFC PATCH v4 65/75] target/i386: remove obsoleted helpers

A number of helpers have been obsoleted by the use of tcg_gen_gvec_* functions; remove all of them. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 65 target/i386/ops_sse_header.h | 39 -- target/i386/translate.c | 38

[Qemu-devel] [RFC PATCH v4 62/75] target/i386: introduce AVX2 translators

Use the translator macros to define translators required by AVX2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 50eab9181c

[Qemu-devel] [RFC PATCH v4 75/75] target/i386: convert pmovmskb/movmskps/movmskpd helpers to gvec style

Make these helpers suitable for use with tcg_gen_gvec_* functions. Signed-off-by: Jan Bobek --- target/i386/ops_sse.h| 74 ++-- target/i386/ops_sse_header.h | 9 ++- target/i386/translate.c | 132 ++- 3 files changed, 65 insertions

[Qemu-devel] [RFC PATCH v4 46/75] target/i386: introduce SSE3 code generators

Introduce code generators required by SSE3 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 61 + 1 file changed, 61 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index a478f73c17..d449a64464 100644

[Qemu-devel] [RFC PATCH v4 67/75] target/i386: introduce aliases for helper-based tcg_gen_gvec_* functions

Expand our aliases for tcg_gen_gvec_* functions to also include those that generate calls to out-of-line helpers. This allows us use them via the DEF_GEN_INSN*_GVEC macros. --- target/i386/translate.c | 30 ++ 1 file changed, 30 insertions(+) diff --git

[Qemu-devel] [RFC PATCH v4 57/75] target/i386: introduce AES and PCLMULQDQ code generators

Introduce code generators required by AES and PCLMULQDQ instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 75b0a818f2..14117c2993 100644 --- a/target/i386

[Qemu-devel] [RFC PATCH v4 45/75] target/i386: introduce SSE3 translators

Use the translator macros to define translators required by SSE3 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3445b4cff1..a478f73c17 100644 --- a/target/i386

[Qemu-devel] [RFC PATCH v4 47/75] target/i386: introduce SSE3 vector instructions to sse-opcode.inc.h

Add all the SSE3 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 6df5fda010..84785a4e04 100644

[Qemu-devel] [RFC PATCH v4 49/75] target/i386: introduce SSSE3 code generators

Introduce code generators required by SSSE3 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 33 + 1 file changed, 33 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 25d3b969b1..f43e9b1ba4 100644

[Qemu-devel] [RFC PATCH v4 53/75] target/i386: introduce SSE4.1 vector instructions to sse-opcode.inc.h

Add all the SSE4.1 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 101 +++ 1 file changed, 101 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index d8ea71aa6c

[Qemu-devel] [RFC PATCH v4 51/75] target/i386: introduce SSE4.1 translators

Use the translator macros to define translators required by SSE4.1 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 12 1 file changed, 12 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index f43e9b1ba4..110b963215 100644

[Qemu-devel] [RFC PATCH v4 38/75] target/i386: introduce MMX vector instructions to sse-opcode.inc.h

Add all MMX vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 136 +++ 1 file changed, 136 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 04d0c49168

[Qemu-devel] [RFC PATCH v4 50/75] target/i386: introduce SSSE3 vector instructions to sse-opcode.inc.h

Add all the SSSE3 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 67 1 file changed, 67 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 84785a4e04

[Qemu-devel] [RFC PATCH v4 52/75] target/i386: introduce SSE4.1 code generators

Introduce code generators required by SSE4.1 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 101 1 file changed, 101 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 110b963215..3ff063b701 100644

[Qemu-devel] [RFC PATCH v4 35/75] target/i386: introduce instruction translator macros

Instruction "translators" are responsible for decoding and loading instruction operands, calling the passed-in code generator, and storing the operands back (if applicable). Once a translator returns, the instruction has been translated to TCG ops, hence the name. Signed-off-by:

[Qemu-devel] [RFC PATCH v4 54/75] target/i386: introduce SSE4.2 code generators

Introduce code generators required by SSE4.2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3ff063b701..f3b047c0df 100644 --- a/target/i386/translate.c +++ b

[Qemu-devel] [RFC PATCH v4 44/75] target/i386: introduce SSE2 vector instructions to sse-opcode.inc.h

Add all the SSE2 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 326 ++- 1 file changed, 325 insertions(+), 1 deletion(-) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index

[Qemu-devel] [RFC PATCH v4 36/75] target/i386: introduce MMX translators

Use the translator macros to define instruction translators required by MMX instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 1c2502ff50..96ba0f5704 100644

[Qemu-devel] [RFC PATCH v4 34/75] target/i386: introduce sse-opcode.inc.h

This header is intended to eventually list all supported instructions along with some useful details (e.g. mnemonics, opcode, operands etc.) It shall be used (along with some preprocessor magic) anytime we need to automatically generate code for every instruction. Signed-off-by: Jan Bobek

[Qemu-devel] [RFC PATCH v4 31/75] target/i386: introduce code generators

In this context, "code generators" are functions that receive decoded instruction operands and emit TCG ops implementing the correct instruction functionality. Introduce the naming macros first, actual generator macros will be added later. Signed-off-by: Jan Bobek --- target/i386/t

[Qemu-devel] [RFC PATCH v4 41/75] target/i386: introduce SSE vector instructions to sse-opcode.inc.h

Add all the SSE vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 161 +++ 1 file changed, 161 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index e570d449fc

[Qemu-devel] [RFC PATCH v4 29/75] target/i386: introduce H*, L*, V*, U*, W* (SSE/AVX) operands

These address the SSE/AVX-technology register file. Offset of the entire corresponding register is passed as the operand value, regardless of operand-size suffix. Signed-off-by: Jan Bobek --- target/i386/translate.c | 220 1 file changed, 220 insertions

[Qemu-devel] [RFC PATCH v4 33/75] target/i386: introduce gvec-based code generator macros

Code generators defined using these macros rely on a gvec operation (i.e. tcg_gen_gvec_*). Signed-off-by: Jan Bobek --- target/i386/translate.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 046914578b

[Qemu-devel] [RFC PATCH v4 26/75] target/i386: introduce M* (memptr) operands

The memory-pointer operand decodes the indirect form of ModR/M byte, loads the effective address into a register and passes that register as the operand. Signed-off-by: Jan Bobek --- target/i386/translate.c | 36 1 file changed, 36 insertions(+) diff --git

[Qemu-devel] [RFC PATCH v4 42/75] target/i386: introduce SSE2 translators

Use the translator macros to define translators required by SSE2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index d1537bc1b7..43917edc76

[Qemu-devel] [RFC PATCH v4 28/75] target/i386: introduce P*, N*, Q* (MMX) operands

These address the MMX-technology register file; the corresponding cpu_env offset is passed as the operand value. Notably, offset of the entire register is pased at all times, regardless of the operand-size suffix. Signed-off-by: Jan Bobek --- target/i386/translate.c | 80

[Qemu-devel] [RFC PATCH v4 30/75] target/i386: alias H* operands with the V* operands

and shall not be included in the final patch series. Signed-off-by: Jan Bobek --- target/i386/translate.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 23ba1d5edd..2e78bed78f 100644 --- a/target/i386

[Qemu-devel] [RFC PATCH v4 24/75] target/i386: introduce operand for direct-only r/m field

Many operands can only decode successfully if the ModR/M byte has the direct form (i.e. MOD=3). Capture this common aspect by introducing a special direct-only r/m field operand. Signed-off-by: Jan Bobek --- target/i386/translate.c | 37 + 1 file changed, 37

[Qemu-devel] [RFC PATCH v4 40/75] target/i386: introduce SSE code generators

Introduce code generators required by SSE instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 309 1 file changed, 309 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index d77c08b7db..d1537bc1b7 100644

[Qemu-devel] [RFC PATCH v4 22/75] target/i386: introduce modrm operand

This permits the ModR/M byte to be passed raw into the code generator, effectively allowing to short-circuit the operand decoding mechanism and do the decoding work manually in the code generator. Signed-off-by: Jan Bobek --- target/i386/translate.c | 20 1 file changed, 20

[Qemu-devel] [RFC PATCH v4 23/75] target/i386: introduce operands for decoding modrm fields

The old code uses bitshifts and bitwise-and all over the place for decoding ModR/M fields. Avoid doing that by introducing proper decoding operands. Signed-off-by: Jan Bobek --- target/i386/translate.c | 62 + 1 file changed, 62 insertions(+) diff --git

[Qemu-devel] [RFC PATCH v4 39/75] target/i386: introduce SSE translators

Use the translator macros to define translators required by SSE instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index fdfca03071

[Qemu-devel] [RFC PATCH v4 20/75] target/i386: introduce generic load-store operand

This operand attempts to capture the "indirect" or "memory" operand in a generic way. It significatly reduces the amount code that needs to be written in order to read operands from memory to temporary storage and write them back. Signed-off-by: Jan Bobek --- target/i

[Qemu-devel] [RFC PATCH v4 19/75] target/i386: introduce generic either-or operand

The either-or operand attempts to decode one operand, and if it fails, it falls back to a second operand. It is unifying, meaning that insnop_arg_t of the second operand must be implicitly castable to insnop_arg_t of the first operand. Signed-off-by: Jan Bobek --- target/i386/translate.c | 44

[Qemu-devel] [RFC PATCH v4 16/75] target/i386: disable AVX/AVX2 cpuid bitchecks

. Signed-off-by: Jan Bobek --- target/i386/translate.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3e54443d99..e7c2ad41bf 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4564,15

[Qemu-devel] [RFC PATCH v4 37/75] target/i386: introduce MMX code generators

Define code generators required for MMX instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 100 1 file changed, 100 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 96ba0f5704..fdfca03071 100644

[Qemu-devel] [RFC PATCH v4 18/75] target/i386: introduce generic operand alias

It turns out it is useful to be able to declare operand name aliases. Introduce a macro to capture this functionality. Signed-off-by: Jan Bobek --- target/i386/translate.c | 20 1 file changed, 20 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c

[Qemu-devel] [RFC PATCH v4 17/75] target/i386: introduce instruction operand infrastructure

insnop_arg_t, insnop_ctxt_t and init, prepare and finalize functions form the basis of instruction operand decoding. Introduce macros for defining a generic instruction operand; use cases for operand decoding will be introduced later. Signed-off-by: Jan Bobek --- target/i386/translate.c | 28

[Qemu-devel] [RFC PATCH v4 15/75] target/i386: introduce function check_cpuid

Introduce a helper function to take care of instruction CPUID checks. Signed-off-by: Jan Bobek --- target/i386/translate.c | 62 + 1 file changed, 62 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 467ecf15ba

[Qemu-devel] [RFC PATCH v4 06/75] target/i386: Simplify gen_exception arguments

From: Richard Henderson We can compute cur_eip from values present within DisasContext. Signed-off-by: Richard Henderson --- target/i386/translate.c | 89 - 1 file changed, 44 insertions(+), 45 deletions(-) diff --git a/target/i386/translate.c

[Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based code generator macros

Code generators defined using these macros rely on a helper function (as emitted by gen_helper_*). Signed-off-by: Jan Bobek --- target/i386/translate.c | 160 1 file changed, 160 insertions(+) diff --git a/target/i386/translate.c b/target/i386

[Qemu-devel] [RFC PATCH v4 07/75] target/i386: use pc_start from DisasContext

The variable pc_start is already a member of DisasContext. Remove the superfluous local variable. Reviewed-by: Richard Henderson Signed-off-by: Jan Bobek --- target/i386/translate.c | 131 1 file changed, 65 insertions(+), 66 deletions(-) diff --git

[Qemu-devel] [RFC PATCH v4 13/75] target/i386: decode the 0F38/0F3A prefix in gen_sse_ng

In order to decode 0F38/0F3A-prefixed instructions, we need to load an additional byte. This poses a problem if the instruction is not implemented yet; implement a rewind in this (default) case. Signed-off-by: Jan Bobek --- target/i386/translate.c | 16 1 file changed, 16

[Qemu-devel] [RFC PATCH v4 27/75] target/i386: introduce G*, R*, E* (general register) operands

These address the general-purpose register file. The corresponding 32-bit or 64-bit register is passed as the operand value. Signed-off-by: Jan Bobek --- target/i386/translate.c | 88 + 1 file changed, 88 insertions(+) diff --git a/target/i386

[Qemu-devel] [RFC PATCH v4 03/75] target/i386: use dflag from DisasContext

There already is a variable dflag in DisasContext, so use that one rather than the identically-named local helper variable. Suggested-by: Richard Henderson Signed-off-by: Jan Bobek --- target/i386/translate.c | 180 1 file changed, 90 insertions(+), 90

[Qemu-devel] [RFC PATCH v4 08/75] target/i386: make variable b1 const

The variable b1 does not change value once assigned. Make this fact explicit by marking it const. Reviewed-by: Richard Henderson Signed-off-by: Jan Bobek --- target/i386/translate.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/i386/translate.c b

[Qemu-devel] [RFC PATCH v4 12/75] target/i386: introduce CASES_* macros in gen_sse_ng

In case one or more fields should be ignored during instruction disambiguation, we need to generate multiple case labels. Introduce CASES_* macros for this purpose. Signed-off-by: Jan Bobek --- target/i386/translate.c | 54 + 1 file changed, 54 insertions

[Qemu-devel] [RFC PATCH v4 25/75] target/i386: introduce Ib (immediate) operand

Introduce the immediate-byte operand, which loads a byte from the instruction stream and passes its value as the operand. Signed-off-by: Jan Bobek --- target/i386/translate.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/i386/translate.c b/target/i386

[Qemu-devel] [RFC PATCH v4 05/75] target/i386: introduce disas_insn_prefix

Move the code for decoding an instruction prefix into a separate function. Signed-off-by: Jan Bobek --- target/i386/translate.c | 48 + 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index

[Qemu-devel] [RFC PATCH v4 09/75] target/i386: make variable is_xmm const

The variable is_xmm does not change value after assignment, so make this fact explicit by marking it const. Reviewed-by: Richard Henderson Signed-off-by: Jan Bobek --- target/i386/translate.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/i386

[Qemu-devel] [RFC PATCH v4 21/75] target/i386: introduce tcg register operands

TCG operands allocate a 32-bit or 64-bit TCG temporary and later automatically free it. Signed-off-by: Jan Bobek --- target/i386/translate.c | 44 + 1 file changed, 44 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index

[Qemu-devel] [RFC PATCH v4 11/75] target/i386: introduce gen_sse_ng

This function serves as the point-of-intercept for all newly implemented instructions. If no new implementation exists, fall back to gen_sse. Signed-off-by: Jan Bobek --- target/i386/translate.c | 46 - 1 file changed, 45 insertions(+), 1 deletion

[Qemu-devel] [RFC PATCH v4 01/75] target/i386: Push rex_r into DisasContext

From: Richard Henderson Treat this value the same as we do for rex_b and rex_x. Signed-off-by: Richard Henderson --- target/i386/translate.c | 85 + 1 file changed, 44 insertions(+), 41 deletions(-) diff --git a/target/i386/translate.c

[Qemu-devel] [RFC PATCH v4 14/75] target/i386: introduce aliases for some tcg_gvec operations

The aliases create a thin layer above the raw tcg_gvec functions, making room for us to permute the arguments, pass additional constant values etc., which will prove highly useful later. Signed-off-by: Jan Bobek --- target/i386/translate.c | 39 +++ 1 file

[Qemu-devel] [RFC PATCH v4 04/75] target/i386: use prefix from DisasContext

Use prefix from DisasContext instead of the local helper variable prefixes. Suggested-by: Richard Henderson Signed-off-by: Jan Bobek --- target/i386/translate.c | 110 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/target/i386

[Qemu-devel] [RFC PATCH v4 02/75] target/i386: Push rex_w into DisasContext

From: Richard Henderson Treat this the same as we already do for other rex bits. Signed-off-by: Richard Henderson --- target/i386/translate.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index

[Qemu-devel] [RFC PATCH v4 10/75] target/i386: add vector register file alignment constraints

gvec operations require that all vectors be aligned on 16-byte boundary; make sure the MM/XMM/YMM/ZMM register file is aligned as neccessary. Reviewed-by: Richard Henderson Signed-off-by: Jan Bobek --- target/i386/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[Qemu-devel] [RFC PATCH v4 00/75] rewrite MMX/SSE*/AVX/AVX2 vector instruction translation

.html 5. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg02689.html 6. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg02701.html Jan Bobek (72): target/i386: use dflag from DisasContext target/i386: use prefix from DisasContext target/i386: introduce

Re: [Qemu-devel] [RFC PATCH v3 02/46] target/i386: Push rex_w into DisasContext

On 8/15/19 6:19 AM, Aleksandar Markovic wrote: > > 15.08.2019. 11.55, "Richard Henderson" <mailto:richard.hender...@linaro.org>> је написао/ла: >> >> On 8/15/19 8:30 AM, Aleksandar Markovic wrote: >> > >> > 15.08.2019. 04.13, "Jan

Re: [Qemu-devel] [RFC PATCH v3 15/46] target/i386: introduce function ck_cpuid

On 8/15/19 11:01 AM, Aleksandar Markovic wrote: > > 15.08.2019. 04.23, "Jan Bobek" <mailto:jan.bo...@gmail.com>> је написао/ла: >> >> Introduce a helper function to take care of instruction CPUID checks. >> >> Signed-off-by: Jan Bobek m

Re: [Qemu-devel] [RFC PATCH v3 46/46] target/i386: introduce SSE3 instructions to sse-opcode.inc.h

On 8/15/19 6:07 AM, Aleksandar Markovic wrote: > > 15.08.2019. 11.55, "Richard Henderson" > је написао/ла: >> >> On 8/15/19 8:02 AM, Aleksandar Markovic wrote: >> > A question for you: What about FISTTP, MONITOR, MWAIT, that belong to >> > SSE3, but >> > are

[Qemu-devel] [RFC PATCH v3 43/46] target/i386: introduce SSE2 instructions to sse-opcode.inc.h

Add all the SSE2 instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 323 ++- 1 file changed, 322 insertions(+), 1 deletion(-) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index

[Qemu-devel] [RFC PATCH v3 42/46] target/i386: introduce SSE2 code generators

Introduce code generators required by SSE2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 444 +++- 1 file changed, 442 insertions(+), 2 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 177bedd0ef

[Qemu-devel] [RFC PATCH v3 44/46] target/i386: introduce SSE3 translators

Use the translator macros to define translators required by SSE3 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 7ec082e79d..c72138014a 100644 --- a/target/i386

[Qemu-devel] [RFC PATCH v3 38/46] target/i386: introduce SSE translators

Use the translator macros to define translators required by SSE instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 29 + 1 file changed, 29 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index a02e9cd0d2..ef64fe606f

[Qemu-devel] [RFC PATCH v3 40/46] target/i386: introduce SSE instructions to sse-opcode.inc.h

Add all the SSE instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 158 +++ 1 file changed, 158 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 36963e5a7c..39947aeb51

[Qemu-devel] [RFC PATCH v3 41/46] target/i386: introduce SSE2 translators

Use the translator macros to define translators required by SSE2 instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 33 + 1 file changed, 33 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3d526ee470

[Qemu-devel] [RFC PATCH v3 37/46] target/i386: introduce MMX instructions to sse-opcode.inc.h

Add all MMX instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 131 +++ 1 file changed, 131 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index c5e81a6a80..36963e5a7c

[Qemu-devel] [RFC PATCH v3 39/46] target/i386: introduce SSE code generators

Introduce code generators required by SSE instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 319 1 file changed, 319 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index ef64fe606f..3d526ee470 100644

[Qemu-devel] [RFC PATCH v3 32/46] target/i386: introduce gvec-based code generator macros

Code generators defined using these macros rely on a gvec operation (i.e. tcg_gen_gvec_*). Signed-off-by: Jan Bobek --- target/i386/translate.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index b28d651b82..75652afb45

[Qemu-devel] [RFC PATCH v3 36/46] target/i386: introduce MMX code generators

Define code generators required for MMX instructions. Signed-off-by: Jan Bobek --- target/i386/translate.c | 111 1 file changed, 111 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 4fecb0d240..a02e9cd0d2 100644

[Qemu-devel] [RFC PATCH v3 31/46] target/i386: introduce helper-based code generator macros

Code generators defined using these macros rely on a helper function (as emitted by gen_helper_*). Signed-off-by: Jan Bobek --- target/i386/translate.c | 106 1 file changed, 106 insertions(+) diff --git a/target/i386/translate.c b/target/i386

[Qemu-devel] [RFC PATCH v3 28/46] target/i386: introduce P*, N*, Q* (MMX) operands

These address the MMX-technology register file; the corresponding cpu_env offset is passed as the operand value. Notably, offset of the entire register is pased at all times, regardless of the operand-size suffix. Signed-off-by: Jan Bobek --- target/i386/translate.c | 79

[Qemu-devel] [RFC PATCH v3 33/46] target/i386: introduce sse-opcode.inc.h

This header is intended to eventually list all supported instructions along with some useful details (e.g. mnemonics, opcode, operands etc.) It shall be used (along with some preprocessor magic) anytime we need to automatically generate code for every instruction. Signed-off-by: Jan Bobek

[Qemu-devel] [RFC PATCH v3 34/46] target/i386: introduce instruction translator macros

Instruction "translators" are responsible for decoding and loading instruction operands, calling the passed-in code generator, and storing the operands back (if applicable). Once a translator returns, the instruction has been translated to TCG ops, hence the name. Signed-off-by:

[Qemu-devel] [RFC PATCH v3 29/46] target/i386: introduce H*, V*, U*, W* (SSE/AVX) operands

These address the SSE/AVX-technology register file. Offset of the entire corresponding register is passed as the operand value, regardless of operand-size suffix. Signed-off-by: Jan Bobek --- target/i386/translate.c | 117 1 file changed, 117 insertions

[Qemu-devel] [RFC PATCH v3 27/46] target/i386: introduce G*, R*, E* (general register) operands

These address the general-purpose register file. The corresponding 32-bit or 64-bit register is passed as the operand value. Signed-off-by: Jan Bobek --- target/i386/translate.c | 78 + 1 file changed, 78 insertions(+) diff --git a/target/i386

[Qemu-devel] [RFC PATCH v3 26/46] target/i386: introduce M* (memptr) operands

The memory-pointer operand decodes the indirect form of ModR/M byte, loads the effective address into a register and passes that register as the operand. Signed-off-by: Jan Bobek --- target/i386/translate.c | 36 1 file changed, 36 insertions(+) diff --git

[Qemu-devel] [RFC PATCH v3 30/46] target/i386: introduce code generators

In this context, "code generators" are functions that receive decoded instruction operands and emit TCG ops implementing the correct instruction functionality. Introduce the naming macros first, actual generator macros will be added later. Signed-off-by: Jan Bobek --- target/i386/t

[Qemu-devel] [RFC PATCH v3 25/46] target/i386: introduce Ib (immediate) operand

Introduce the immediate-byte operand, which loads a byte from the instruction stream and passes its value as the operand. Signed-off-by: Jan Bobek --- target/i386/translate.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/i386/translate.c b/target/i386

[Qemu-devel] [RFC PATCH v3 19/46] target/i386: introduce generic load-store operand

This operand attempts to capture the "indirect" or "memory" operand in a generic way. It significatly reduces the amount code that needs to be written in order to read operands from memory to temporary storage and write them back. Signed-off-by: Jan Bobek --- target/i

[Qemu-devel] [RFC PATCH v3 24/46] target/i386: introduce operand vex_v

This operand yields value of the VEX. field. Signed-off-by: Jan Bobek --- target/i386/translate.c | 20 1 file changed, 20 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index c918065b96..4562a097fa 100644 --- a/target/i386/translate.c

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