nt entries where the target node has no
memory. These could be surpressed but it isn't 'wrong' to provide
them and it is (probably) permissible under ACPI to hotplug memory
into these nodes later.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 -
tests/dat
Add a test with 6 nodes to exercise most interesting corner cases
of SRAT and HMAT generation including the new Generic Initiator
and Generic Port Affinity structures. More details of the
set up in the following patch adding the table data.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios
-by: Jonathan Cameron
---
v2: Updates to QMP documentation to provide a lot more information
on the parameters.
---
qapi/qom.json| 35 ++
include/hw/acpi/acpi_generic_initiator.h | 18 ++-
include/hw/pci/pci_bridge.h | 1 +
hw/acpi
The test to be added exercises many corners of the SRAT and HMAT
table generation.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
tests/data/acpi/q35/APIC.acpihmat-generic-x | 0
tests/data/acpi/q35/CEDT.acpihmat-generic-x | 0
tests/data/acpi/q35
This will simplify reuse when adding acpi-generic-port.
Note that some error_printf() messages will now print acpi-generic-node
whereas others will move to type specific cases in next patch so
are left alone for now.
Signed-off-by: Jonathan Cameron
---
v2: Fix a typo in comment.
---
include/hw
Before making additional modification, tidy up this misleading indentation.
Reviewed-by: Ankit Agrawal
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/acpi_generic_initiator.c b/hw/acpi
).
https://lore.kernel.org/qemu-devel/2eb6672cfdaea7dacd8e9bb0523887f13b9f85ce.1710282274.git@redhat.com/
https://lore.kernel.org/qemu-devel/74e2845c5f95b0c139c79233ddb65bb17f2dd679.1710282274.git@redhat.com/
Jonathan Cameron (6):
hw/acpi/GI: Fix trivial parameter alignment issue.
hw/acpi
On Tue, 21 May 2024 16:38:53 -0700
fan wrote:
> On Mon, May 20, 2024 at 05:50:12PM +0100, Jonathan Cameron wrote:
> > On Wed, 1 May 2024 15:29:31 -0700
> > fan wrote:
> >
> > > From 873f59ec06c38645768ada452d9b18920a34723e Mon Sep 17 00:00:00 2001
> > >
On Tue, 21 May 2024 16:32:52 -0700
fan wrote:
> From 9d6d774ec973d22c0f662b32385345a88b14cc55 Mon Sep 17 00:00:00 2001
> From: Fan Ni
> Date: Tue, 20 Feb 2024 09:48:31 -0800
> Subject: [PATCH 11/14] hw/cxl/events: Add qmp interfaces to add/release
> dynamic capacity extents
>
> To simulate FM
On Wed, 1 May 2024 15:29:31 -0700
fan wrote:
> From 873f59ec06c38645768ada452d9b18920a34723e Mon Sep 17 00:00:00 2001
> From: Fan Ni
> Date: Tue, 20 Feb 2024 09:48:31 -0800
> Subject: [PATCH] hw/cxl/events: Add qmp interfaces to add/release dynamic
> capacity extents
> Status: RO
>
On Fri, 17 May 2024 11:14:41 +0100
Jonathan Cameron wrote:
> On Fri, 17 May 2024 18:07:07 +0800
> Yuquan Wang wrote:
>
> > On Fri, May 10, 2024 at 06:16:46PM +0100, Jonathan Cameron wrote:
> > >
> > > https://git.kernel.org/pub/scm/linux/kernel/git/jic2
On Thu, 16 May 2024 10:05:33 -0700
fan wrote:
> On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > On Thu, Apr 18, 2024 at 04:10:51PM -0700, nifan@gmail.com wrote:
> > > A git tree of this series can be found here (with one extra commit on top
> > > for printing out
On Fri, 17 May 2024 18:07:07 +0800
Yuquan Wang wrote:
> On Fri, May 10, 2024 at 06:16:46PM +0100, Jonathan Cameron wrote:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/jic23/cxl-staging.git/log/?h=arm-numa-fixes
> >
> Thank you :)
> > I've run out of
On Thu, 9 May 2024 16:35:34 +0800
Yuquan Wang wrote:
> On Wed, May 08, 2024 at 01:02:52PM +0100, Jonathan Cameron wrote:
> >
> > > [0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x4000-0xbfff]
> > > [0.00] ACPI: SRAT: Node 1 PXM 1 [mem 0xc000-0x13f
On Fri, 3 May 2024 18:42:31 +0800
Shiyang Ruan wrote:
> 在 2024/4/24 1:57, Ira Weiny 写道:
> > Shiyang Ruan wrote:
> >> Currently driver only traces cxl events, poison creation (for both vmem
> >> and pmem type) on cxl memdev is silent. OS needs to be notified then it
> >> could handle poison
On Wed, 8 May 2024 16:00:51 +0800
Yuquan Wang wrote:
> Hello, Jonathan
>
> Recently I run some cxl tests on qemu virt(branch:cxl-2024-04-22-draft) but
> met some
> problems.
>
> Problems:
> 1) the virt machine could not set the right numa topology from user input;
>
> My Qemu numa set:
>
On Tue, 7 May 2024 00:22:00 +
"Xingtao Yao (Fujitsu)" wrote:
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Tuesday, April 30, 2024 10:43 PM
> > To: Yao, Xingtao/姚 幸涛
> > Cc: fan...@samsung.com; qemu-devel@nongnu.org
> > Su
> > >> > +# @hid: host id
> > >>
> > >> @host-id, unless "HID" is established terminology in CXL DCD land.
> > >
> > > host-id works.
> > >>
> > >> What is a host ID?
> > >
> > > It is an id identifying the host to which the capacity is being added.
> >
> > How are these IDs
On Mon, 29 Apr 2024 09:58:42 +0200
Markus Armbruster wrote:
> fan writes:
>
> > On Fri, Apr 26, 2024 at 11:12:50AM +0200, Markus Armbruster wrote:
> >> nifan@gmail.com writes:
>
> [...]
>
> >> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> >> > index 4281726dec..2dcf03d973 100644
>
On Wed, 24 Apr 2024 01:36:56 +
"Xingtao Yao (Fujitsu)" wrote:
> ping.
>
> > -Original Message-
> > From: Yao Xingtao
> > Sent: Sunday, April 7, 2024 11:07 AM
> > To: jonathan.came...@huawei.com; fan...@samsung.com
> > Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛
> > Subject:
On Tue, 30 Apr 2024 08:55:12 +0200
Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > On Tue, 23 Apr 2024 12:56:21 +0200
> > Markus Armbruster wrote:
> >
> >> Jonathan Cameron writes:
> >>
> >> > These are very similar to th
On Tue, 23 Apr 2024 12:56:21 +0200
Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > These are very similar to the recently added Generic Initiators
> > but instead of representing an initiator of memory traffic they
> > represent an edge point beyond whic
On Thu, 25 Apr 2024 10:30:51 -0700
Ira Weiny wrote:
> Markus Armbruster wrote:
> > fan writes:
> >
> > > On Wed, Apr 24, 2024 at 03:09:52PM +0200, Markus Armbruster wrote:
> > >> nifan@gmail.com writes:
> > >>
> > >> > From: Fan Ni
> > >> >
> > >> > Since fabric manager emulation
On Wed, 24 Apr 2024 10:33:33 -0700
Ira Weiny wrote:
> Markus Armbruster wrote:
> > nifan@gmail.com writes:
> >
> > > From: Fan Ni
> > >
> > > Since fabric manager emulation is not supported yet, the change implements
> > > the functions to add/release dynamic capacity extents as QMP
On Mon, 22 Apr 2024 15:23:16 +0100
Jonathan Cameron wrote:
> On Mon, 22 Apr 2024 13:04:48 +0100
> Jonathan Cameron wrote:
>
> > On Sat, 20 Apr 2024 16:35:46 -0400
> > Gregory Price wrote:
> >
> > > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
On Mon, 22 Apr 2024 13:04:48 +0100
Jonathan Cameron wrote:
> On Sat, 20 Apr 2024 16:35:46 -0400
> Gregory Price wrote:
>
> > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > &g
On Sat, 20 Apr 2024 16:35:46 -0400
Gregory Price wrote:
> On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > >
> > > added review to all patches, will hopefully be able to add a Tested-by
> > > tag early next week, along
On Thu, 18 Apr 2024 16:11:00 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
Hi Fan,
Please expand CC list to include QAPI maintainers.
+CC Markus and Micheal.
Also, for future versions +CC Michael Tsirkin.
I'm find rolling these up as a series with the precursors but
if it is already some
On Fri, 19 Apr 2024 13:27:59 -0400
Gregory Price wrote:
> On Thu, Apr 18, 2024 at 04:10:57PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > Add (file/memory backed) host backend for DCD. All the dynamic capacity
> > regions will share a single, large enough host backend. Set up
On Thu, 18 Apr 2024 16:10:57 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend for DCD. All the dynamic capacity
> regions will share a single, large enough host backend. Set up address
> space for DC regions to support read/write operations to dynamic
On Fri, 19 Apr 2024 17:40:07 +0200
Philippe Mathieu-Daudé wrote:
> On 18/4/24 12:04, Zhao Liu wrote:
> > From: Zhao Liu
>
>
> > ---
> > Zhao Liu (3):
> >hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean
> >hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean
> >
On Fri, 19 Apr 2024 13:52:07 +0200
Gerd Hoffmann wrote:
> Hi,
>
> > Gerd, any ideas? Maybe I needs something subtly different in my
> > edk2 build? I've not looked at this bit of the qemu infrastructure
> > before - is there a document on how that image is built?
>
> There is
ry type is created for storing all memory types that are
> not initialized by device drivers and as a fallback.
>
> Signed-off-by: Ho-Ren (Jack) Chuang
> Signed-off-by: Hao Xiang
> Reviewed-by: "Huang, Ying"
Reviewed-by: Jonathan Cameron
On Thu, 18 Apr 2024 09:15:55 +0100
Jonathan Cameron via wrote:
> On Wed, 17 Apr 2024 13:07:35 -0700
> Richard Henderson wrote:
>
> > On 4/16/24 08:11, Jonathan Cameron wrote:
> > > On Fri, 1 Mar 2024 10:41:09 -1000
> > > Richard Henderson wrote:
> > &
cdat() return boolean
> >hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean
>
> Series:
> Reviewed-by: Philippe Mathieu-Daudé
>
Acked-by: Jonathan Cameron
On Wed, 17 Apr 2024 13:07:35 -0700
Richard Henderson wrote:
> On 4/16/24 08:11, Jonathan Cameron wrote:
> > On Fri, 1 Mar 2024 10:41:09 -1000
> > Richard Henderson wrote:
> >
> >> If translation is disabled, the default memory type is Device, which
&g
On Tue, 16 Apr 2024 09:37:09 -0700
fan wrote:
> On Tue, Apr 16, 2024 at 04:00:56PM +0100, Jonathan Cameron wrote:
> > On Mon, 15 Apr 2024 10:37:00 -0700
> > fan wrote:
> >
> > > On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > > >
> > >
> > > ret = cxl_detect_malformed_extent_list(ct3d, in);
> > > if (ret != CXL_MBOX_SUCCESS) {
> > > +cxl_extent_group_list_delete_front(>dc.extents_pending);
> >
> > If it's a bad message from the host, I don't think the device is supposed to
> > do anything with
On Fri, 1 Mar 2024 10:41:09 -1000
Richard Henderson wrote:
> If translation is disabled, the default memory type is Device, which
> requires alignment checking. This is more optimally done early via
> the MemOp given to the TCG memory operation.
>
> Reviewed-by: Philippe Mathieu-Daudé
>
t; extent is added, all the bits of the blocks in the extent will be set,
> > > which will be cleared when the extent is released.
> > >
> > > Reviewed-by: Jonathan Cameron
> > > Signed-off-by: Fan Ni
> > > ---
> > > hw/cxl/cxl-mailbox-utils.c
On Mon, 15 Apr 2024 13:06:04 -0700
fan wrote:
> From ce75be83e915fbc4dd6e489f976665b81174002b Mon Sep 17 00:00:00 2001
> From: Fan Ni
> Date: Tue, 20 Feb 2024 09:48:31 -0800
> Subject: [PATCH 09/13] hw/cxl/events: Add qmp interfaces to add/release
> dynamic capacity extents
>
> To simulate FM
On Tue, 9 Apr 2024 15:58:46 +0800
Li Zhijian wrote:
> After the kernel commit
> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not
> match a CFMWS window")
> CXL type3 devices cannot be enabled again after the reboot because the
> control register(see 8.1.3.2 in CXL
On Tue, 9 Apr 2024 14:26:51 -0700
fan wrote:
> On Fri, Apr 05, 2024 at 01:18:56PM +0100, Jonathan Cameron wrote:
> > On Mon, 25 Mar 2024 12:02:27 -0700
> > nifan@gmail.com wrote:
> >
> > > From: Fan Ni
> > >
> > > To simulate FM fun
On Tue, 9 Apr 2024 12:02:31 -0700
"Ho-Ren (Jack) Chuang" wrote:
> Hi Jonathan,
>
> On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 15:43:47 -0700
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> >
On Fri, 5 Apr 2024 15:43:47 -0700
"Ho-Ren (Jack) Chuang" wrote:
> On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 00:07:06 +
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> > > The current implemen
On Fri, 5 Apr 2024 14:09:23 -0400
Gregory Price wrote:
> On Fri, Apr 05, 2024 at 06:44:52PM +0100, Jonathan Cameron wrote:
> > On Fri, 5 Apr 2024 12:07:45 -0400
> > Gregory Price wrote:
> >
> > > 3. (C) Upon Device receiving Release Dynamic Capacity Request
&
On Mon, 8 Apr 2024 13:58:00 +0200
Marcin Juszkiewicz wrote:
> For quite a while I am experimenting with PCI Express setup on SBSA-Ref
> system. And finally decided to write.
>
> We want to play with NUMA setup and "pxb-pcie" can be assigned to NUMA
> node other than cpu0 one. But adding it
On Fri, 5 Apr 2024 12:07:45 -0400
Gregory Price wrote:
> On Fri, Apr 05, 2024 at 01:27:19PM +0100, Jonathan Cameron wrote:
> > On Wed, 3 Apr 2024 14:16:25 -0400
> > Gregory Price wrote:
> >
> > A few follow up comments.
> >
> > >
> >
On Fri, 15 Mar 2024 10:29:07 +0800
Shiyang Ruan wrote:
> 在 2024/2/14 0:51, Jonathan Cameron 写道:
> >
> >> +
> >> +void cxl_event_handle_record(struct cxl_memdev *cxlmd,
> >> + enum cxl_event_log_type type,
> >> +
On Mon, 1 Apr 2024 17:00:50 +0100
Jonathan Cameron via wrote:
> On Thu, 28 Mar 2024 06:24:24 +
> "Xingtao Yao (Fujitsu)" wrote:
>
> > Jonathan
> >
> > thanks for your reply!
> >
> > > -----Original Message-
> > > From: Jo
On Fri, 5 Apr 2024 00:07:06 +
"Ho-Ren (Jack) Chuang" wrote:
> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics
gned-off-by: Ho-Ren (Jack) Chuang
> Reviewed-by: "Huang, Ying"
Reviewed-by: Jonathan Cameron
the change, we relax the constraints. As long as the DPA range of
> the extent is covered by accepted extents, we allow the release.
>
> Signed-off-by: Fan Ni
Nice.
Reviewed-by: Jonathan Cameron
> ---
> hw/mem/cxl_type3.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
On Mon, 25 Mar 2024 12:02:29 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by accepted extent(s) in the device, the
t is added, all the bits of the blocks in the extent will be set,
> which will be cleared when the extent is released.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Fan Ni
On Wed, 3 Apr 2024 14:16:25 -0400
Gregory Price wrote:
A few follow up comments.
> On Mon, Mar 25, 2024 at 12:02:27PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > To simulate FM functionalities for initiating Dynamic Capacity Add
> > (Opcode 5604h) and Dynamic Capacity Release
On Mon, 25 Mar 2024 12:02:27 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> To simulate FM functionalities for initiating Dynamic Capacity Add
> (Opcode 5604h) and Dynamic Capacity Release (Opcode 5605h) as in CXL spec
> r3.1 7.6.7.6.5 and 7.6.7.6.6, we implemented two QMP interfaces to
On Mon, 25 Mar 2024 12:02:26 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Per CXL spec 3.1, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
>
> For the process of the above two
On Thu, 4 Apr 2024 13:32:23 +
Jørgen Hansen wrote:
Hi Jørgen,
> > +static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
> > + uint8_t *payload_in,
> > + size_t len_in,
> > +
Ni
One really minor comment inline.
Reviewed-by: Jonathan Cameron
>
> +/*
> + * CXL r3.1 section 8.2.9.9.9.2:
> + * Get Dynamic Capacity Extent List (Opcode 4801h)
> + */
> +static CXLRetCode cmd_dcd_get_dyn_cap_ext_list(const struct cxl_cmd *cmd,
> +
from the consortium in the long run.
With that tweaked.
Reviewed-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 16 ++-
> hw/mem/cxl_type3.c | 187 +---
> include/hw/cxl/cxl_device.h | 8 ++
> 3 files changed, 172 insertions(+), 39
On Wed, 3 Apr 2024 22:56:58 +0800
Shiyang Ruan wrote:
> 在 2024/3/30 9:50, Dan Williams 写道:
> > Shiyang Ruan wrote:
> >> The GMER only has "Physical Address" field, no such one indicates length.
> >> So, when a poison event is received, we could use GET_POISON_LIST command
> >> to get the
> > > @@ -858,7 +910,8 @@ static int __init memory_tier_init(void)
> > >* For now we can have 4 faster memory tiers with smaller adistance
> > >* than default DRAM tier.
> > >*/
> > > - default_dram_type = alloc_memory_type(MEMTIER_ADISTANCE_DRAM);
> > > +
A few minor comments inline.
> diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h
> index a44c03c2ba3a..16769552a338 100644
> --- a/include/linux/memory-tiers.h
> +++ b/include/linux/memory-tiers.h
> @@ -140,12 +140,13 @@ static inline int mt_perf_to_adistance(struct
>
On Tue, 2 Apr 2024 00:17:37 +
"Ho-Ren (Jack) Chuang" wrote:
> Since different memory devices require finding, allocating, and putting
> memory types, these common steps are abstracted in this patch,
> enhancing the scalability and conciseness of the code.
>
> Signed-off-by: Ho-Ren (Jack)
nt entries where the target node has no
memory. These could be surpressed but it isn't 'wrong' to provide
them and it is (probably) permissible under ACPI to hotplug memory
into these nodes later.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 -
tests/dat
Add a test with 6 nodes to exercise most interesting corner cases
of SRAT and HMAT generation including the new Generic Initiator
and Generic Port Affinity structures. More details of the
set up in the following patch adding the table data.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios
The test to be added exercises many corners of the SRAT and HMAT
table generation.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
tests/data/acpi/q35/APIC.acpihmat-generic-x | 0
tests/data/acpi/q35/CEDT.acpihmat-generic-x | 0
tests/data/acpi/q35
-by: Jonathan Cameron
---
qapi/qom.json| 18 +++
include/hw/acpi/acpi_generic_initiator.h | 18 ++-
include/hw/pci/pci_bridge.h | 1 +
hw/acpi/acpi_generic_initiator.c | 141 +--
hw/pci-bridge/pci_expander_bridge.c | 1
This will simplify reuse when adding acpi-generic-port.
Note that some error_printf() messages will now print acpi-generic-node
whereas others will move to type specific cases in next patch so
are left alone for now.
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/acpi_generic_initiator.h
Before making additional modification, tidy up this misleading indentation.
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/acpi_generic_initiator.c b/hw/acpi/acpi_generic_initiator.c
index
.1710282274.git@redhat.com/
https://lore.kernel.org/qemu-devel/74e2845c5f95b0c139c79233ddb65bb17f2dd679.1710282274.git@redhat.com/
Jonathan Cameron (6):
hw/acpi/GI: Fix trivial parameter alignment issue.
hw/acpi: Insert an acpi-generic-node base under acpi-generic-initiator
hw/acpi
On Tue, 2 Apr 2024 09:46:47 +0800
Li Zhijian wrote:
> After the kernel commit
> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not
> match a CFMWS window")
Fixes tag seems appropriate.
> CXL type3 devices cannot be enabled again after the reboot because this
> flag was
On Tue, 2 Apr 2024 09:46:46 +0800
Li Zhijian wrote:
> It helps to figure out where the first dvsec register is located. In
> addition, replace offset and size hardcore with existing macros.
>
> Signed-off-by: Li Zhijian
I agree we should be using the macros.
The offset calc is a bit
On Sun, 21 Jan 2024 21:50:00 -0500
Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> On Tue, Jan 9, 2024 at 12:54 PM Jonathan Cameron
> wrote:
> >
> > On Fri, 22 Dec 2023 18:00:50 +0900
> > Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> >
> > > The
ci_machine_done().
>
> Signed-off-by: Philippe Mathieu-Daudé
LGTM as a change on it's own - I've not reviewed the series
in general though, hence just an ack as an rb feels too strong.
Acked-by: Jonathan Cameron
On Wed, 27 Mar 2024 17:16:42 +0100
Philippe Mathieu-Daudé wrote:
> CXL is based on PCIe. In is pointless to initialize
> its context on non-PCI machines.
>
> Signed-off-by: Philippe Mathieu-Daudé
Seems a reasonable restriction.
Acked-by: Jonathan Cameron
Jonathan
> ---
>
On Thu, 28 Mar 2024 06:24:24 +
"Xingtao Yao (Fujitsu)" wrote:
> Jonathan
>
> thanks for your reply!
>
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Wednesday, March 27, 2024 9:28 PM
> > To: Yao, Xingtao/姚 幸涛
> >
On Tue, 26 Mar 2024 21:46:53 -0400
Yao Xingtao wrote:
> In 3, 6, 12 interleave ways, we could not access cxl memory properly,
> and when the process is running on it, a 'segmentation fault' error will
> occur.
>
> According to the CXL specification '8.2.4.20.13 Decoder Protection',
> there are
learing %u\n", log,
> - le16_to_cpu(payload->handles[i]));
> + le16_to_cpu(payload->handles[i-1]));
Trivial but needs spaces around the -. e.g. [i - 1]
Maybe Dan can fix up whilst applying.
Otherwise
Reviewed-by: Jonathan Cameron
>
> if (i == max_handles) {
> payload->nr_recs = i;
On Wed, 13 Mar 2024 21:24:06 +0300
Michael Tokarev wrote:
> 07.03.2024 19:03, Jonathan Cameron via wrote:
> > With a numa set up such as
> >
> > -numa nodeid=0,cpus=0 \
> > -numa nodeid=1,memdev=mem \
> > -numa nodeid=2,cpus=1
> >
> > and a
On Fri, 15 Mar 2024 09:52:28 +0800
Yuquan Wang wrote:
> Hello, Jonathan
>
> When during the test of qmps of CXL events like
> "cxl-inject-general-media-event",
> I am confuesd about the argument "flags". According to "qapi/cxl.json" in
> qemu,
> this argument represents "Event Record Flags"
On Fri, 8 Mar 2024 20:35:53 -0800
fan wrote:
> On Thu, Mar 07, 2024 at 12:45:55PM +0000, Jonathan Cameron wrote:
> > ...
> >
> > > > > +list = records;
> > > > > +extents = g_new0(CXLDCExtentRaw, num_extents);
> > > >
CPI Spec 6.3, Section 5.2.16.6
>
> Suggested-by: Jonathan Cameron
Reviewed-by: Jonathan Cameron
> Signed-off-by: Ankit Agrawal
> ---
> hw/i386/acpi-build.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> ind
On Fri, 8 Mar 2024 14:38:55 +
Peter Maydell wrote:
> On Fri, 8 Mar 2024 at 14:34, Jonathan Cameron
> wrote:
> >
> > On Fri, 8 Mar 2024 13:47:47 +
> > Peter Maydell wrote:
> > > Is there a way we could write this that would catch this error?
> &
the value.
Fixes: Coverity ID 1534095 buffer overrun
Fixes: 8700ee15de ("hw/cxl: Standardize all references on CXL r3.1 and minor
updates")
Reported-by: Peter Maydell
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_pci.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On Fri, 8 Mar 2024 13:47:47 +
Peter Maydell wrote:
> On Wed, 14 Feb 2024 at 11:16, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > Previously not all references mentioned any spec version at all.
> > Given r3.1 is the current speci
On Fri, 8 Mar 2024 10:01:34 +0800
Yuquan Wang wrote:
> On 2024-03-07 20:10, jonathan.cameron wrote:
>
> > Hack is fine the relevant device with lspci -tv and then use
> > setpci -s 0d:00.0 0x208.l=0
> > to clear all the mask bits for uncorrectable errors.
>
> Thanks! The suggestions from
On Thu, 4 Jan 2024 00:44:43 +
Hao Xiang wrote:
> * Add a DSA task completion callback.
> * DSA completion thread will call the tasks's completion callback
> on every task/batch task completion.
> * DSA submission path to wait for completion.
> * Implement CPU fallback if DSA is not able to
array.
Stash the reverse lookup when writing the initiator list and use
it to get the correct array index index.
Fixes: 4586a2cb83 ("hmat acpi: Build System Locality Latency and Bandwidth
Information Structure(s)")
Signed-off-by: Jonathan Cameron
---
hw/acpi/hmat.c | 6 +-
1 file
it breaks Linux HMAT passing and the table is rejected.
https://elixir.bootlin.com/linux/v6.7/source/drivers/acpi/numa/hmat.c#L444
Signed-off-by: Jonathan Cameron
v2: Fix link in patch description to be stable.
---
hw/acpi/hmat.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw
Structures (and I have patches for those to follow shortly)
but that's overly optimistic beyond CXL where the kernel will use
them and which drove their introduction.
Jonathan Cameron (2):
hmat acpi: Do not add Memory Proximity Domain Attributes Structure
targetting non existent memory
dy handles MMIO accesses.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Suggested-by: Peter Maydell
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
v3: No change.
target/i386/tcg/sysemu/excp_helper.c | 57 +++-
1 file changed, 30
Previously: tcg/i386: Page tables in MMIO memory fixes (CXL)
Richard Henderson picked up patches 1 and 3 which were architecture independent
leaving just this x86 specific patch.
No change to the patch. Resending because it's hard to spot individual
unapplied patches in a larger series.
Original
this by adding new address_space_read_continue_cached()
and address_space_write_continue_cached() which share all the logic
with the flatview versions except for the MemoryRegion lookup which
is unnecessary as the MemoryRegionCache only covers one MemoryRegion.
Signed-off-by: Jonathan Cameron
---
v2
This code will be reused for the address_space_cached accessors
shortly.
Also reduce scope of result variable now we aren't directly
calling this in the loop.
Signed-off-by: Jonathan Cameron
---
v2: Thanks to Peter Xu
- Fix alignment of code.
- Drop unused addr parameter.
- Carry through new
Precursor to factoring out the inner loops for reuse.
Reviewed-by: Peter Xu
Signed-off-by: Jonathan Cameron
---
v2: Picked up tag from Peter.
system/physmem.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/system/physmem.c b
the parameter in address_space_read/write_cached_slow()
Suggested-by: Peter Xu
Signed-off-by: Jonathan Cameron
---
v2: New patch.
- I have kept the renames to only the code I'm touching later in this
series, but they could be applied much more widely.
---
system/physmem.c | 50
mr_addr.
To avoid duplicating most of the code, the next 2 patches factor out
the common parts of flatview_read_continue() and flatview_write_continue()
so they can be reused.
Write path has not been tested but it so similar to the read path I've
included it here.
Jonathan Cameron (4):
physmem
On Fri, 1 Mar 2024 13:44:01 +0800
Peter Xu wrote:
> On Thu, Feb 15, 2024 at 02:28:17PM +0000, Jonathan Cameron wrote:
>
> Can we rename the subject?
>
> physmem: Fix wrong MR in large address_space_read/write_cached_slow()
>
> IMHO "wrong MR" is misleading, a
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