From: Huai-Cheng Kuo
The Data Object Exchange implementation of CXL Coherent Device Attribute
Table (CDAT). This implementation is referring to "Coherent Device
Attribute Table Specification, Rev. 1.03, July. 2022" and "Compute
Express Link Specification, Rev. 3.0, July. 2022"
This patch adds
This Data Object Exchange Mailbox allows software to query the
latency and bandwidth between ports on the switch. For now
only provide information on routes between the upstream port and
each downstream port (not p2p).
Signed-off-by: Jonathan Cameron
--
Changes since v7:
- Moved to enum for
From: Huai-Cheng Kuo
Emulation of PCIe Data Object Exchange (DOE)
PCIE Base Specification r6.0 6.3 Data Object Exchange
Supports multiple DOE PCIe Extended Capabilities for a single PCIe
device. For each capability, a static array of DOEProtocol should be passed
to pcie_doe_init(). The
Changes since v7: Details in individual patches:
Thanks to Gregory Price for reviewing!
- Fix heap corruption.
- Check allocations succeed.
- Substantial refactor of type 3 cdat table build to make it
simpler and easier to add volatile entry support.
V7 Cover letter - lightly edited.
From: Huai-Cheng Kuo
The CDAT can be specified in two ways. One is to add ",cdat="
in "-device cxl-type3"'s command option. The file is required to provide
the whole CDAT table in binary mode. The other is to use the default
that provides some 'reasonable' numbers based on type of memory and
On Thu, 13 Oct 2022 07:36:28 -0400
Gregory Price wrote:
> Reading through your notes, everything seems reasonable, though I'm not
> sure I agree with the two pass notion, though I'll wait to see the patch
> set.
>
> The enum is a good idea, *forehead slap*, I should have done it. If we
> have
On Fri, 7 Oct 2022 16:21:54 +0100
Jonathan Cameron wrote:
> From: Huai-Cheng Kuo
>
> The Data Object Exchange implementation of CXL Coherent Device Attribute
> Table (CDAT). This implementation is referring to "Coherent Device
> Attribute Table Specification, Rev. 1.02, Oct. 2020" and "Compute
On Wed, 12 Oct 2022 14:21:20 -0400
Gregory Price wrote:
> The CDAT can contain multiple entries for multiple memory regions, this
> will allow us to re-use the initialization code when volatile memory
> region support is added.
>
> Signed-off-by: Gregory Price
I'm in two minds about this...
On Wed, 12 Oct 2022 14:21:18 -0400
Gregory Price wrote:
> Makes the size of the allocated cdat table static (6 entries),
> flattens the code, and reduces the number of exit conditions
>
> Signed-off-by: Gregory Price
Hmm. I don't entirely like this as it stands because it leads to more
On Wed, 12 Oct 2022 14:21:19 -0400
Gregory Price wrote:
> The existing code allocates a subtable for SLBIS entries, uses a
> local variable to avoid a g_autofree footgun, and the cleanup code
> causes heap corruption.
Ah good point (particularly given I moaned about how you were handling
the
On Wed, 12 Oct 2022 12:01:54 -0400
Gregory Price wrote:
> This code contains heap corruption on free, and I think should be
> refactored to pre-allocate all the entries we're interested in putting
> into the table.
Good point on the heap corruption.. (oops. Particularly as I raised
that I
On Wed, 12 Oct 2022 12:01:54 -0400
Gregory Price wrote:
> This code contains heap corruption on free, and I think should be
> refactored to pre-allocate all the entries we're interested in putting
> into the table. This would flatten the code and simplify the error
> handling steps.
>
> Also,
On Thu, 13 Oct 2022 10:07:40 +0100
Jonathan Cameron wrote:
> On Wed, 12 Oct 2022 14:21:17 -0400
> Gregory Price wrote:
>
> > For style - pulling these validations ahead flattens the code.
>
> True, but at the cost of separating the check from where it is
> obvious why we have the check.
On Wed, 12 Oct 2022 14:21:17 -0400
Gregory Price wrote:
> For style - pulling these validations ahead flattens the code.
True, but at the cost of separating the check from where it is
obvious why we have the check. I'd prefer to see it next to the
use.
Inverting the hostmem check is
On Wed, 12 Oct 2022 14:21:15 -0400
Gregory Price wrote:
> Included in this response is a recommended patch set on top of this
> patch that resolves a number of issues, including style and a heap
> corruption bug.
>
> The purpose of this patch set is to refactor the CDAT initialization
> code to
On Tue, 11 Oct 2022 17:19:14 -0400
Gregory Price wrote:
> This is a preparatory commit for enabling multiple memory regions within
> a single CXL Type-3 device. We will need to initialize multiple CDAT
> DSMAS regions (and subsequent DSLBIS, and DSEMTS entries), so generalize
> the
On Tue, 11 Oct 2022 13:22:40 -0400
Gregory Price wrote:
> I'll push the patches to qemu-cxl and linux-cxl today or tomorrow, I
> wanted to get them into a state on gitlab for Jonathan to rebase and
> merge into his work. He'll likely end up pushing the entire series at
> the end of the day.
>
On Mon, 10 Oct 2022 15:29:44 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
> commands. Enable those commands to control interrupts for each of the
> event log types.
>
> Signed-off-by: Ira Weiny
A few trivial
On Mon, 10 Oct 2022 15:29:43 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> To facilitate testing of event interrupt support add a QMP HMP command
> to reset the event logs and issue interrupts when the guest has enabled
> those interrupts.
Two things in here, so probably wants breaking
On Mon, 10 Oct 2022 15:29:42 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Replace the stubbed out CXL Get/Clear Event mailbox commands with
> commands which return the mock event information.
>
> Signed-off-by: Ira Weiny
> ---
> hw/cxl/cxl-device-utils.c | 1 +
>
On Mon, 10 Oct 2022 15:29:41 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> To facilitate testing of guest software add mock events and code to
> support iterating through the event logs.
>
> Signed-off-by: Ira Weiny
Various comments inline, but biggest one is I'd like to see
a much
On Mon, 10 Oct 2022 15:29:38 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> CXL Event records inform the OS of various CXL device events. Thus far CXL
> memory devices are emulated and therefore don't naturally have events which
> will occur.
>
> Add mock events and a HMP trigger
On Mon, 10 Oct 2022 15:29:40 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> UUID's are defined as network byte order fields. No static initializer
> was available for UUID's in their standard big endian format.
>
> Define a big endian initializer for UUIDs.
>
> Signed-off-by: Ira
On Mon, 10 Oct 2022 15:29:39 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Gcc requires constant versions of cpu_to_le* calls.
>
> Add a 64 bit version.
>
> Signed-off-by: Ira Weiny
Seems reasonable to me but I'm not an expert in this stuff.
FWIW
Reviewed-by: Jonathan Cameron
> > but i'm not sure of what to do with this info. We have some proof
> > that real hardware works with this no problem, and the only difference
> > is that the EFI/bios/firmware is setting the memory regions as `usable`
> > or `soft reserved`, which would imply the EDK2 is the blocker here
> >
On Mon, 10 Oct 2022 11:20:05 -0400
Gregory Price wrote:
> > >
> > > Maybe we should consider 2 new options:
> > > --persistent-memdevs=pm1 pm2 pm3
> > > --volatile-memdevs=vm1 vm2 vm3
> > >
> > > etc, and deprecate --memdev, and go with your array of memdevs idea.
> > >
> > > I think I could
On Fri, 19 Aug 2022 09:46:55 +0100
Jonathan Cameron wrote:
> On Thu, 18 Aug 2022 17:37:40 +0100
> Jonathan Cameron via wrote:
>
> > On Wed, 17 Aug 2022 17:16:19 +0100
> > Jonathan Cameron wrote:
> >
> > > On Thu, 11 Aug 2022 17:46:55 -0700
> > >
On Thu, 6 Oct 2022 19:37:02 -0400
Gregory Price wrote:
> This commit enables setting one memory region for a type-3 device, but
> that region may now be either a persistent region or volatile region.
>
> Future work may enable setting both regions simultaneously, as this is
> a possible
On Fri, 7 Oct 2022 10:50:12 -0400
Gregory Price wrote:
> Now that i've had some time to look at the spec, the DVSEC CXL Capability
> register (8.1.3.1 in 3.0 spec)
> only supports enabling two HDM ranges at the moment, which to me means we
> should implement
>
> memdev0=..., memdev1=...
That
>
> I was unaware that an SLD could be comprised of multiple regions
> of both persistent and volatile memory. I was under the impression that
> it could only be one type of memory. Of course that makes sense in the
> case of a memory expander that simply lets you plug DIMMs in *facepalm*
>
On Fri, 7 Oct 2022 16:21:51 +0100
Jonathan Cameron wrote:
> Whilst I have carried on Huai-Cheng Kuo's series version numbering and
> naming, there have been very substantial changes since v6 so I would
> suggest fresh review makes sense for anyone who has looked at this before.
> In particularly
From: Huai-Cheng Kuo
The CDAT can be specified in two ways. One is to add ",cdat="
in "-device cxl-type3"'s command option. The file is required to provide
the whole CDAT table in binary mode. The other is to use the default
that provides some 'reasonable' numbers based on type of memory and
From: Huai-Cheng Kuo
The Data Object Exchange implementation of CXL Coherent Device Attribute
Table (CDAT). This implementation is referring to "Coherent Device
Attribute Table Specification, Rev. 1.02, Oct. 2020" and "Compute
Express Link Specification, Rev. 2.0, Oct. 2020"
This patch adds
On Thu, 6 Oct 2022 19:37:01 -0400
Gregory Price wrote:
> Current code sets to STORAGE_EXPRESS and then overrides it.
>
> Signed-off-by: Gregory Price
I'm carry the same patch after you reported it the other day.
Reviewed-by: Jonathan Cameron
> ---
> hw/mem/cxl_type3.c | 3 +--
> 1 file
Whilst I have carried on Huai-Cheng Kuo's series version numbering and
naming, there have been very substantial changes since v6 so I would
suggest fresh review makes sense for anyone who has looked at this before.
In particularly if the Avery design folks could check I haven't broken
anything
This Data Object Exchange Mailbox allows software to query the
latency and bandwidth between ports on the switch. For now
only provide information on routes between the upstream port and
each downstream port (not p2p).
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_upstream.c | 182
This will be used by several upcoming patch sets so break it out
such that it doesn't matter which one lands first.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index
From: Huai-Cheng Kuo
Emulation of PCIe Data Object Exchange (DOE)
PCIE Base Specification r6.0 6.3 Data Object Exchange
Supports multiple DOE PCIe Extended Capabilities for a single PCIe
device. For each capability, a static array of DOEProtocol should be passed
to pcie_doe_init(). The
On Thu, 6 Oct 2022 11:52:06 -0400
Gregory Price wrote:
> On Thu, Oct 06, 2022 at 09:50:07AM +0100, Jonathan Cameron wrote:
> > On Thu, 6 Oct 2022 09:45:57 +0100
> > Jonathan Cameron wrote:
> >
> > > Great to see this.
> > >
> > > Missing Signed-off by so we can't apply this (no developer
On Thu, 6 Oct 2022 09:45:57 +0100
Jonathan Cameron wrote:
> On Wed, 5 Oct 2022 20:01:03 -0400
> Gourry wrote:
>
> > Type 3 devices were hard-coded to always present as persistent memory
> > devices.
> > This patch adds the "is_pmem" attribute which can be used to instantiate
> > a device as
On Wed, 5 Oct 2022 20:01:03 -0400
Gourry wrote:
> Type 3 devices were hard-coded to always present as persistent memory devices.
> This patch adds the "is_pmem" attribute which can be used to instantiate
> a device as either a pmem or vmem.
Hi Gourry,
Great to see this.
Missing Signed-off by
The Device Serial Number Extended Capability PCI r6.0 sec 7.9.3
provides a standard way to provide a device serial number as
an IEEE defined 64-bit extended unique identifier EUI-64.
CXL 2.0 section 8.1.12.2 Memory Device PCIe Capabilities and
Extended Capabilities requires this to be used to
On Thu, 22 Sep 2022 21:11:39 +0800
Yicong Yang wrote:
> From: Yicong Yang
>
> This series mainly change the policy for building a cluster topology node
> in PPTT. Previously we'll always build a cluster node in PPTT without
> asking the user, after this set the cluster node will be built only
On Thu, 15 Sep 2022 17:59:04 +
Tong Zhang wrote:
> The structure is for device dvsec not port dvsec. Change type to fix
> this issue.
>
> Signed-off-by: Tong Zhang
Acked-by: Jonathan Cameron
> ---
> hw/mem/cxl_type3.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
CXL 3.0 introduces a CXL Performance Monitoring Unit.
Add basic emulation of such units and instantiate 2 in
CXL Type 3 devices.
Limitations:
- Random selection of supported events.
- Mixture of fixed purpose and configurable counters is intended
to hit some edge cases in the discovery code,
Allows for easier looping over entries when adding CPMU instances.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 8
hw/pci-bridge/cxl_downstream.c | 4 ++--
hw/pci-bridge/cxl_root_port.c | 4 ++--
hw/pci-bridge/cxl_upstream.c | 4 ++--
This will be used by several upcoming patch sets so break it out
such that it doesn't matter which one lands first.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index
CXL 3.0 introduces a CXL Performance Monitoring Unit.
(13.2 Performance Monitoring)
These unit may be present in any CXL component but for now the kernel
code only supports them in Type 3 Memory devices.
Add basic emulation of such units and instantiate 2 in each CXL Type 3 device.
Kernel driver
On Thu, 18 Aug 2022 17:37:40 +0100
Jonathan Cameron via wrote:
> On Wed, 17 Aug 2022 17:16:19 +0100
> Jonathan Cameron wrote:
>
> > On Thu, 11 Aug 2022 17:46:55 -0700
> > Dan Williams wrote:
> >
> > > Dan Williams wrote:
> >
On Wed, 17 Aug 2022 17:16:19 +0100
Jonathan Cameron wrote:
> On Thu, 11 Aug 2022 17:46:55 -0700
> Dan Williams wrote:
>
> > Dan Williams wrote:
> > > Bobo WL wrote:
> > > > Hi Dan,
> > > >
> > > > Thanks for your reply!
> > > >
> > > > On Mon, Aug 8, 2022 at 11:58 PM Dan Williams
> >
On Thu, 11 Aug 2022 17:46:55 -0700
Dan Williams wrote:
> Dan Williams wrote:
> > Bobo WL wrote:
> > > Hi Dan,
> > >
> > > Thanks for your reply!
> > >
> > > On Mon, Aug 8, 2022 at 11:58 PM Dan Williams
> > > wrote:
> > > >
> > > > What is the output of:
> > > >
> > > > cxl list -MDTu
Get LSA needs 4 byte offset and 4 byte length arguments.
CXL rev 2.0 Table 178.
Fixes: 3ebe676a34 ("hw/cxl/device: Implement get/set Label Storage Area (LSA)")
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
A placeholder of ~0 is used to indicate variable payload size.
Whilst the checks for output payload correctly took this into
account, those for input payload did not.
This results in failure of the Set LSA command.
Fixes: 464e14ac43 ("hw/cxl/device: Implement basic mailbox (8.2.8.4)")
There is no checking on the availability of a write callback.
Hence QEMU crashes if a write does occur to one of these regions.
Discovered whilst chasing a Linux kernel bug that incorrectly
wrote into one of these regions.
Fixes: 6364adacdf ("hw/cxl/device: Implement the CAP array (8.2.8.1-2)")
The recent addition of CXL Region setup to the 6.0-rc1 Linux kernel
has allowed us to test a few paths that weren't exercised fully until
now. That threw up a mixture of bugs in QEMU emulation and the kernel
(kernel fixes already posted).
The first patch is down to a wrong assumption about RO
On Mon, 8 Aug 2022 13:20:49 +0100
Jonathan Cameron wrote:
> Peter Maydell reported both these issues, having looked into Coverity
> identified issues. The memory leak was straight forward, but testing the
> second patch identified a bug in the Linux kernel.
>
> This bug has been fixed in the
On Mon, 15 Aug 2022 15:55:15 -0700
Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Fri, 12 Aug 2022 16:44:03 +0100
> > Jonathan Cameron wrote:
> >
> > > On Thu, 11 Aug 2022 18:08:57 +0100
> > > Jonathan Cameron via wrote:
> > &
On Mon, 15 Aug 2022 18:04:44 +0100
Jonathan Cameron wrote:
> On Fri, 12 Aug 2022 16:44:03 +0100
> Jonathan Cameron wrote:
>
> > On Thu, 11 Aug 2022 18:08:57 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 9 Aug 2022 17:08:25
On Fri, 12 Aug 2022 16:44:03 +0100
Jonathan Cameron wrote:
> On Thu, 11 Aug 2022 18:08:57 +0100
> Jonathan Cameron via wrote:
>
> > On Tue, 9 Aug 2022 17:08:25 +0100
> > Jonathan Cameron wrote:
> >
> > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > B
On Mon, 15 Aug 2022 15:18:09 +0100
Jonathan Cameron via wrote:
> On Fri, 12 Aug 2022 17:15:09 +0100
> Jonathan Cameron wrote:
>
> > On Fri, 12 Aug 2022 09:03:02 -0700
> > Dan Williams wrote:
> >
> > > Jonathan Cameron wrote:
> > > > On
On Fri, 12 Aug 2022 17:15:09 +0100
Jonathan Cameron wrote:
> On Fri, 12 Aug 2022 09:03:02 -0700
> Dan Williams wrote:
>
> > Jonathan Cameron wrote:
> > > On Thu, 11 Aug 2022 18:08:57 +0100
> > > Jonathan Cameron via wrote:
> > >
On Fri, 12 Aug 2022 09:03:02 -0700
Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Thu, 11 Aug 2022 18:08:57 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 9 Aug 2022 17:08:25 +0100
> > > Jonathan Cameron wrote:
> > >
> &
On Thu, 11 Aug 2022 18:08:57 +0100
Jonathan Cameron via wrote:
> On Tue, 9 Aug 2022 17:08:25 +0100
> Jonathan Cameron wrote:
>
> > On Tue, 9 Aug 2022 21:07:06 +0800
> > Bobo WL wrote:
> >
> > > Hi Jonathan
> > >
> > > Thanks for y
On Tue, 9 Aug 2022 17:08:25 +0100
Jonathan Cameron wrote:
> On Tue, 9 Aug 2022 21:07:06 +0800
> Bobo WL wrote:
>
> > Hi Jonathan
> >
> > Thanks for your reply!
> >
> > On Mon, Aug 8, 2022 at 8:37 PM Jonathan Cameron
> > wrote:
> > >
> > > Probably not related to your problem, but there is
On Tue, 9 Aug 2022 21:07:06 +0800
Bobo WL wrote:
> Hi Jonathan
>
> Thanks for your reply!
>
> On Mon, Aug 8, 2022 at 8:37 PM Jonathan Cameron
> wrote:
> >
> > Probably not related to your problem, but there is a disconnect in QEMU /
> > kernel assumptionsaround the presence of an HDM decoder
On Fri, 5 Aug 2022 10:20:23 +0800
Bobo WL wrote:
> Hi list
>
> I want to test cxl functions in arm64, and found some problems I can't
> figure out.
Hi Bob,
Glad to see people testing this code.
>
> My test environment:
>
> 1. build latest bios from https://github.com/tianocore/edk2.git
Use g_autofree to free the CXLFixedWindow structure if an
error occurs in configuration before we have added to
the list (via g_steal_pointer())
Fix Coverity CID: 1488872
Reported-by: Peter Maydell
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 5 +++--
1 file changed, 3
Two issues were present in this code:
1) Check on which register to look in was inverted.
2) Both branches use the _LO register.
Whilst here moved to extract32() rather than hand rolling
the field extraction as simpler and hopefully less error prone.
Fixes Coverity CID: 1488873
Reported-by:
Peter Maydell reported both these issues, having looked into Coverity
identified issues. The memory leak was straight forward, but testing the
second patch identified a bug in the Linux kernel.
This bug has been fixed in the series
On Wed, 20 Jul 2022 13:23:10 +0100
Peter Maydell wrote:
> On Mon, 16 May 2022 at 21:52, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > These memops perform interleave decoding, walking down the
> > CXL topology from CFMWS described host interleave
> > decoder via CXL host
On Thu, 30 Jun 2022 09:30:58 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jun 30, 2022 at 02:40:13PM +0200, Brice Goglin wrote:
> >
> > Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
> > > On Thu, 30 Jun 2022 09:36:47 +0200
> > > Brice Goglin wrote:
> > >
> > > > Allow -numa without
Whilst the interleave granularity is always small enough that this isn't
a real problem (much less than 4GiB) let's change the constant
to ULL to fix the coverity warning.
Reported-by: Peter Maydell
Fixes: 829de299d1 ("hw/cxl/component: Add utils for interleave parameter
encoding/decoding")
This got left behind in the move of the CXL setup code from core
files to the machines that support it.
Link:
https://gitlab.com/qemu-project/qemu/-/commit/1ebf9001fb2701e3c00b401334c8f3900a46adaa
Signed-off-by: Jonathan Cameron
---
include/hw/boards.h | 1 -
1 file changed, 1 deletion(-)
Previously broken_reserved_end was taken into account, but Igor Mammedov
identified that this could lead to a clash between potential RAM being
mapped in the region and CXL usage. Hence always add the size of the
device_memory memory region. This only affects the case where the
Three more or less less unrelated fixes for recently added CXL code.
Jonathan Cameron (3):
hw/machine: Clear out left over CXL related pointer from move of state
handling to machines.
hw/i386/pc: Always place CXL Memory Regions after device_memory
hw/cxl: Fix size of constant in
On Mon, 27 Jun 2022 14:29:19 +0100
Peter Maydell wrote:
> On Mon, 16 May 2022 at 21:51, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > Both registers and the CFMWS entries in CDAT use simple encodings
> > for the number of interleave ways and the interleave granularity.
> >
On Fri, 24 Jun 2022 17:12:25 +0100
Peter Maydell wrote:
> On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
> wrote:
> >
> > Add a single complex case for aarch64 virt machine.
> >
> > Signed-off-by: Jonathan Cameron
> > ---
> > tests/qtest/cxl-test.c | 48
On Fri, 24 Jun 2022 16:01:42 +0100
Peter Maydell wrote:
> On Fri, 24 Jun 2022 at 15:54, Jonathan Cameron
> wrote:
> > Just occurred to me there is another barrier to an approach that adds
> > DT bindings.
> > I fairly sure hw/pci-bridge/pci_expander_bridge.c (PXB)
> > only works on ACPI
On Thu, 23 Jun 2022 16:56:58 +0200
Brice Goglin wrote:
> Brice Goglin (4):
>hmat acpi: Don't require initiator value in -numa
>tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
>tests: acpi: q35: add test for hmat nodes without initiators
>tests: acpi: q35: update
On Fri, 24 Jun 2022 15:08:44 +0100
Jonathan Cameron wrote:
> On Fri, 24 Jun 2022 13:56:32 +0100
> Peter Maydell wrote:
>
> > On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
> > wrote:
> > >
> > > On Fri, 24 Jun 2022 11:48:47 +0100
> > > Peter Maydell wrote:
> > > >
> > > > This seems to
On Fri, 24 Jun 2022 13:56:32 +0100
Peter Maydell wrote:
> On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
> wrote:
> >
> > On Fri, 24 Jun 2022 11:48:47 +0100
> > Peter Maydell wrote:
> > >
> > > This seems to be missing code to advertise the new devices in the
> > > device tree.
> >
> >
On Fri, 24 Jun 2022 11:48:47 +0100
Peter Maydell wrote:
> On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
> wrote:
> >
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extended memmap.
> > The CFMWs are
On Thu, 16 Jun 2022 15:19:48 +0100
Jonathan Cameron via wrote:
> Previously patches 40 and 41 of
> [PATCH v10 00/45] CXl 2.0 emulation Support
> https://lore.kernel.org/qemu-devel/20220429144110.25167-45-jonathan.came...@huawei.com/#r
>
> Now the base CXL support inclu
On Tue, 21 Jun 2022 12:49:09 +0200
Brice Goglin wrote:
> Le 20/06/2022 à 18:05, Igor Mammedov a écrit :
> > On Mon, 20 Jun 2022 17:24:18 +0200
> > Brice Goglin wrote:
> >
> >> Le 20/06/2022 à 15:27, Igor Mammedov a écrit Machine (2966MB total) +
> >> Package P#0
> NUMANode P#2
> > +/*
> > + * This is very inefficient, but good enough for now!
> > + * Also thed payload will always fit, so no need to handle the MORE flag
> > and
> > + * make this stateful.
> > + */
> > +static ret_code cmd_media_get_poison_list(struct cxl_cmd *cmd,
> > +
On Mon, 20 Jun 2022 17:20:56 +0100
Jonathan Cameron wrote:
> Inject poison using qom-set to first set the poison_start
> and poison_length followed by writing to poison_inject to
> add to the poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via
> the mailbox command
Inject poison using qom-set to first set the poison_start
and poison_length followed by writing to poison_inject to
add to the poison list.
For now, the poison is not returned CXL.mem reads, but only via
the mailbox command Get Poison List.
See CXL 2.0, sec 8.2.9.5.4.1 Get Poison list (Opcode
On Fri, 17 Jun 2022 14:31:51 +0200
David Hildenbrand wrote:
> Xiao Guangrong doesn't have enough time to actively review or contribute
> to our NVDIMM implementation. Let's dissolve the "NVDIMM" section, moving
> relevant ACPI parts to "ACPI/SMBIOS" and moving memory device stuff into a
> new
On Thu, 16 Jun 2022 16:45:00 +0200
Igor Mammedov wrote:
> On Mon, 16 May 2022 16:51:34 -0400
> "Michael S. Tsirkin" wrote:
>
> > From: Ben Widawsky
> >
> > CXL host bridges themselves may have MMIO. Since host bridges don't have
> > a BAR they are treated as special for MMIO. This patch
Switches were already introduced, but now we support them update
the documentation to provide an example in diagram and
qemu command line parameter forms.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 88 -
1 file changed, 86
Previously sent as patches 43-45 of
[PATCH v10 00/45] CXl 2.0 emulation Support
https://lore.kernel.org/qemu-devel/20220429144110.25167-45-jonathan.came...@huawei.com/#r
Now the initial CXL support is upstream, patch sets applying to different
parts of the CXL infrastructure can be reviewed /
Emulation of a simple CXL Switch downstream port.
The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 43 +-
hw/pci-bridge/cxl_downstream.c | 249 +
hw/pci-bridge/meson.build | 2 +-
3
An initial simple upstream port emulation to allow the creation
of CXL switches. The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_upstream.c | 216 +++
hw/pci-bridge/meson.build| 2 +-
include/hw/cxl/cxl.h
Add a single complex case for aarch64 virt machine.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 48 +
tests/qtest/meson.build | 1 +
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/cxl-test.c
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
---
Previously patches 40 and 41 of
[PATCH v10 00/45] CXl 2.0 emulation Support
https://lore.kernel.org/qemu-devel/20220429144110.25167-45-jonathan.came...@huawei.com/#r
Now the base CXL support including for x86/pc is upstream (patches 1-39)
there are no dependencies between the next few CXL
This removes the last of the CXL code from the MachineState where it
is visible to all Machines to only those that support CXL (currently i386/pc)
As i386/pc always support CXL now, stop allocating the state independently.
Note the pxb register hookup code runs even if cxl=off in order to detect
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.
Note that for
Whilst here take the oportunity to shorten the function name.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
hw/cxl/cxl-host-stubs.c | 2 +-
hw/cxl/cxl-host.c | 8 +++-
hw/i386/pc.c | 5 +
include/hw/cxl/cxl.h | 2 --
include/hw/cxl/cxl_host.h
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
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