Re: [Qemu-devel] [PATCH v7 08/26] tcg/i386: Add vector operations

On Mon, 18 Dec 2017, Richard Henderson wrote: > The x86 vector instruction set is extremely irregular. With newer > editions, Intel has filled in some of the blanks. However, we don't > get many 64-bit operations until SSE4.2, introduced in 2009. > > The subsequent edition was for AVX1,

Re: [Qemu-devel] [PATCH v7 02/26] tcg: Add generic vector expanders

On Mon, 18 Dec 2017, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > Makefile.target |2 +- > accel/tcg/tcg-runtime.h | 29 ++ > tcg/tcg-gvec-desc.h | 49 ++ > tcg/tcg-op-gvec.h| 152 ++ >

Re: [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders

On Tue, 21 Nov 2017, Richard Henderson wrote: > diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c > new file mode 100644 > index 00..925c293f9c > --- /dev/null > +++ b/tcg/tcg-op-gvec.c <...> > +/* Set OPRSZ bytes at DOFS to replications of IN or IN_C. */ > +static void

Re: [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication

On Tue, 21 Nov 2017, Richard Henderson wrote: > Signed-off-by: Richard Henderson > +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) > +{ > +TCGTemp *rt = tcgv_vec_temp(r); > +TCGTemp *at = tcgv_vec_temp(a); > +TCGTemp *bt =

Re: [Qemu-devel] [PATCH RFC 2/3] tcg/optimize: do copy propagation for memory locations

On Wed, 22 Nov 2017, Richard Henderson wrote: > On 11/09/2017 03:41 PM, Kirill Batuzov wrote: > > +typedef struct TCGMemLocation { > > +/* Offset is relative to ENV. Only fields of CPUState are accounted. > > */ > > +tcg_target_ulong offset; >

[Qemu-devel] [PATCH RFC 3/3] tcg/optimize: handle vector loads and stores during copy propagation

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/optimize.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index da7f069444..1b6962c6c5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -318,6 +318,8 @@ static TCG

[Qemu-devel] [PATCH RFC 1/3] tcg: support MOV_VEC and MOVI_VEC opcodes in register allocator

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index a7854a59a1..6db7dd526a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3327,10 +3327,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlo

[Qemu-devel] [PATCH RFC 2/3] tcg/optimize: do copy propagation for memory locations

-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/optimize.c | 266 + 1 file changed, 266 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 847dfa44c9..da7f069444 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@

[Qemu-devel] [PATCH RFC 0/3] TCG: do copy propagation through memory locations

of TCGTemp or tcg_temp_info structures thus making TCGMemLocation reusable in liveness or register allocation. But we do not have SSA (yet?). Any thoughts or comments? Kirill Batuzov (3): tcg: support MOV_VEC and MOVI_VEC opcodes in register allocator tcg/optimize: do copy propagation for memory

Re: [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion

On Fri, 18 Aug 2017, Richard Henderson wrote: > On 08/18/2017 04:33 AM, Kirill Batuzov wrote: > > From my own experimentations some times ago, > > > > (1) translating vector instructions to vector instructions in TCG is faster > > than > > > > (2) tr

Re: [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion

On Thu, 17 Aug 2017, Alex Bennée wrote: > Hi, > > With upcoming work on SVE I've been looking at the way we implement > vector registers in QEMU's TCG. The current orthodoxy is to decompose > the vector into a series of TCG registers, often calling a helper > function the calculation of each

Re: [Qemu-devel] [PATCH v2.1 13/21] tcg/i386: support remaining vector addition operations

On Tue, 21 Feb 2017, Philippe Mathieu-Daudé wrote: > Hi Kirill, > > could you check my previous comment? > Hi Philippe, thank you for your comments. I've seen them and I'll apply changes you suggested in the next version of the series. I was just hoping to get a bit more feedback before I

Re: [Qemu-devel] [PATCH v2.1 00/20] Emulate guest vector operations with host vector operations

On Thu, 2 Feb 2017, Kirill Batuzov wrote: > The goal of these patch series is to set up an infrastructure to emulate > guest vector operations using host vector operations. Preliminary > experiments show that simply translating loads and stores increases > performance of x264 video

[Qemu-devel] [PATCH v2.1 14/21] tcg: do not rely on exact values of MO_BSWAP or MO_SIGN in backend

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/aarch64/tcg-target.inc.c | 4 ++-- tcg/arm/tcg-target.inc.c | 4 ++-- tcg/i386/tcg-target.inc.c| 4 ++-- tcg/mips/tcg-target.inc.c| 4 ++-- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c

[Qemu-devel] [PATCH v2.1 18/21] softmmu: create helpers for vector loads

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- cputlb.c | 4 + softmmu_template_vector.h | 266 ++ tcg/tcg.h | 5 + 3 files changed, 275 insertions(+) create mode 100644 softmmu_template_vector.h diff

[Qemu-devel] [PATCH v2.1 19/21] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.inc.c | 68 ++- 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1e6edc0..4647e97 100644 --- a/tc

[Qemu-devel] [PATCH v2.1 11/21] tcg/i386: add support for vector opcodes

need to support any other opcodes we want. INDEX_op_add_i32x4 is the only one for now. The PADDD instruction handles it perfectly. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 34 +- tcg/i386/tcg-target.inc.c

[Qemu-devel] [PATCH v2.1 21/21] tcg/README: update README to include information about vector opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/README | 47 ++- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/tcg/README b/tcg/README index a9858c2..209dbc4 100644 --- a/tcg/README +++ b/tcg/README @@ -53,9

[Qemu-devel] [PATCH v2.1 20/21] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg

-bit loads to 128-bit temporaries. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 90e14df..5bd0b1c 100644 --- a/target/arm/translate.c

[Qemu-devel] [PATCH v2.1 15/21] target/aarch64: do not check for non-existent TCGMemOp

MO_64|MO_SIGN is not a valid TCGMemOp. This code compiles only because by coincidence this value equals to MO_SSIGN mask defined in the same enum. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- Bugfix which is only indirectly related to this series. Other changes of the series e

[Qemu-devel] [PATCH v2.1 05/21] tcg: add simple alias analysis

, this variable should be spilled and reloaded at appropriate times. Previously no such analysis was performed and for correctness reasons it was required that no load/store operations overlap with memory locations of global variables. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- I b

[Qemu-devel] [PATCH v2.1 02/21] tcg: add support for 64bit vector type

Introduce TCG_TYPE_V64 and corresponding TCGv_v64 for TCG temps. Add helper functions that work with temps of this new type. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 23 +++ tcg/tcg.c| 13 + tcg/tcg.h

[Qemu-devel] [PATCH v2.1 00/20] Emulate guest vector operations with host vector operations

handle the host/guest different endianness (whether do we swap only bytes in elements or whole vectors?). Different targets seem to have different ideas on how this should be done. Kirill Batuzov (20): tcg: add support for 128bit vector type tcg: add support for 64bit vector type tcg: s

[Qemu-devel] [PATCH v2.1 08/21] tcg: add vector addition operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- Support for representing a v128 addition as two v64 additions have been added. As a result GEN_VECT_WRAPPER_HALVES macro was added. It is larger and more complicated than original GEN_VECT_WRAPPER (which is still used for v64 add

[Qemu-devel] [PATCH v2.1 07/21] tcg: allow globals to overlap

properly, some fixes are needed in the register allocator and liveness analysis. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/optimize.c | 19 - tcg/tcg.c | 128 + tcg/tcg.h | 20 + 3 files c

[Qemu-devel] [PATCH v2.1 12/21] tcg/i386: support 64-bit vector operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.inc.c | 22 ++ 2 files changed, 23 insertions(+) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b0704e8..755ebaa 100644 --- a/tcg/i386/tcg-ta

[Qemu-devel] [PATCH v2.1 10/21] target/arm: use vector opcode to handle vadd. instruction

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index d7578e2..90e14df 100644 --- a/target/arm/translate.c +++ b/targ

[Qemu-devel] [PATCH v2.1 13/21] tcg/i386: support remaining vector addition operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- I believe checkpatch warning here to be false-positive. --- tcg/i386/tcg-target.h | 10 + tcg/i386/tcg-target.inc.c | 54 +-- 2 files changed, 62 insertions(+), 2 deletions(-)

[Qemu-devel] [PATCH v2.1 09/21] target/arm: support access to vector guest registers as globals

To support vector guest registers as globals we need to do two things: 1) create corresponding globals, 2) mark which globals can overlap, Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- For vector registers I used the same coding style as was used for scalar registers. Should I

[Qemu-devel] [PATCH v2.1 06/21] tcg: use results of alias analysis in liveness analysis

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.c | 61 + 1 file changed, 61 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 18d97ec..27e5944 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -564,6 +564,11 @@

[Qemu-devel] [PATCH v2.1 01/21] tcg: add support for 128bit vector type

Introduce TCG_TYPE_V128 and corresponding TCGv_v128 for TCG temps. Add helper functions that work with temps of this new type. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 24 tcg/tcg.c| 13 + tcg/tcg.h

[Qemu-devel] [PATCH v2.1 16/21] tcg: introduce new TCGMemOp - MO_128

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.h | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 5e0c6da..63a83f9 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -306,11 +306,12 @@ typedef enum TCGMemOp { MO_16

[Qemu-devel] [PATCH v2.1 04/21] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 38 ++ tcg/tcg-opc.h | 18 ++ 2 files changed, 56 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 517745e..250493b 100644 --- a/tcg/tcg-op.h +++ b/tcg/tc

[Qemu-devel] [PATCH v2.1 17/21] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.inc.c | 5 + tcg/tcg-op.c | 24 tcg/tcg-op.h | 15 +++ tcg/tcg-opc.h | 4 4 files changed, 48 insertions(+) diff --git a/tcg/i3

[Qemu-devel] [PATCH v2.1 03/21] tcg: support representing vector type with smaller vector or scalar types

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- This is not as bad as I thought it would be. Only two cases: type == base_type and type != base_type. --- tcg/tcg.c | 136 +- 1 file changed, 91 insertions(+), 45 del

[Qemu-devel] [PATCH v2 14/20] tcg: do not rely on exact values of MO_BSWAP or MO_SIGN in backend

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/aarch64/tcg-target.inc.c | 4 ++-- tcg/arm/tcg-target.inc.c | 4 ++-- tcg/i386/tcg-target.inc.c| 4 ++-- tcg/mips/tcg-target.inc.c| 4 ++-- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c

[Qemu-devel] [PATCH v2 17/20] softmmu: create helpers for vector loads

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- cputlb.c | 4 + softmmu_template_vector.h | 266 ++ tcg/tcg.h | 5 + 3 files changed, 275 insertions(+) create mode 100644 softmmu_template_vector.h diff

[Qemu-devel] [PATCH v2 20/20] tcg/README: update README to include information about vector opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/README | 47 ++- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/tcg/README b/tcg/README index a9858c2..209dbc4 100644 --- a/tcg/README +++ b/tcg/README @@ -53,9

[Qemu-devel] [PATCH v2 13/20] tcg/i386: support remaining vector addition operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 10 + tcg/i386/tcg-target.inc.c | 54 +-- 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h

[Qemu-devel] [PATCH v2 01/20] tcg: add support for 128bit vector type

Introduce TCG_TYPE_V128 and corresponding TCGv_v128 for TCG temps. Add helper functions that work with temps of this new type. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 24 tcg/tcg.c| 13 + tcg/tcg.h

[Qemu-devel] [PATCH v2 11/20] tcg/i386: add support for vector opcodes

need to support any other opcodes we want. INDEX_op_add_i32x4 is the only one for now. The PADDD instruction handles it perfectly. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 34 +- tcg/i386/tcg-target.inc.c

[Qemu-devel] [PATCH v2 04/20] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 38 ++ tcg/tcg-opc.h | 18 ++ 2 files changed, 56 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 517745e..250493b 100644 --- a/tcg/tcg-op.h +++ b/tcg/tc

[Qemu-devel] [PATCH v2 19/20] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg

-bit loads to 128-bit temporaries. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 90e14df..76f9927 100644 --- a/target/arm/translate.c +++ b/

[Qemu-devel] [PATCH v2 08/20] tcg: add vector addition operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- Support for representing a v128 addition as two v64 additions have been added. As a result GEN_VECT_WRAPPER_HALVES macro was added. It is larger and more complicated than original GEN_VECT_WRAPPER (which is still used for v64 add

[Qemu-devel] [PATCH v2 05/20] tcg: add simple alias analysis

, this variable should be spilled and reloaded at appropriate times. Previously no such analysis was performed and for correctness reasons it was required that no load/store operations overlap with memory locations of global variables. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/opti

[Qemu-devel] [PATCH v2 18/20] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.inc.c | 68 ++- 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1e6edc0..4647e97 100644 --- a/tc

[Qemu-devel] [PATCH v2 12/20] tcg/i386: support 64-bit vector operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.inc.c | 22 ++ 2 files changed, 23 insertions(+) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b0704e8..755ebaa 100644 --- a/tcg/i386/tcg-ta

[Qemu-devel] [PATCH v2 15/20] tcg: introduce new TCGMemOp - MO_128

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.h | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 5e0c6da..63a83f9 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -306,11 +306,12 @@ typedef enum TCGMemOp { MO_16

[Qemu-devel] [PATCH v2 03/20] tcg: support representing vector type with smaller vector or scalar types

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- This is not as bad as I thought it would be. Only two cases: type == base_type and type != base_type. --- tcg/tcg.c | 136 +- 1 file changed, 91 insertions(+), 45 del

[Qemu-devel] [PATCH v2 00/20] Emulate guest vector operations with host vector operations

her do we swap only bytes in elements or whole vectors?). Different targets seem to have different ideas on how this should be done. Kirill Batuzov (20): tcg: add support for 128bit vector type tcg: add support for 64bit vector type tcg: support representing vector type with smaller vec

[Qemu-devel] [PATCH v2 16/20] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.inc.c | 5 + tcg/tcg-op.c | 24 tcg/tcg-op.h | 15 +++ tcg/tcg-opc.h | 4 4 files changed, 48 insertions(+) diff --git a/tcg/i3

[Qemu-devel] [PATCH v2 06/20] tcg: use results of alias analysis in liveness analysis

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.c | 61 + 1 file changed, 61 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 18d97ec..27e5944 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -564,6 +564,11 @@

[Qemu-devel] [PATCH v2 02/20] tcg: add support for 64bit vector type

Introduce TCG_TYPE_V64 and corresponding TCGv_v64 for TCG temps. Add helper functions that work with temps of this new type. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 23 +++ tcg/tcg.c| 13 + tcg/tcg.h

[Qemu-devel] [PATCH v2 07/20] tcg: allow globals to overlap

properly, some fixes are needed in the register allocator and liveness analysis. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/optimize.c | 19 - tcg/tcg.c | 128 + tcg/tcg.h | 20 + 3 files c

[Qemu-devel] [PATCH v2 09/20] target/arm: support access to vector guest registers as globals

To support vector guest registers as globals we need to do two things: 1) create corresponding globals, 2) mark which globals can overlap, Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 30 -- 1 file changed, 28 insertions

[Qemu-devel] [PATCH v2 10/20] target/arm: use vector opcode to handle vadd. instruction

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index d7578e2..90e14df 100644 --- a/target/arm/translate.c +++ b/targ

Re: [Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type

On Mon, 23 Jan 2017, Richard Henderson wrote: > On 01/23/2017 02:30 AM, Kirill Batuzov wrote: > > Because 4 adds on 4 i32 registers work good only when the size of > > vector elements matches the size of scalar variables we use for > > representation of a vector. add_i16x8 w

Re: [Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type

On Sat, 21 Jan 2017, Richard Henderson wrote: > On 01/19/2017 08:54 AM, Kirill Batuzov wrote: > > > > Wrappers issue emulation code instead of operation if it is not supported by > > host. > > > > tcg_gen_add_i32x4 looks like this: >

Re: [Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type

On 19.01.2017 18:09, Richard Henderson wrote: On 01/19/2017 05:04 AM, Kirill Batuzov wrote: On Wed, 18 Jan 2017, Richard Henderson wrote: On 01/17/2017 01:07 AM, Kirill Batuzov wrote: +static inline TCGv_v128 tcg_global_mem_new_v128(TCGv_ptr reg, intptr_t offset

Re: [Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type

On Wed, 18 Jan 2017, Richard Henderson wrote: > On 01/17/2017 01:07 AM, Kirill Batuzov wrote: > > +static inline TCGv_v128 tcg_global_mem_new_v128(TCGv_ptr reg, intptr_t > > offset, > > +const char *name) &g

Re: [Qemu-devel] [PATCH 10/18] tcg/i386: add support for vector opcodes

On Tue, 17 Jan 2017, Richard Henderson wrote: > On 01/17/2017 01:07 AM, Kirill Batuzov wrote: > > To be able to generate vector operations in a TCG backend we need to do > > several things. > > > > 1. We need to tell the register allocator about vector target's regi

[Qemu-devel] [PATCH 18/18] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg

-bit loads to 128-bit temporaries. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4378d44..8b28f77 100644 --- a/target/arm/translate.c +++ b/

[Qemu-devel] [PATCH 07/18] tcg: add vector addition operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 169 ++ tcg/tcg-opc.h | 12 + tcg/tcg.h | 29 ++ 3 files changed, 210 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index c469ea3..5

[Qemu-devel] [PATCH 12/18] tcg/i386: support remaining vector addition operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 10 ++ tcg/i386/tcg-target.inc.c | 37 + 2 files changed, 47 insertions(+) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 849b339..5deb08e

[Qemu-devel] [PATCH 09/18] target/arm: use vector opcode to handle vadd. instruction

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- target/arm/translate.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b81b5d..4378d44 100644 --- a/target/arm/translate.c +++ b/targ

[Qemu-devel] [PATCH 11/18] tcg/i386: support 64-bit vector operations

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.inc.c | 27 +++ 2 files changed, 28 insertions(+) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 974a58b..849b339 100644 --- a/tcg/i3

[Qemu-devel] [PATCH 04/18] tcg: add simple alias analysis

, this variable should be spilled and reloaded at appropriate times. Previously no such analysis was performed and for correctness reasons it was required that no load/store operations overlap with memory locations of global variables. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- chec

[Qemu-devel] [PATCH 03/18] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 38 ++ tcg/tcg-opc.h | 18 ++ 2 files changed, 56 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 173fb24..c469ea3 100644 --- a/tcg/tcg-op.h +++ b/tcg/tc

[Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type

Introduce TCG_TYPE_V128 and corresponding TCGv_v128 for TCG temps. Add hepler functions that work with temps of this new type. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 24 tcg/tcg.c| 13 + tcg/tcg.h

[Qemu-devel] [PATCH 17/18] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.inc.c | 63 +-- 1 file changed, 56 insertions(+), 7 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index c28fd09..a48da20 100644 --- a/tc

[Qemu-devel] [PATCH 14/18] tcg: introduce new TCGMemOp - MO_128

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.h | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index cb672f2..f205c6b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -295,11 +295,12 @@ typedef enum TCGMemOp { MO_16

[Qemu-devel] [PATCH 15/18] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.inc.c | 5 + tcg/tcg-op.c | 16 tcg/tcg-op.h | 8 tcg/tcg-opc.h | 4 4 files changed, 33 insertions(+) diff --git a/tcg/i386/tcg-target.i

[Qemu-devel] [PATCH 02/18] tcg: add support for 64bit vector type

Introduce TCG_TYPE_V64 and corresponding TCGv_v64 for TCG temps. Add hepler functions that work with temps of this new type. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg-op.h | 23 +++ tcg/tcg.c| 13 + tcg/tcg.h

[Qemu-devel] [PATCH 13/18] tcg: do not relay on exact values of MO_BSWAP or MO_SIGN in backend

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/aarch64/tcg-target.inc.c | 4 ++-- tcg/arm/tcg-target.inc.c | 4 ++-- tcg/i386/tcg-target.inc.c| 4 ++-- tcg/mips/tcg-target.inc.c| 4 ++-- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c

[Qemu-devel] [PATCH 06/18] tcg: allow globals to overlap

properly, some fixes are needed in the register allocator and liveness analysis. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.c | 49 + tcg/tcg.h | 18 ++ 2 files changed, 67 insertions(+) diff --git a/tcg/t

[Qemu-devel] [PATCH 16/18] softmmu: create helpers for vector loads

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- cputlb.c | 4 + softmmu_template_vector.h | 266 ++ tcg/tcg.h | 5 + 3 files changed, 275 insertions(+) create mode 100644 softmmu_template_vector.h diff

[Qemu-devel] [PATCH 10/18] tcg/i386: add support for vector opcodes

need to support any other opcodes we want. INDEX_op_add_i32x4 is the only one for now. The PADDD instruction handles it perfectly. Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/i386/tcg-target.h | 24 +- tcg/i386/tcg-target.inc.c

[Qemu-devel] [PATCH 05/18] tcg: use results of alias analysis in liveness analysis

Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- tcg/tcg.c | 71 +++ 1 file changed, 71 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index e81d1c4..2f97c13 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1448,6 +1448,58 @@

[Qemu-devel] [PATCH 08/18] target/arm: support access to vector guest registers as globals

To support vector guest registers as globals we need to do two things: 1) create corresponding globals, 2) mark which globals can overlap, Signed-off-by: Kirill Batuzov <batuz...@ispras.ru> --- I've declared regnames for new globals the same way they used to be declared for scala

[Qemu-devel] [PATCH 00/18] Emulate guest vector operations with host vector operations

in the backend (x86_64 was used in these series). For experiments I have used ARM guest on x86_64 host. I wanted some pair of different architectures with vector extensions both. ARM and x86_64 pair fits well. Kirill Batuzov (18): tcg: add support for 128bit vector type tcg: add support for 64bit

Re: [Qemu-devel] Commit 812c1057f, Handle G_IO_HUP in tcp_chr_read for tcp chardev, broke CloudStack

On Fri, 17 Jul 2015, Nils Carlson wrote: Hi, The commit 812c1057f, Handle G_IO_HUP in tcp_chr_read for tcp chardev, broke CloudStack. CloudStack was relying on fire-and-forget style messaging across a unix socket to the VM. Because the host fires the message and then closes the socket a

[Qemu-devel] [PATCH v2] target-arm: check that LSB = MSB in BFI instruction

. To reproduce issue run the following program int main(void) { asm volatile (.long 0x07c00c12 :: ); return 0; } compiled with gcc -marm -static badop_arm.c -o badop_arm Signed-off-by: Kirill Batuzov batuz...@ispras.ru --- target-arm/translate.c |4 1 file changed, 4 insertions

[Qemu-devel] [PATCH] target-arm: check that LSB = MSB in BFI instruction

. To reproduce issue run the following program int main(void) { asm volatile (.long 0x07c00c12 :: ); return 0; } compiled with gcc -marm -static badop_arm.c -o badop_arm Signed-off-by: Kirill Batuzov batuz...@ispras.ru --- target-arm/translate.c |2 ++ 1 file changed, 2 insertions(+) diff

Re: [Qemu-devel] Update on TCG Multithreading

On Mon, 1 Dec 2014, Mark Burton wrote: One issue I’d like to see more opinions on is the question of a cache per core, or a shared cache. I have heard anecdotal evidence that a shared cache gives a major performance benefit…. Does anybody have anything more concrete? There is a

Re: [Qemu-devel] [PATCH] hw/arm/realview.c: Fix memory leak in realview_init()

On Wed, 19 Nov 2014, Peter Maydell wrote: Not for 2.2, Fair enough. and I'm still not really convinced in general that it's worthwhile at all. I'm surprised that this small patch caused so much controversy. It seems very simple and straightforward to me. This patch fixes a memory leak.

Re: [Qemu-devel] [PATCH] hw/arm/realview.c: Fix memory leak in realview_init()

On 20 November 2014 11:53, Kirill Batuzov batuz...@ispras.ru wrote: I'm surprised that this small patch caused so much controversy. It seems very simple and straightforward to me. This patch fixes a memory leak. The fact that it indeed was a memory leak is indicated by Valgrind output

Re: [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

On Thu, 16 Oct 2014, Kirill Batuzov wrote: (4) Consider supporting generic vector operations in the TCG? I gave it a go and was quite happy with the result. I have implemented the add_i32x4 opcode which is addition of 128-bit vectors composed of four 32-bit integers and used

Re: [Qemu-devel] [PATCH] hw/arm/realview.c: Fix memory leak in realview_init()

On Fri, 31 Oct 2014, Peter Maydell wrote: On 31 October 2014 10:42, Nikita Belov zod...@ispras.ru wrote: On 2014-10-29 19:03, Peter Maydell wrote: We leak all of the MemoryRegions we allocate here, because we don't have a persistent state struct to keep them in. This doesn't really

Re: [Qemu-devel] [PATCH] MAINTAINERS: Add more TCG files

On Wed, 22 Oct 2014, Paolo Bonzini wrote: Unfortunately, TCG files do not really have a maintainer yet. But at least there will be fewer unmaintained files. Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- MAINTAINERS | 16 1 file changed, 16 insertions(+) diff

Re: [Qemu-devel] [PATCH] get_maintainer.pl: Default to --no-git-fallback

On Tue, 21 Oct 2014, Markus Armbruster wrote: Michael S. Tsirkin m...@redhat.com writes: On Mon, Oct 20, 2014 at 03:04:44PM +0100, Peter Maydell wrote: On 20 October 2014 10:19, Markus Armbruster arm...@redhat.com wrote: Contributors rely on this script to find maintainers to copy. The

Re: [Qemu-devel] [PATCH] get_maintainer.pl: Default to --no-git-fallback

On Tue, 21 Oct 2014, Markus Armbruster wrote: Paolo Bonzini pbonz...@redhat.com writes: On 10/20/2014 04:15 PM, Michael S. Tsirkin wrote: What do you want to happen in this case? Won't this cause even more patches to fall to the floor? The benefit seems marginal, the risk high. I

[Qemu-devel] [PATCH RFC 6/7] target-arm: use add_i32x4 opcode to handle vadd.i32 instruction

Signed-off-by: Kirill Batuzov batuz...@ispras.ru --- target-arm/translate.c | 12 1 file changed, 12 insertions(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 22855d8..00ea5cf 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5239,6

[Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

. Still there are some cons I mentioned earlier. The need to support a lot of opcodes is the most significant in the long run I think. So before I commit my time to conversion of more operations I'd like to hear your opinions if this approach is acceptable and worth spending efforts. Kirill Batuzov (7

[Qemu-devel] [PATCH RFC 7/7] tcg/i386: add support for vector opcodes

to support any other opcodes we want. INDEX_op_add_i32x4 is the only one for now. PADDD instruction handles it perfectly. Signed-off-by: Kirill Batuzov batuz...@ispras.ru --- tcg/i386/tcg-target.c | 103 ++--- tcg/i386/tcg-target.h | 24

[Qemu-devel] [PATCH RFC 4/7] tcg: add add_i32x4 opcode

in a serious performance degradation. Signed-off-by: Kirill Batuzov batuz...@ispras.ru --- tcg/tcg-op.h | 108 + tcg/tcg-opc.h | 12 +++ tcg/tcg.h |5 +++ 3 files changed, 125 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h

Re: [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

On Thu, 16 Oct 2014, Alex Bennée wrote: From Valgrind experience there are enough genericism. Valgrind can translate SSE, AltiVec and NEON instructions to vector opcodes. Most of the opcodes are reused between instruction sets. Doesn't Valgrind have the advantage of

Re: [Qemu-devel] [PATCH v3] qemu-char: Do not disconnect when there's data for reading

of connection as suggested by Kirill. Cc: Kirill Batuzov batuz...@ispras.ru Cc: Nikolay Nikolaev n.nikol...@virtualopensystems.com Cc: Markus Armbruster arm...@redhat.com Cc: Anthony Liguori aligu...@amazon.com Signed-off-by: Zifei Tong zifeit...@gmail.com --- Changes in v3: handle EWOULDBLOCK, remove

Re: [Qemu-devel] [PATCH] qemu-char: Do not disconnect when there's data for reading

a related bug when running socat in write-only mode, with $ echo quit | socat -u - UNIX-CONNECT:qemu-monitor the monitor won't not run the 'quit' command. CC: Kirill Batuzov batuz...@ispras.ru CC: Nikolay Nikolaev n.nikol...@virtualopensystems.com CC: Anthony Liguori aligu...@amazon.com

Re: [Qemu-devel] Serial: possible hang during intensive interaction over the console

On Fri, 5 Sep 2014, Andrey Korolyov wrote: Heh, it is kernel- (defaults-) dependent after all. Debian hangs always, on 3.10, 3.14 and 3.16, Fedora 20 works fine on 3.15. I`ll check if there are any 82550-specific patches in Fedora tree a bit later. It is a setting-dependent issue,

Re: [Qemu-devel] Serial: possible hang during intensive interaction over the console

On Wed, 3 Sep 2014, Andrey Korolyov wrote: Given 2.1 and isa-serial output, set as ttyS0 for the guest VM with 9600 baud rate. The test case is quite simple - display as much data as possible over serial console and do not hang the system. While qemu-1.1 works perfectly, with complaining

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