for other people :)
Signed-off-by: Kito Cheng
---
accel/tcg/cpu-exec.c | 3 +++
include/hw/core/cpu.h | 2 ++
include/qemu/log.h| 1 +
util/log.c| 2 ++
4 files changed, 8 insertions(+)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index a565a3f8ec..2cbec0a6ed 100644
Implement -d cpu,vu to dump content of vector register.
Signed-off-by: Kito Cheng
---
target/riscv/cpu.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c1b96da7da..97b289d277 100644
--- a/target/riscv/cpu.c
h set elen to 0 as auto detect, and keep the capability to
let user could configure that.
Signed-off-by: Kito Cheng
---
target/riscv/cpu.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 487d0faa63..c1b96da
-implementation-defined-constant-parameters
[2]
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
Signed-off-by: Kito Cheng
---
target/riscv/cpu.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv
Set I, M, A, F, D and C bit for hwcap if misa is set.
V3 Changes:
- Simplify logic of getting hwcap.
V2 Changes:
- Only set imafdc bits, sync with upstream linux kernel.
Signed-off-by: Kito Cheng
---
linux-user/elfload.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/linux
Set I, M, A, F, D and C bit for hwcap if misa is set.
V2 Changes:
- Only set imafdc bits, sync with upstream linux kernel.
Signed-off-by: Kito Cheng
---
linux-user/elfload.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/linux-user/elfload.c
RISC-V define the hwcap as same as content of misa, but it only take lower
26-bits.
Signed-off-by: Kito Cheng
---
linux-user/elfload.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 17ab06f612..41b9ef72ea 100644
--- a/linux
Some target are using llseek instead of _llseek like riscv,
nios2, hexagon, and openrisc.
Signed-off-by: Kito Cheng
---
linux-user/strace.c| 3 ++-
linux-user/strace.list | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index
Add Frank, he is the SiFive's qemu maintainer.
On Thu, Apr 15, 2021 at 11:57 AM Alistair Francis wrote:
>
> + LIU Zhiwei and Kito Cheng
>
> Alistair
>
> On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote:
> >
> > Public bug reported:
Hi Alistair, Frank:
Should we add the bext_spec option like Vector-ext? I would suggest
adding one to align the behavior between V and B.
But I have no strong opinion for this.
>DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
Hi Keith:
Thanks for your reply, but it seems like we need some more modification in
linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in mail
rather than attachment :)
Patch here:
>From 2f1eb5825a6dda177d3289106970eab05cb08445 Mon Sep 17 00:00:00 2001
From: Kito Ch
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
> +} else {
> +generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
> +}
> exit_tb(ctx); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> return true;
> diff --git a/target/riscv/tra
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f4574..bc29e118c6d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> if (cpu->cfg.ext_h) {
> target_misa |=
Hi Zhiwei:
vsetvl and vsetvli seems like missing ISA checking before translate,
this cause those 2 instructions can be executed even RVV not enable.
My testing env is qemu riscv64-linux-user mode.
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
> b/target/riscv/insn_trans/trans_rvv.inc.c
From: Kito Cheng
base register is no rs1 not rs2 for fsw.
Signed-off-by: Kito Cheng
---
target/riscv/insn_trans/trans_rvc.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c
b/target/riscv/insn_trans/trans_rvc.inc.c
index 5819f53
hardfloat fused multiply-add might fallback to softfloat mode in some
situation, but it might already changed the value of input operands,
so we must restore those value before fallback.
This bug is catched by running gcc testsuite on RISC-V qemu.
Signed-off-by: Kito Cheng
---
fpu/softfloat.c
Verified with gcc testsuite on rv64gc, no new regression introduced, and
get less fails.
Palmer Dabbelt 於 2019年3月21日 週四，22:59寫道：
> While running the GCC test suite against 4.0.0-rc0, Kito found a
> regression introduced by the decodetree conversion that caused divuw and
> remuw to sign-extend
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