[PATCH v5 60/60] target/riscv: configure and turn on vector extension from command line

ault value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. These properties can be specified with other values. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 44 +++- target/riscv/cpu.h | 2 ++ 2 files changed, 45

[PATCH v5 57/60] target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 17 +++ target/riscv/vector_helper.c| 136 4 files changed, 177 insertions(+) diff

[PATCH v5 58/60] target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 23 + target/riscv/vector_helper.c| 68 + 4 files changed, 103 insertions

[PATCH v5 56/60] target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 47 + target/riscv/vector_helper.c| 36 +++ 4 files changed, 94

[PATCH v5 55/60] target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 26 + target/riscv/vector_helper.c| 15 ++ 4 files changed, 47 insertions

[PATCH v5 54/60] target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 33 + target/riscv/vector_helper.c| 20 +++ 4 files changed, 59 insertions

[PATCH v5 53/60] target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 21 target/riscv/vector_helper.c| 26 + 4 files changed, 54

[PATCH v5 52/60] target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 22 ++ target/riscv/vector_helper.c| 31 + 4 files changed, 59 insertions

[PATCH v5 51/60] target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 23 + target/riscv/vector_helper.c| 66 + 4 files changed, 96 insertions(+) diff

[PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4 files changed, 54 insertions

[PATCH v5 49/60] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4 files changed, 55 insertions

[PATCH v5 48/60] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 28 + target/riscv/vector_helper.c| 40 + 4 files changed, 85

[PATCH v5 47/60] target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 50 + 4 files changed, 58 insertions(+) diff --git

[PATCH v5 46/60] target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 5 target/riscv/vector_helper.c| 39 + 4 files changed, 58 insertions(+) diff

[PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11 +++ 4 files changed, 24 insertions(+) diff --git a/target

[PATCH v5 44/60] target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 17 ++ target/riscv/vector_helper.c| 76 + 4 files changed, 134 insertions

[PATCH v5 43/60] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 42 + target/riscv/vector_helper.c| 42 + 4 files changed

[PATCH v5 42/60] target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 42 +++ target/riscv/vector_helper.c| 45 + 4 files changed, 103

[PATCH v5 41/60] target/riscv: vector floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33 + 4 files changed, 56 insertions

[PATCH v5 39/60] target/riscv: vector floating-point classify instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 62 + 4 files changed, 70 insertions(+) diff --git

[PATCH v5 40/60] target/riscv: vector floating-point merge instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 12 +++ target/riscv/vector_helper.c| 28 + 4 files changed, 45 insertions

[PATCH v5 38/60] target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 37 target/riscv/insn32.decode | 12 ++ target/riscv/insn_trans/trans_rvv.inc.c | 33 target/riscv/vector_helper.c| 221 4 files changed, 303 insertions(+) diff

[PATCH v5 37/60] target/riscv: vector floating-point sign-injection instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 +++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 +++ target/riscv/vector_helper.c| 76 + 4 files changed, 109 insertions(+) diff

[PATCH v5 36/60] target/riscv: vector floating-point min/max instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 6 ++ target/riscv/vector_helper.c| 27 + 4 files changed, 50 insertions

[PATCH v5 35/60] target/riscv: vector floating-point square-root instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 37 +++ target/riscv/vector_helper.c| 40 + 4 files changed, 84

[PATCH v5 34/60] target/riscv: vector widening floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 + target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 84 + 4 files changed, 119 insertions(+) diff

[PATCH v5 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 228 4 files changed, 311 insertions(+) diff

[PATCH v5 32/60] target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22 ++ 4 files changed, 33 insertions(+) diff --git

[PATCH v5 31/60] target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 16 + target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 48 + 4 files changed, 76 insertions

[PATCH v5 30/60] target/riscv: vector widening floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 131 target/riscv/vector_helper.c| 77 ++ 4 files changed, 233 insertions

[PATCH v5 27/60] target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 109 4 files changed, 140 insertions(+) diff

[PATCH v5 28/60] target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 128 4 files changed, 155 insertions(+) diff

[PATCH v5 29/60] target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 107 target/riscv/vector_helper.c| 89 4 files changed, 217

[PATCH v5 26/60] target/riscv: vector widening saturating scaled multiply-add

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c| 180 4 files changed, 218 insertions(+) diff

[PATCH v5 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c| 103 4 files changed, 118 insertions(+) diff

[PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ target/riscv/vector_helper.c| 129 4 files changed, 158 insertions(+) diff

[PATCH v5 23/60] target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 ++ target/riscv/vector_helper.c| 278 4 files changed, 337 insertions(+) diff

[PATCH v5 22/60] target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 24 ++ target/riscv/vector_helper.c| 58 + 4 files changed, 94 insertions

[PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c| 45 + 4 files changed, 83 insertions

[PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88 + 4 files changed, 139 insertions

[PATCH v5 19/60] target/riscv: vector widening integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51 + 4 files changed, 84 insertions

[PATCH v5 18/60] target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74 + 4 files changed, 125 insertions

[PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 147 4 files changed, 198 insertions(+) diff

[PATCH v5 16/60] target/riscv: vector integer min/max instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 71 + 4 files changed, 122 insertions

[PATCH v5 15/60] target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 66 target/riscv/vector_helper.c| 130 4 files changed, 273

[PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 91 + target/riscv/vector_helper.c| 14 4 files changed, 124 insertions(+) diff

[PATCH v5 13/60] target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 44 + target/riscv/vector_helper.c| 82 + 4 files changed, 160

[PATCH v5 12/60] target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c| 51 + 4 files changed, 96 insertions

[PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 108 ++ target/riscv/vector_helper.c| 140 4 files changed, 291

[PATCH v5 10/60] target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 target/riscv/insn32.decode | 16 +++ target/riscv/insn_trans/trans_rvv.inc.c | 154 target/riscv/vector_helper.c| 112 + 4 files changed, 331

[PATCH v5 09/60] target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 21 +++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 220 target/riscv/vector_helper.c| 122 + 4 files changed, 373 insertions

[PATCH v5 08/60] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h

[PATCH v5 07/60] target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h

[PATCH v5 06/60] target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 35 +++ target/riscv/insn32.decode

[PATCH v5 05/60] target/riscv: add vector stride load and store instructions

the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 6 + target/riscv/helper.h | 105 ++ target/riscv/insn32.decode | 32 ++ target/riscv/insn_trans

[PATCH v5 04/60] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makef

[PATCH v5 03/60] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v5 02/60] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v5 01/60] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v5 00/60] target/riscv: support vector extension v0.7.1

for no-fault operations in linux user mode. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (60): target/riscv: add vector

[PATCH v4 34/60] target/riscv: vector widening floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 + target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 84 + 4 files changed, 119 insertions(+) diff

[PATCH v4 30/60] target/riscv: vector widening floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 131 target/riscv/vector_helper.c| 77 ++ 4 files changed, 233 insertions

[PATCH v4 31/60] target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 16 + target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 48 + 4 files changed, 76 insertions

[PATCH v4 28/60] target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 128 4 files changed, 155 insertions(+) diff

[PATCH v4 23/60] target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 ++ target/riscv/vector_helper.c| 278 4 files changed, 337 insertions(+) diff

[PATCH v4 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c| 103 4 files changed, 118 insertions(+) diff

[PATCH v4 24/60] target/riscv: vector single-width averaging add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ target/riscv/vector_helper.c| 129 4 files changed, 158 insertions(+) diff

[PATCH v4 29/60] target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 107 target/riscv/vector_helper.c| 89 4 files changed, 217

[PATCH v4 21/60] target/riscv: vector widening integer multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c| 45 + 4 files changed, 83 insertions

[PATCH v4 26/60] target/riscv: vector widening saturating scaled multiply-add

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c| 180 4 files changed, 218 insertions(+) diff

[PATCH v4 20/60] target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88 + 4 files changed, 139 insertions

[PATCH v4 18/60] target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74 + 4 files changed, 125 insertions

[PATCH v4 27/60] target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 109 4 files changed, 140 insertions(+) diff

[PATCH v4 35/60] target/riscv: vector floating-point square-root instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 37 +++ target/riscv/vector_helper.c| 40 + 4 files changed, 84

[PATCH v4 16/60] target/riscv: vector integer min/max instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 71 + 4 files changed, 122 insertions

[PATCH v4 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 108 ++ target/riscv/vector_helper.c| 140 4 files changed, 291

[PATCH v4 22/60] target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 24 ++ target/riscv/vector_helper.c| 58 + 4 files changed, 94 insertions

[PATCH v4 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 228 4 files changed, 311 insertions(+) diff

[PATCH v4 14/60] target/riscv: vector narrowing integer right shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 91 + target/riscv/vector_helper.c| 14 4 files changed, 124 insertions(+) diff

[PATCH v4 17/60] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 147 4 files changed, 198 insertions(+) diff

[PATCH v4 19/60] target/riscv: vector widening integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51 + 4 files changed, 84 insertions

[PATCH v4 13/60] target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 44 + target/riscv/vector_helper.c| 82 + 4 files changed, 160

[PATCH v4 15/60] target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 66 target/riscv/vector_helper.c| 130 4 files changed, 273

[PATCH v4 32/60] target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22 ++ 4 files changed, 33 insertions(+) diff --git

[PATCH v4 12/60] target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c| 51 + 4 files changed, 96 insertions

[PATCH v4 10/60] target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 target/riscv/insn32.decode | 16 +++ target/riscv/insn_trans/trans_rvv.inc.c | 154 target/riscv/vector_helper.c| 112 + 4 files changed, 331

[PATCH v4 08/60] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h

[PATCH v4 02/60] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v4 06/60] target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 35 +++ target/riscv/insn32.decode

[PATCH v4 01/60] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v4 05/60] target/riscv: add vector stride load and store instructions

the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 6 + target/riscv/helper.h | 105 ++ target/riscv/insn32.decode | 32 ++ target/riscv/insn_trans

[PATCH v4 09/60] target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 21 +++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 220 target/riscv/vector_helper.c| 122 + 4 files changed, 373 insertions

[PATCH v4 04/60] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makef

[PATCH v4 03/60] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v4 00/60] target/riscv: support vector extension v0.7.1

user mode. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (60): target/riscv: add vector extension field in CPURISCVState

[PATCH v4 07/60] target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h

Questions about pollute the mail list archives

Hi, forks When I sent vector extension patchset v3(2020/03/09),  my mail system works some wrong, and only part of the patchset were sent.  When I try to send again, it either can't work. Even more, I found the mail list archives were polluted, many repetitions and scattered in many

[PATCH v3 32/60] target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22 ++ 4 files changed, 33 insertions(+) diff --git

[PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 228 4 files changed, 311 insertions(+) diff

[PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 108 ++ target/riscv/vector_helper.c| 140 4 files changed, 291

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