On Tue, Jul 27, 2021 at 12:14:48PM +0200, Ard Biesheuvel wrote:
> (+ Lorenzo)
>
> On Tue, 27 Jul 2021 at 12:07, Michael S. Tsirkin wrote:
> >
> > On Tue, Jul 27, 2021 at 11:50:23AM +0200, Ard Biesheuvel wrote:
> > > On Tue, 27 Jul 2021 at 11:30, Michael S. Tsirkin wrote:
> > > >
> > > > On Tue,
On Wed, May 27, 2020 at 11:02:40PM -0400, Jon Derrick wrote:
> VMD device 28C0 natively assists guest passthrough of the VMD endpoint
> through the use of shadow registers that provide Host Physical Addresses
> to correctly assign bridge windows. These shadow registers are only
> available if VMD
On Thu, Jun 11, 2020 at 09:16:48PM +, Derrick, Jonathan wrote:
[...]
> > > > Hi Jon,
> > > >
> > > > it looks like I can take this patch for v5.8 whereas patch 2 depends
> > > > on the QEMU changes acceptance and should probably wait.
> > > >
> > > > Please let me know your thoughts asap
On Fri, May 29, 2020 at 03:53:37PM +, Derrick, Jonathan wrote:
> On Fri, 2020-05-29 at 11:33 +0100, Lorenzo Pieralisi wrote:
> > On Wed, May 27, 2020 at 11:02:39PM -0400, Jon Derrick wrote:
> > > Versions of VMD with the Host Physical Address shadow register use t
On Wed, May 27, 2020 at 11:02:39PM -0400, Jon Derrick wrote:
> Versions of VMD with the Host Physical Address shadow register use this
> register to calculate the bus address offset needed to do guest
> passthrough of the domain. This register shadows the Host Physical
> Address registers
Hi Guenter,
On Fri, Jan 22, 2016 at 06:17:49PM -0800, Guenter Roeck wrote:
> On 01/13/2016 06:50 AM, Lorenzo Pieralisi wrote:
> >The Performance Monitors extension is an optional feature of the
> >AArch64 architecture, therefore, in order to access Performance
> >Moni
ation and
restore")
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
Reported-by: Guenter Roeck <li...@roeck-us.net>
Tested-by: Guenter Roeck <li...@roeck-us.net>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Ma
implements a guard by reading the ID_AA64DFR0_EL1 register
PMUVer field to detect the PMUv3 presence and prevent accessing PMUv3
system registers if the Performance Monitors extension is not
implemented in the core.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
Reported-by: Guenter Roe
field before
accessing them.
This patch implements a guard by reading the ID_AA64DFR0_EL1 register
PMUVer field to detect the PMUv3 presence and prevent accessing PMUv3
system registers if the Performance Monitors extension is not
implemented in the core.
Signed-off-by: Lorenzo Pieralisi <lor
On Thu, Jan 07, 2016 at 01:25:35PM +, Peter Maydell wrote:
> On 24 December 2015 at 00:52, Guenter Roeck wrote:
> > Hi all,
> >
> > since commit 60792ad349f3 ("arm64: kernel: enforce pmuserenr_el0
> > initialization
> > and restore"), my arm64 qemu tests of linux-next are
On Thu, Jan 07, 2016 at 03:58:15PM +, Peter Maydell wrote:
> On 7 January 2016 at 15:53, Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
> wrote:
> > On Thu, Jan 07, 2016 at 01:25:35PM +, Peter Maydell wrote:
> >> We had previously been relying on the kernel n
Hi Guenter,
On Wed, Dec 23, 2015 at 04:52:51PM -0800, Guenter Roeck wrote:
> Hi all,
>
> since commit 60792ad349f3 ("arm64: kernel: enforce pmuserenr_el0
> initialization
> and restore"), my arm64 qemu tests of linux-next are failing. After this
> commit,
> qemu does not display any output.
>
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