> Peter Maydell hat am 18. März 2017 um 23:22
> geschrieben:
>
> This is expected, because you're creating two devices.
> Device 1 is the one that's created by calling
> mydevice_init() here in the board code.
> Device 2 is created because you say "-device mydevice"
> on the command line.
I see
Hello development,
I ran into some behaviour I don't understand and which may be a qemu problem
but which may also be my fault, since I haven't investigated much on QOM so far.
I am currently writing a NIC sysbus device based on the structure of
hw/net/smc91c111.c
qemu is invoked as:
$ qemu-
> Peter Maydell hat am 27. Februar 2017 um 16:27
> geschrieben:
>
>
> On 27 February 2017 at 14:35, Marc Bommert wrote:
> >> Peter Maydell hat am 27. Februar 2017 um 15:07
> >> geschrieben:
> >> Suppose that only the interrupt programmed into VECT
> Peter Maydell hat am 27. Februar 2017 um 15:07
> geschrieben:
>
> The comment in pl190_read() about VECTADDR says
> "an enabled interrupt X at priority P causes prio_mask[Y]
> to have bit X set for all Y > P", but your patch would
> make that not be true.
Sorry, of course, the comment has to
The "current" priority bit (1 << i) should also be set in s->prio_mask[i], if
the interrupt is enabled. This will in turn cause the read operation of
VECTADDR to return the correct vector of the pending interrupt.
---
hw/intc/pl190.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
** Changed in: qemu
Status: New => Fix Committed
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https://bugs.launchpad.net/bugs/1668103
Title:
Possible off-by-one error in priority handling of hw/PL190.c
Status in QEMU:
>From 0cd0c1346f9adb7b90df3e4e30a5904eeda33bfa Mon Sep 17 00:00:00 2001
From: Marc Bommert
Date: Sun, 26 Feb 2017 22:08:49 +0100
Subject: [PATCH] Fix off-by-one error in priority handling when reading
VECTADDR: Also, if enabled, have the "current" priority bit (1<prio_mask[i]
** Changed in: qemu
Assignee: (unassigned) => Marc Bommert (brightwise)
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https://bugs.launchpad.net/bugs/1668103
Title:
Possible off-by-one error in priority handling of hw/PL
Public bug reported:
I have a problem when reading back VECTADDR in my proprietary OS's
interrupt handler.
Example client code:
1) Write INTENCLEAR to clear all interrupt enable bits
2) Set all 16 vector control registers to zero
3) Set vector address #2 to value 2
4) Set vector control #2 t
