[PATCH] target/mips: enable GINVx support for I6400 and I6500

GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu

[PATCH v2 4/4] target/mips: set correct CP0.Config[4, 5] values for M14K(c)

Signed-off-by: Marcin Nowakowski Suggested-by: Philippe Mathieu-Daudé --- target/mips/cpu-defs.c.inc | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fdde04dfb9..d45f245a67 100644 --- a/target/mips/cpu

[PATCH v2 2/4] target/mips: fix SWM32 handling for micromips

Signed-off-by: Marcin Nowakowski Reviewed-by: Philippe Mathieu-Daudé --- target/mips/tcg/ldst_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index d0bd0267b2..c1a8380e34 100644 --- a/target/mips/tcg/lds

[PATCH v2 3/4] target/mips: implement CP0.Config7.WII bit support

Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski

[PATCH v2 1/4] target/mips: fix JALS32/J32 instruction handling for microMIPS

bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski Reviewed-by: Richard Henderson --- t

[PATCH v2 0/4] target/mips: misc microMIPS fixes

v2: - add reviewed-by to patch 1 & 2 - add CP0.Config7.WII for P5600 - new patch: add CP0.Config[4,5] for M14K(c) Marcin Nowakowski (4): target/mips: fix JALS32/J32 instruction handling for microMIPS target/mips: fix SWM32 handling for micromips target/mips: implement CP0.Config7

Re: [PATCH 3/3] target/mips: implement CP0.Config7.WII bit support

On Wed, Feb 15, 2023 at 7:33 PM Philippe Mathieu-Daudé wrote: > > Hi Marcin, > > On 15/2/23 09:47, Marcin Nowakowski wrote: > > Some older cores use CP0.Config7.WII bit to indicate that a disabled > > interrupt should wake up a sleeping CPU. > > Enable this b

[PATCH 1/3] target/mips: fix JALS32/J32 instruction handling for microMIPS

bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski --- target/mips/tcg/translate.c | 6 ++

[PATCH 3/3] target/mips: implement CP0.Config7.WII bit support

Some older cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14Kc, which supports that. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski

[PATCH 2/3] target/mips: fix SWM32 handling for micromips

SWM32 should store a sequence of 32-bit words from the GPRs, but it was incorrectly coded to store 16-bit words only. As a result, an LWM32 that usually follows would restore invalid register values. Signed-off-by: Marcin Nowakowski --- target/mips/tcg/ldst_helper.c | 4 ++-- 1 file changed, 2

[PATCH 0/3] target/mips: misc microMIPS fixes

Marcin Nowakowski (3): target/mips: fix JALS32/J32 instruction handling for microMIPS target/mips: fix SWM32 handling for micromips target/mips: implement CP0.Config7.WII bit support target/mips/cpu-defs.c.inc| 1 + target/mips/cpu.c | 6 -- target/mips/cpu.h