s not harm so, anyway:
> Reviewed-by: Damien Hedde
>
> On 1/7/21 9:00 PM, Peter Maydell wrote:
> > Alistair/Edgar/Damien -- could I get a review from one of you
> > for this Xilinx clock-gen related patch, please?
> >
> > thanks
> > -- PMM
>
Pass an additional argument to zynq_slcr_compute_clocks that indicates whether
an reset-exit condition
applies. If called from zynq_slcr_reset_exit, external clocks are assumed to be
active, even if the
device state indicates a reset state.
Signed-off-by: Michael Peter
---
hw/misc/zynq_slcr.c
Hi Phil,
thanks for your advise and patience.
I created a new patch (this time with a sign-off) and sent it to qemu-
de...@nongnu.org.
Since I have to use a corporate email system, I hope that the formatting
is not gone.
Best regards,
Michael
--
You received this bug notification because
Public bug reported:
Hello,
we have come across a strange behavior in the Zynq7000 model of Qemu
that seems to have been introduced between 5.0.0 and 5.1.0.
The reset values of the SLCR register, in particular those for UART_CLK_CTRL,
are such that
the UARTs should find functional clocks. Up
