Hi Daniel,
On 5/10/2024 3:10 AM, Daniel P. Berrangé wrote:
On Fri, May 10, 2024 at 11:05:44AM +0300, Michael Tokarev wrote:
09.05.2024 17:11, Daniel P. Berrangé wrote:
On Thu, May 09, 2024 at 04:54:16PM +0300, Michael Tokarev wrote:
03.05.2024 20:46, Babu Moger wrote:
diff --git
Any feedback or concerns with this patch? Otherwise can this be merged?
Thanks
Babu
On 1/2/24 17:17, Babu Moger wrote:
> Observed the following failure while booting the SEV-SNP guest and the
> guest fails to boot with the smp parameters:
> "-smp 192,sockets=1,dies=12,cores=8,threads=2".
>
>
Sanity tested on AMD machine. Looks good.
Tested-by: Babu Moger
On 2/27/24 04:32, Zhao Liu wrote:
> From: Zhao Liu
>
> Hi list,
>
> This is the our v9 patch series, rebased on the master branch at the
> commit 03d496a992d9 ("Merge tag 'pull-qapi-2024-02-26' of
>
On 2/27/24 04:32, Zhao Liu wrote:
> From: Zhao Liu
>
> The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
> for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
> the number of sharing threads directly.
>
> From AMD's APM, NumSharingCache
On 2/27/24 04:32, Zhao Liu wrote:
> From: Zhao Liu
>
> CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
> processors sharing cache.
>
> The number of logical processors sharing this cache is
> NumSharingCache + 1.
>
> After cache models have topology information, we can
On 2/29/24 01:32, Zhao Liu wrote:
> Hi Babu,
>
>>> DEF("smp", HAS_ARG, QEMU_OPTION_smp,
>>> "-smp
>>> [[cpus=]n][,maxcpus=maxcpus][,drawers=drawers][,books=books][,sockets=sockets]\n"
>
> Here the "drawers" and "books" are listed...
>
>>> -"
>>>
Hi Zhao,
On 2/27/24 04:32, Zhao Liu wrote:
> From: Zhao Liu
>
> As module-level topology support is added to X86CPU, now we can enable
> the support for the modules parameter on PC machines. With this support,
> we can define a 5-level x86 CPU topology with "-smp":
>
> -smp
Hi Zhao,
Ran few basic tests on AMD systems. Changes look good.
Thanks
Babu
Tested-by: Babu Moger
On 1/8/24 02:27, Zhao Liu wrote:
> From: Zhao Liu
>
> Hi list,
>
> This is the our v7 patch series, rebased on the master branch at the
> commit d328fef93ae7 ("Merge tag 'pull-20231230' of
Hi Zhao,
On 12/14/2023 8:08 AM, Zhao Liu wrote:
On Fri, Nov 10, 2023 at 11:08:06AM -0600, Babu Moger wrote:
Date: Fri, 10 Nov 2023 11:08:06 -0600
From: Babu Moger
Subject: [PATCH] target/i386: Fix CPUID encoding of Fn801E_ECX
X-Mailer: git-send-email 2.34.1
Observed the following failure
Gentle reminder. Please let me know if there are any concerns or please
pull these patches for next update.
Thanks Babu
On 11/10/23 11:08, Babu Moger wrote:
Observed the following failure while booting the SEV-SNP guest and the
guest fails to boot with the smp parameters:
"-smp
On 9/14/2023 2:21 AM, Zhao Liu wrote:
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
On 9/14/2023 2:21 AM, Zhao Liu wrote:
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
From AMD's APM, NumSharingCache
Tested the series on AMD system. Created a VM and ran some basic commands.
Everything looks good.
Tested-by: Babu Moger
On 9/14/2023 2:21 AM, Zhao Liu wrote:
From: Zhao Liu
Hi list,
(CC k...@vger.kernel.org for better browsing.)
This is the our v4 patch series, rebased on the master
On 9/14/2023 2:21 AM, Zhao Liu wrote:
From: Zhao Liu
For function comments in this file, keep the comment style consistent
with other files in the directory.
Signed-off-by: Zhao Liu
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yanan Wang
Reviewed-by: Xiaoyao Li
Acked-by: Michael S.
Hi John,
On 9/5/2023 10:01 AM, John Allen wrote:
On Fri, Sep 01, 2023 at 11:30:53AM +0100, Joao Martins wrote:
On 26/07/2023 21:41, John Allen wrote:
Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required to
be exposed to guests to allow them to handle machine check
Hi Zhao,
On 8/18/23 02:37, Zhao Liu wrote:
> Hi Babu,
>
> On Mon, Aug 14, 2023 at 11:03:53AM -0500, Moger, Babu wrote:
>> Date: Mon, 14 Aug 2023 11:03:53 -0500
>> From: "Moger, Babu"
>> Subject: Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level
Hi Zhao,
On 8/14/23 03:22, Zhao Liu wrote:
> Hi Babu,
>
> On Fri, Aug 04, 2023 at 10:48:29AM -0500, Moger, Babu wrote:
>> Date: Fri, 4 Aug 2023 10:48:29 -0500
>> From: "Moger, Babu"
>> Subject: Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level
Hi Zhao,
On 8/4/23 04:56, Zhao Liu wrote:
> Hi Babu,
>
> On Thu, Aug 03, 2023 at 03:44:13PM -0500, Moger, Babu wrote:
>> Date: Thu, 3 Aug 2023 15:44:13 -0500
>> From: "Moger, Babu"
>> Subject: Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode
Hi Zhao,
On 8/4/23 04:48, Zhao Liu wrote:
> Hi Babu,
>
> On Thu, Aug 03, 2023 at 11:41:40AM -0500, Moger, Babu wrote:
>> Date: Thu, 3 Aug 2023 11:41:40 -0500
>> From: "Moger, Babu"
>> Subject: Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level
Hi Zhao,
Please copy the thread to k...@vger.kernel.org also. It makes it easier
to browse.
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> CPUID[0x801D].EAX[bits 25:14] is used to represent the cache
> topology for amd CPUs.
Please change this to.
CPUID[0x801D].EAX[bits
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
> for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
> the number of sharing threads directly.
>
> From AMD's APM, NumSharingCache
Hi Zhao,
On 8/2/23 18:49, Moger, Babu wrote:
> Hi Zhao,
>
> Hitting this error after this patch.
>
> ERROR:../target/i386/cpu.c:257:max_processor_ids_for_cache: code should
> not be reached
> Bail out! ERROR:../target/i386/cpu.c:257:max_processor_ids_for_cache: code
&g
Hi Zhao,
Hitting this error after this patch.
ERROR:../target/i386/cpu.c:257:max_processor_ids_for_cache: code should
not be reached
Bail out! ERROR:../target/i386/cpu.c:257:max_processor_ids_for_cache: code
should not be reached
Aborted (core dumped)
Looks like share_level for all the caches
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhuocheng Ding
>
> We introduce cluster-id other than module-id to be consistent with
s/We introduce/Introduce/
Thanks
Babu
> CpuInstanceProperties.cluster-id, and this avoids the confusion
> of parameter names when hotplugging.
>
>
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhuocheng Ding
>
> Support module level in i386 cpu topology structure "X86CPUTopoInfo".
>
> Since x86 does not yet support the "clusters" parameter in "-smp",
> X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the
> module
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> In cpu_x86_cpuid(), there are many variables in representing the cpu
> topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
>
> Since the names of cs->nr_cores/cs->nr_threads does not accurately
> represent its meaning, the use
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
> CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
> nearest power-of-2 integer.
>
> The nearest power-of-2 integer can be caculated by
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhuocheng Ding
>
> From CPUState.nr_cores' comment, it represents "number of cores within
> this CPU package".
>
> After 003f230e37d7 ("machine: Tweak the order of topology members in
> struct CpuTopology"), the meaning of smp.cores changed to
Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> In fact, this unit tests APIC ID other than CPUID.
This is not clear.
The tests in test-x86-topo.c actually test the APIC ID combinations.
Rename to test-x86-topo.c to make its name more in line with its actual
content.
> Rename to
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> Hi list,
>
> This is the our v3 patch series, rebased on the master branch at the
> commit 234320cd0573 ("Merge tag 'pull-target-arm-20230731' of https:
> //git.linaro.org/people/pmaydell/qemu-arm into staging").
>
> Comparing
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> For function comments in this file, keep the comment style consistent
> with other places.
s/with other places./with other files in the directory./
>
> Signed-off-by: Zhao Liu
> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by:
Hi John,
Thanks for the patches. Few comments below.
On 7/6/23 14:40, John Allen wrote:
> Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required to
> be exposed to guests to allow them to handle machine check exceptions on AMD
> hosts.
>
> Reported-by: William Roche
>
[AMD Official Use Only - General]
> -Original Message-
> From: Paolo Bonzini
> Sent: Friday, May 5, 2023 3:31 AM
> To: Moger, Babu
> Cc: pbonz...@redhat.com; richard.hender...@linaro.org;
> weijiang.y...@intel.com; phi...@linaro.org; d...@amazon.co.uk;
> p...
Hi Robert,
On 4/25/23 10:22, Moger, Babu wrote:
> Hi Robert,
>
> On 4/25/23 00:42, Robert Hoo wrote:
>> Babu Moger 于2023年4月25日周二 00:42写道：
>>>
>>> From: Michael Roth
>>>
>>> New EPYC CPUs versions require small changes to their cache_info's.
&
[AMD Official Use Only - General]
Hi Maksim,
> -Original Message-
> From: Maksim Davydov
> Sent: Wednesday, April 26, 2023 3:35 AM
> To: Moger, Babu
> Cc: weijiang.y...@intel.com; phi...@linaro.org; d...@amazon.co.uk;
> p...@xen.org; joao.m.mart...@oracle.com; qem
Hi Maksim,
On 4/25/23 07:51, Maksim Davydov wrote:
>
> On 4/24/23 19:33, Babu Moger wrote:
>> From: Michael Roth
>>
>> Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3.
>> The only difference vs. older models is an updated cache_info with
>> the 'complex_indexing' bit unset, since this
Hi Robert,
On 4/25/23 00:42, Robert Hoo wrote:
> Babu Moger 于2023年4月25日周二 00:42写道：
>>
>> From: Michael Roth
>>
>> New EPYC CPUs versions require small changes to their cache_info's.
>
> Do you mean, for the real HW of EPYC CPU, each given model, e.g. Rome,
> has HW version updates
On 5/25/22 02:05, Igor Mammedov wrote:
> On Tue, 24 May 2022 14:48:29 -0500
> "Moger, Babu" wrote:
>
>> On 5/24/22 10:19, Igor Mammedov wrote:
>>> On Tue, 24 May 2022 11:10:18 -0400
>>> Igor Mammedov wrote:
>>>
>>> CCing AM
On 5/24/22 18:23, Alejandro Jimenez wrote:
> On 5/24/2022 3:48 PM, Moger, Babu wrote:
>>
>> On 5/24/22 10:19, Igor Mammedov wrote:
>>> On Tue, 24 May 2022 11:10:18 -0400
>>> Igor Mammedov wrote:
>>>
>>> CCing AMD folks as that might be of int
On 5/24/22 10:19, Igor Mammedov wrote:
> On Tue, 24 May 2022 11:10:18 -0400
> Igor Mammedov wrote:
>
> CCing AMD folks as that might be of interest to them
I am trying to recreate the bug on my AMD system here.. Seeing this message..
qemu-system-x86_64: -numa node,nodeid=0,memdev=ram-node0:
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Igor Mammedov
> Sent: Wednesday, March 18, 2020 5:47 AM
> To: Moger, Babu
> Cc: Eduardo Habkost ; marcel.apfelb...@gmail.com;
> pbonz...@redhat.com; r...@twiddle.net; m...@redh
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Eduardo Habkost
> Sent: Tuesday, March 17, 2020 6:46 PM
> To: Moger, Babu
> Cc: marcel.apfelb...@gmail.com; pbonz...@redhat.com; r...@twiddle.net;
> m...@redhat.com; imamm...@redh
[AMD Official Use Only - Internal Distribution Only]
Ok. I am looking at it.
> -Original Message-
> From: Eduardo Habkost
> Sent: Tuesday, March 17, 2020 6:22 PM
> To: Moger, Babu
> Cc: marcel.apfelb...@gmail.com; pbonz...@redhat.com; r...@twiddle.net;
> m...
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Eduardo Habkost
> Sent: Tuesday, March 10, 2020 6:06 PM
> To: Moger, Babu
> Cc: marcel.apfelb...@gmail.com; pbonz...@redhat.com; r...@twiddle.net;
> m...@redhat.com; imamm...@redh
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Eduardo Habkost
> Sent: Wednesday, February 5, 2020 4:38 PM
> To: Ani Sinha
> Cc: Paolo Bonzini ; r...@twiddle.net; qemu-
> de...@nongnu.org; Singh, Brijesh ; Moger, Babu
>
> S
Adds the support for 2nd Gen AMD EPYC Processors. The model display
name will be EPYC-Rome.
Adds the following new feature bits on top of the feature bits from the
first generation EPYC models.
perfctr-core : core performance counter extensions support. Enables the VM to
use
Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
to use extended performance counter support. It enables six
programmable counters instead of 4 counters.
clzero : instruction zeroes out the 64 byte
The following series adds the support for 2nd generation AMD EPYC Processors
on qemu guests. The model display name for 2nd generation will be EPYC-Rome.
Also fixes few missed cpu feature bits in 1st generation EPYC models.
The Reference documents are available at
> -Original Message-
> From: Eduardo Habkost
> Sent: Tuesday, November 5, 2019 3:43 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; qemu-devel@nongnu.org
> Subject: Re: [PATCH 1/2] i386: Add mis
Adds the support for 2nd Gen AMD EPYC Processors. The model display
name will be EPYC-Rome.
Adds the following new feature bits on top of the feature bits from the
first generation EPYC models.
perfctr-core : core performance counter extensions support. Enables the VM to
use
Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
to use extended performance counter support. It enables six
programmable counters instead of 4 counters.
clzero : instruction zeroes out the 64 byte
The following series adds the support for 2nd generation AMD EPYC Processors
on qemu guests. The model display name for will be EPYC-Rome.
Also fixes few missed cpu feature bits in 1st generation EPYC models.
The Reference documents are available at
On 10/10/19 10:59 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:13:09PM +0000, Moger, Babu wrote:
>> Adds new epyc property in PCMachineState and also in MachineState.
>> This property will be used to initialize the mode specific handlers
>> to generate apic
On 10/10/19 10:59 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:13:09PM +0000, Moger, Babu wrote:
>> Adds new epyc property in PCMachineState and also in MachineState.
>> This property will be used to initialize the mode specific handlers
>> to generate apic
On 9/22/19 7:48 AM, Michael S. Tsirkin wrote:
> On Fri, Sep 06, 2019 at 07:12:18PM +0000, Moger, Babu wrote:
>> Introduce cpu core complex id(ccx_id) in x86CPU topology.
>> Each CCX can have upto 4 cores and share same L3 cache.
>> This information is required to build t
Eduardo and all,
Waiting for the feedback on this to move forward. Appreciate your time.
Thanks Babu
On 9/6/19 2:11 PM, Moger, Babu wrote:
> These series fixes the problems encoding APIC ID for AMD EPYC cpu models.
> https://bugzilla.redhat.com/show_bug.cgi?id=1728166
>
> This i
On 9/6/19 2:20 PM, Eric Blake wrote:
> On 9/6/19 2:12 PM, Moger, Babu wrote:
>> Introduce cpu core complex id(ccx_id) in x86CPU topology.
>> Each CCX can have upto 4 cores and share same L3 cache.
>> This information is required to build the topology in
>> new
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f25491a029..f8b1fc5c07 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4094,9 +4094,10 @@ void
Adds new epyc property in PCMachineState and also in MachineState.
This property will be used to initialize the mode specific handlers
to generate apic ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 23 +++
include/hw/boards.h |2 ++
include/hw/i386/pc.h |
Introduce following handlers for new epyc mode.
x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index.
x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id.
x86_apicid_from_topo_ids_epyci: Generate apicid from topo ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 +
1
Current topology id match will not work for epyc mode when setting
the node id. In epyc mode, ids like smt_id, thread_id, core_id,
ccx_id, socket_id can be same for more than one CPUs with across
two numa nodes.
For example, we can have two CPUs with following ids on two different node.
1.
hw/i386: Introduce topo_ids_from_apicid handler PCMachineState
Add function pointer topo_ids_from_apicid in PCMachineState.
Initialize with correct handler based on mode selected.
x86_apicid_from_cpu_idx will be the default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 13
Add function pointers in PCMachineState to handle apic id specific
functionalities. This will be used to initialize with correct
handlers based on mode selected.
x86_apicid_from_cpu_idx will be default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 -
Introduce initialize_topo_info to initialize X86CPUTopoInfo
data structure to build the topology. No functional change.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
Use the new epyc mode functions and delete the unused code.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 171 +++--
1 file changed, 48 insertions(+), 123 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Introduce cpu core complex id(ccx_id) in x86CPU topology.
Each CCX can have upto 4 cores and share same L3 cache.
This information is required to build the topology in
new apyc mode.
Signed-off-by: Babu Moger
---
hw/core/machine-hmp-cmds.c |3 +++
hw/core/machine.c | 13
Add function pointer apic_id_from_topo_ids in PCMachineState.
Initialize with correct handler based on the mode selected.
Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids
for consistency. x86_apicid_from_topo_ids will be the default handler.
Signed-off-by: Babu Moger
---
Some parameters are unnecessarily passed for offset/width
calculation. Remove those parameters from function prototypes.
No functional change.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 45 ++--
target/i386/cpu.c | 12
This is an effort to re-arrange few data structure for better
readability. Add X86CPUTopoInfo which will have all the topology
informations required to build the cpu topology. There is no
functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 40
These functions add support for building new epyc mode topology
given smp details like numa nodes, cores, threads and sockets.
Subsequent patches will use these functions to build the topology.
The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model
Store the smp Sockets in CpuTopology. Socket information
is required to build the cpu topology in new epyc mode.
Signed-off-by: Babu Moger
---
hw/core/machine.c |1 +
hw/i386/pc.c|1 +
include/hw/boards.h |2 ++
vl.c|1 +
4 files changed, 5
Rename few data structures related to X86 topology.
X86CPUTopoIDs will have individual arch ids. Next
patch introduces X86CPUTopoInfo which will have all
topology information(like cores, threads etc..).
Adds node_id and ccx_id. This will be required to support
new epyc mode mode. There is no
To support new epyc mode, we need to know the number of numa nodes
in advance to generate apic id correctly. So, split the numa
initialization into two. The function parse_numa initializes numa_info
and updates nb_numa_nodes. And then parse_numa_node does the numa node
initialization.
These series fixes the problems encoding APIC ID for AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
This is the second pass to give an idea of the changes required to address
the issue. First pass is availabe at
https://patchwork.kernel.org/cover/11069785/
Currently,
Hi Eduardo,
Thanks for the quick comments. I will look into your comments closely
and will let you know if I have questions.
> -Original Message-
> From: Eduardo Habkost
> Sent: Thursday, August 1, 2019 2:29 PM
> To: Moger, Babu
> Cc: marcel.apfelb...@gmail.com; m...@re
Add sockets in CpuTopology. This is required when building
the CPU topology.
Signed-off-by: Babu Moger
---
hw/core/machine.c | 1 +
hw/i386/pc.c| 1 +
include/hw/boards.h | 2 ++
vl.c| 1 +
4 files changed, 5 insertions(+)
diff --git a/hw/core/machine.c
Per Processor Programming Reference (PPR) for AMD Family 17h Models,
the pkg_id offset in apicid is 6. Fix the offset based on EPYC models.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c
Use the functions defined in topology.h and remove the old code.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 146 +-
1 file changed, 27 insertions(+), 119 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Currently, the apicid is a sequential number in x86 cpu models. This
works fine for most of the cases. But, in certain cases this will
result into cpu topology inconsistency. This problem was observed in
AMD EPYC cpu models.
To address that we need to build apicid as per the hardware
These series fixes the problems encoding APIC ID for AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
This is the first pass to give an idea of the changes required to address
the issue. Please feel free to comment.
Currently, apic id is decoded based on
Check the cpu_type before calling the apicid functions
from topology.h.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 81 +---
1 file changed, 70 insertions(+), 11 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ef39463fd5..dad55c940f
Looks good. Did some basic testing.
Reviewed-by: Babu Moger
> -Original Message-
> From: Richard W.M. Jones
> Sent: Friday, August 10, 2018 2:41 AM
> To: Eduardo Habkost
> Cc: qemu-devel@nongnu.org; Paolo Bonzini ;
> Richard Henderson ; Moger, Babu
>
> S
> -Original Message-
> From: Aleksandar Markovic [mailto:amarko...@wavecomp.com]
> Sent: Wednesday, July 18, 2018 8:35 AM
> To: Philippe Mathieu-Daudé ; Eduardo Habkost
> ; qemu-devel@nongnu.org
> Cc: Moger, Babu ; Paolo Bonzini
> ; Aurelien Jarno ; Richard
>
Looks good. thanks
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Monday, July 2, 2018 8:10 PM
> To: qemu-devel@nongnu.org
> Cc: Eduardo Habkost ; Paolo Bonzini
> ; Moger, Babu ; Michael
> S. Tsirkin ; Igor Mammedov
> Subje
m
> Cc: qemu-devel@nongnu.org; mtosa...@redhat.com; k...@vger.kernel.org;
> k...@tripleback.net; ge...@hostfission.com; Moger, Babu
>
> Subject: [PATCH v15 1/3] i386: Fix up the Node id for CPUID_8000_001E
>
> This is part of topoext support. To keep the compatibility, we n
> -Original Message-
> From: Moger, Babu
> Sent: Thursday, June 14, 2018 6:09 PM
> To: Moger, Babu ; Eduardo Habkost
>
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-devel@nongnu.org;
>
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org]
> On Behalf Of Moger, Babu
> Sent: Thursday, June 14, 2018 3:41 PM
> To: Eduardo Habkost
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r.
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org]
> On Behalf Of Moger, Babu
> Sent: Thursday, June 14, 2018 5:19 PM
> To: Eduardo Habkost
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r.
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Thursday, June 14, 2018 2:13 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Thursday, June 14, 2018 1:41 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Thursday, June 14, 2018 1:40 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Wednesday, June 13, 2018 9:22 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Wednesday, June 13, 2018 1:49 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Wednesday, June 13, 2018 1:18 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org]
> On Behalf Of Moger, Babu
> Sent: Wednesday, June 13, 2018 1:11 PM
> To: Eduardo Habkost
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r.
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Wednesday, June 13, 2018 12:18 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
..@twiddle.net; mtosa...@redhat.com; qemu-devel@nongnu.org;
> k...@vger.kernel.org; k...@tripleback.net; ge...@hostfission.com; Jiri
> Denemark
> Subject: Re: [PATCH v13 3/5] i386: Enable TOPOEXT feature on AMD EPYC
> CPU
>
>
>
> On 06/12/2018 02:05 PM, Eduardo Habkost wrote:
> &
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Tuesday, June 12, 2018 12:40 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-dev
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org]
> On Behalf Of Eduardo Habkost
> Sent: Monday, June 11, 2018 4:10 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r.
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org]
> On Behalf Of Eduardo Habkost
> Sent: Monday, June 11, 2018 4:05 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r.
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