On Thu, 28 Mar 2019 10:34:08 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 27, 2019 at 8:15 PM Palmer Dabbelt wrote:
On Wed, 27 Mar 2019 09:29:56 PDT (-0700), alistai...@gmail.com wrote:
> On Wed, Mar 27, 2019 at 3:29 AM Palmer Dabbelt wrote:
>>
>> On Wed, 20 Mar 20
On Wed, 27 Mar 2019 09:29:56 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 27, 2019 at 3:29 AM Palmer Dabbelt wrote:
On Wed, 20 Mar 2019 17:46:09 PDT (-0700), Alistair Francis wrote:
> The irq is incorrectly calculated to be off by one. It has worked in the
> past as the priorit
(-)
--
2.21.0
Thanks, I've got these on for-master. I'll let them sit for a bit to see if
there are any other comments, but
Reviewed-by: Palmer Dabbelt
On Wed, 27 Mar 2019 11:52:53 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 27, 2019 at 11:51 AM Alistair Francis
wrote:
Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
Signed-off-by: Alistair Francis
I dropped
On Wed, 20 Mar 2019 17:46:09 PDT (-0700), Alistair Francis wrote:
The irq is incorrectly calculated to be off by one. It has worked in the
past as the priority_base offset has also been set incorrectly. We are
about to fix the priority_base offset so first first the irq
calculation.
On Tue, 26 Mar 2019 15:19:25 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 20, 2019 at 5:45 PM Alistair Francis
wrote:
This series updates the PLIC address to match the documentation.
This fixes: https://github.com/riscv/opensbi/issues/97
Alistair Francis (5):
riscv: plic: Fix
On Tue, 26 Mar 2019 10:49:11 PDT (-0700), chout...@adacore.com wrote:
Hi Palmer,
On 26/03/2019 09:58, Palmer Dabbelt wrote:
Do you have anything that actually glues this to a machine so I can test it?
In this patch I do instantiate the device in sifive_e machine.
OK, that's what I thought
/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc1-v2
for you to fetch changes up to 620455350a8da7cc62ae82cb69dd5c556f744136:
target/riscv: Fix wrong expanding for c.fswsp (2019-03-26 03:17:30 -0700)
A second RISC-V Patch
From: Kito Cheng
base register is no rs1 not rs2 for fsw.
Signed-off-by: Kito Cheng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvc.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans
On Tue, 12 Feb 2019 09:38:39 PST (-0800), chout...@adacore.com wrote:
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin
The following changes since commit 62a172e6a77d9072bb1a18f295ce0fcf4b90a4f2:
Update version for v4.0.0-rc0 release (2019-03-19 17:17:22 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc1
for you to fetch changes up
!= 134))
abort ();
exit (0);
}
I haven't done any other testing on this, but it does fix the test case.
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 4 ++--
target/riscv/translate.c| 21 +
= double:
- before:
173.10 MFlops
173.93 MFlops
172.11 MFlops
- after:
178.49 MFlops
178.88 MFlops
178.66 MFlops
Signed-off-by: Kito Cheng
Signed-off-by: Emilio G. Cota
Tested-by: Palmer Dabbelt
Thanks for fixing this!
---
fpu/softfloat.c | 10 ++
1 file
From: Nathaniel Graff
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw
!= 134))
abort ();
exit (0);
}
I haven't done any other testing on this, but it does fix the test case.
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 4 ++--
target/riscv/translate.c| 21 +
2 files changed, 23 inserti
From: Jim Wilson
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Message-Id: <20190212230830.9160-1-j...@sifive.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.
The following changes since commit 86e2fca2d7f163c50b80254e0afdd4e16378b3bb:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190319' into
staging (2019-03-19 10:52:45 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv
first
csr register # become 69. We register extra register on gdb to correct
csr offset calculation
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h | 2
From: Jim Wilson
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Message-Id: <20190212230903.9215-1-j...@sifive.com>
Signed-off-by: Palmer D
From: Jim Wilson
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
configure | 1 +
gdb-xml/riscv-32bit-fpu.xml | 6 +-
gdb-xml/riscv-64bit-cpu.xml | 47 +++
gdb-xml/riscv-64bit-csr.xml | 250
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616bd..b11c4ae22fbc 100644
--- a/target
From: Jim Wilson
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 47 +++
gdb-xml/riscv-32bit-csr.xml | 250
gdb
From: Michael Clark
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed
of supervisor timer and
software interrupts by other interrupt controller models.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c| 15
From: Michael Clark
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer
From: Kito Cheng
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.
Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.
Cc: Palmer Dabbelt
Cc: Sagar
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
Makefile.objs | 1 +
target/riscv/cpu_helper.c | 12 +++-
target/riscv/trace-events | 2 ++
3 files changed, 6
to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 145
echo 1 > /sys/devices/system/cpu/cpu2/online
Reported-by: Atish Patra
Cc: Atish Patra
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
d
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820feaa..3199238ba01e 100644
--- a/hw/riscv/sifive_u.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index feea169e1223..d61bce6d5581 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target
From: Bin Meng
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Bin Meng
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv
Francis
Signed-off-by: Palmer Dabbelt
---
include/elf.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index b35347eee767..ea7708a4ea9a 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1393,6 +1393,16 @@ typedef struct {
#define R_RISCV_SET16
On Sun, 10 Feb 2019 12:17:26 PST (-0800), lukas.a...@aisec.fraunhofer.de wrote:
Re-add the previous compatible string "riscv-virtio-soc" to the soc
device tree node to allow U-Boot and Linux to bind machine-specific
drivers to it. The current compatible string "simple-bus" is retained.
This is
On Tue, 19 Mar 2019 04:55:18 PDT (-0700), Peter Maydell wrote:
On Tue, 19 Mar 2019 at 11:45, Palmer Dabbelt wrote:
This is another one that got queued up behind the decode tree stuff. I'd call
this a new feature, but give that it's been on the list and reviewed I'm not
sure if it's OK
On Fri, 15 Mar 2019 11:33:09 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Mar 15, 2019 at 6:45 AM Chih-Min Chao wrote:
This is the 5th version of the patch set, based on the Jim's previous work,
http://lists.nongnu.org/archive/html/qemu-riscv/2019-02/msg00059.html
v4 -> v5:
On Mon, 18 Mar 2019 17:33:38 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis wrote:
On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
wrote:
>
> v3:
> - Add a patch to remove some dead code
> - Rebase on master
> v2:
> - Add a patch for SiFive U
Thanks. If you spin a full patch (ie, "git commit -s" and then "git
show") I can drop it on riscv-qemu-3.1, our backports branch. Otherwise
hopefully we got the bug via the decodetree conversion.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is
On Mon, 18 Mar 2019 01:39:46 PDT (-0700), pbonz...@redhat.com wrote:
On 15/03/19 21:05, Alistair Francis wrote:
Set msi_nonbroken as true for the PLIC.
According to the comment located here:
-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvc.inc.c | 30 -
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c
b/target
The following changes since commit d4e65539e570d5872003710b5a1064489911d33d:
Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190316' into
staging (2019-03-17 14:10:52 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-4.0-rc0
On Fri, 15 Mar 2019 06:51:40 PDT (-0700), Bastian Koppelmann wrote:
during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.
On Fri, Mar 15, 2019 at 4:19 AM Palmer Dabbelt wrote:
> On Fri, 15 Mar 2019 02:06:07 PDT (-0700), Bastian Koppelmann wrote:
> > Hi Alistair
> >
> > On 3/14/19 9:28 PM, Alistair Francis wrote:
> >> On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt
> wrot
On Fri, 15 Mar 2019 02:06:07 PDT (-0700), Bastian Koppelmann wrote:
Hi Alistair
On 3/14/19 9:28 PM, Alistair Francis wrote:
On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt wrote:
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer
On Thu, 14 Mar 2019 21:57:37 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 14, 2019 at 8:59 PM Palmer Dabbelt wrote:
On Thu, 14 Mar 2019 13:28:37 PDT (-0700), alistai...@gmail.com wrote:
> On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt wrote:
>>
>> From: Bas
On Thu, 14 Mar 2019 13:28:37 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt wrote:
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
This commit is the first bad commit
On Thu, 14 Mar 2019 10:30:20 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 14, 2019 at 10:09 AM Michael S. Tsirkin wrote:
On Thu, Mar 14, 2019 at 03:30:30PM +0100, Paolo Bonzini wrote:
> RISC-V targets did not include PCIe ports before the Kconfig transition,
> and grew them
21:06:26 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf4
for you to fetch changes up to 25e6ca30c668783cd72ff97080ff44e141b99f9b:
target/riscv: Remove decode_RV32_64G() (2019-03-13 10:40:50 +0100
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48 +
2 files changed, 58
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvi.inc.c | 49
From: Bastian Koppelmann
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by:
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++
target/riscv/translate.c
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 160
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++
target/riscv/translate.c
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/insn_trans/trans_rvm.inc.c |
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110 ++
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60 +
2 files changed, 66
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +-
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82
target/riscv/translate.c|
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 379
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++--
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++
target/riscv/insn_trans/trans_rvc.inc.c | 75
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c| 4 ++--
3 files changed, 18
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +
target/riscv/translate.c| 59 +---
2 files changed, 81 insertions(+), 71
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 28 ++
target/riscv/insn_trans/trans_rvd.inc.c | 360
From: Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 34 --
1
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn16.decode | 31
target/riscv/insn_trans/trans_rvc.inc.c | 101
target/riscv/translate.c|
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++--
target/riscv/translate.c| 320 ++--
2 files changed, 164 insertions(+), 211
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +---
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +
From: Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 21 +
1 file changed, 1 insertion(+), 20
From: Bastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
On Tue, 12 Mar 2019 10:36:05 PDT (-0700), arm...@redhat.com wrote:
Machines with no maintainer, but at least one supporter:
[...]
= hw/riscv/sifive_e.c =
Palmer Dabbelt (supporter:RISC-V)
Alistair Francis (supporter:RISC-V)
Sagar Karandikar (supporter:RISC-V)
Bastian
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 160
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dab
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79
The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2019-03-11 18:26:37 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv
-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 8 +---
target/riscv/insn32-64.decode | 25 +
target/riscv/insn_trans/trans_rvi.inc.c | 20
target/riscv/translate.c| 7 ---
4
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++
target/riscv/insn_trans
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 379
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 28 ++
target/riscv/insn_trans/trans_rvd.inc.c | 360
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82
target/riscv
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 43 +++
target/riscv/insn_trans/trans_rvc.inc.c | 151
target/riscv
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer
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