[Qemu-devel] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 60

[Qemu-devel] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvi.inc.c | 21 + target/riscv/translate.c| 40 +++-- 3 files changed, 34

[Qemu-devel] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvm.inc.c | 55 ++-- target/riscv/translate.c| 320 ++-- 2 files changed

[Qemu-devel] [PULL 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 31 target/riscv/insn_trans/trans_rvc.inc.c | 101 target/riscv

[Qemu-devel] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++--- target/riscv/translate.c

[Qemu-devel] [PULL 29/29] target/riscv: Remove decode_RV32_64G()

From: Bastian Koppelmann decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 21 + 1

[Qemu-devel] [PULL 21/29] target/riscv: Remove manual decoding from gen_load()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c

[Qemu-devel] [PULL 28/29] target/riscv: Remove gen_system()

From: Bastian Koppelmann with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 34

[Qemu-devel] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 93 + target/riscv/translate.c| 59 +--- 2

Re: [Qemu-devel] [PATCH] riscv/Kconfig: enable PCI_DEVICES

On Mon, 11 Mar 2019 06:52:33 PDT (-0700), pbonz...@redhat.com wrote: On 11/03/19 13:46, Thomas Huth wrote: On 11/03/2019 10.12, David Abdurachmanov wrote: Re-enable PCI_DEVICES for RISC-V. The patch is based on other /Kconfig. Signed-off-by: David Abdurachmanov Fixes: 82a230d5a303

Re: [Qemu-devel] [PULL] target/riscv: Convert to decodetree

On Mon, 04 Mar 2019 11:30:21 PST (-0800), richard.hender...@linaro.org wrote: On 3/4/19 4:52 AM, Bastian Koppelmann wrote: This looks like an unforeseen decodetree problem (CC' Richard). As these 16/32 instructions share the same trans_* function, we emit the same typedef once for 16 bit and

[Qemu-devel] [PULL 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators

From: Bastian Koppelmann only one translate functions of rvc needs to handle special cases. For the other rvc insns we can remove the extra layer of indirection. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode

[Qemu-devel] [PULL 26/34] target/riscv: Remove manual decoding of RV32/64M insn

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvm.inc.c | 55 ++-- target/riscv/translate.c| 320 ++-- 2 files changed

[Qemu-devel] [PULL 13/34] target/riscv: Convert RV32D insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 28 ++ target/riscv/insn_trans/trans_rvd.inc.c | 360

[Qemu-devel] [PULL 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 31 target/riscv/insn_trans/trans_rvc.inc.c | 101 target/riscv

[Qemu-devel] [PULL 21/34] target/riscv: Remove manual decoding from gen_load()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c

[Qemu-devel] [PULL 25/34] target/riscv: Remove shift and slt insn manual decoding

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 93 + target/riscv/translate.c| 59 +--- 2

[Qemu-devel] [PULL 29/34] target/riscv: Remove decode_RV32_64G()

From: Bastian Koppelmann decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 21 + 1

[Qemu-devel] [PULL 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 20 ++-- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvc.inc.c | 24

[Qemu-devel] [PULL 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64

From: Bastian Koppelmann it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them reuse the code generator used for the non compressed insns. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/insn16-32.decode

[Qemu-devel] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64

From: Bastian Koppelmann this finally removes the old decoder functions that we carried along with it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 1 + target/riscv/insn16-32.decode

[Qemu-devel] [PULL 30/34] target/riscv: Convert @cs_2 insns to share translation functions

From: Bastian Koppelmann These all expand simply to R format instructions. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 10 +++--- target/riscv/insn16-64.decode | 24

[Qemu-devel] [PULL 19/34] target/riscv: Remove gen_jalr()

From: Bastian Koppelmann trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c

[Qemu-devel] [PULL 28/34] target/riscv: Remove gen_system()

From: Bastian Koppelmann with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 34

[Qemu-devel] [PULL 22/34] target/riscv: Remove manual decoding from gen_store()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c

[Qemu-devel] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++--- target/riscv/translate.c

[Qemu-devel] [PULL 15/34] target/riscv: Convert RV priv insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode| 15 +++ .../riscv/insn_trans/trans_privileged.inc.c | 110

[Qemu-devel] [PULL 14/34] target/riscv: Convert RV64D insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32-64.decode | 8 + target/riscv/insn_trans/trans_rvd.inc.c | 82 target/riscv

[Qemu-devel] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvi.inc.c | 21 + target/riscv/translate.c| 40 +++-- 3 files changed, 34

[Qemu-devel] [PULL 12/34] target/riscv: Convert RV64F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 60

[Qemu-devel] [PULL 11/34] target/riscv: Convert RV32F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 35 +++ target/riscv/insn_trans/trans_rvf.inc.c | 379

[Qemu-devel] [PULL 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions

From: Bastian Koppelmann gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer

[Qemu-devel] [PULL 20/34] target/riscv: Remove manual decoding from gen_branch()

From: Bastian Koppelmann We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 46

[Qemu-devel] [PULL 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++ target/riscv/insn_trans

[Qemu-devel] [PULL 08/34] target/riscv: Convert RVXM insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32-64.decode | 7 ++ target/riscv/insn32.decode | 10 +++ target/riscv

[Qemu-devel] [PULL 10/34] target/riscv: Convert RV64A insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32-64.decode | 13 +++ target/riscv/insn_trans/trans_rva.inc.c | 58

[Qemu-devel] [PULL 04/34] target/riscv: Convert RV64I load/store insns to decodetree

-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 8 +--- target/riscv/insn32-64.decode | 25 + target/riscv/insn_trans/trans_rvi.inc.c | 20 target/riscv/translate.c| 7 --- 4

[Qemu-devel] [PULL 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 43 +++ target/riscv/insn_trans/trans_rvc.inc.c | 151 target/riscv

[Qemu-devel] [PULL 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC

From: Bastian Koppelmann for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson Acked-by: Alistair Francis Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dab

[Qemu-devel] [PULL 09/34] target/riscv: Convert RV32A insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 17 +++ target/riscv/insn_trans/trans_rva.inc.c | 160

[Qemu-devel] [PULL 07/34] target/riscv: Convert RVXI csr insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvi.inc.c | 79

[Qemu-devel] [PULL 06/34] target/riscv: Convert RVXI fence insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvi.inc.c | 19

[Qemu-devel] [PULL] target/riscv: Convert to decodetree

11:20:49 +) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf2 for you to fetch changes up to 0bcba29464ea9969fc69cd729e4c8bddfb2e18e3: target/riscv: Remaining rvc insn reuse 32 bit translators (2019-03-01 13:16:18 -0800

[Qemu-devel] [PULL 03/34] target/riscv: Convert RV32I load/store insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvi.inc.c | 48

[Qemu-devel] [PULL 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree

From: Bastian Koppelmann we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt

[Qemu-devel] [PULL 02/34] target/riscv: Convert RVXI branch insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 19 ++ target/riscv/insn_trans

Re: [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree

On Wed, 20 Feb 2019 09:02:57 PST (-0800), Bastian Koppelmann wrote: Hi Palmer, On 2/13/19 4:53 PM, Palmer Dabbelt wrote: Palmer: I caused some merge conflicts in Bastian's patch set so I figured I'd attempt to clean these up. As far as I'm concerned v6 was good to go, but since the merge

Re: [Qemu-devel] [PATCH 11/14] MAINTAINERS: Clean up the RISC-V TCG backend section

: Palmer Dabbelt Cc: Alistair Francis Fixes: 7d04ac38959f8115f2a029d81db1c8aac179aa95 Signed-off-by: Thomas Huth Reviewed-by: Palmer Dabbelt I'm assuming this is going in through another tree, but let me know if you want me to take it. Thanks! --- MAINTAINERS | 1 - 1 file changed, 1

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

. ** Changed in: qemu Assignee: (unassigned) => Palmer Dabbelt (palmerdabbelt) ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1815078 Title:

Re: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree

On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote: On 2/13/19 3:15 AM, Palmer Dabbelt wrote: On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote: [snip] Do you, by any chance, have a v7? It looks like there's quite a few merge conflicts here, and while I'm OK fixing them

Re: [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device

On Wed, 13 Feb 2019 10:54:08 PST (-0800), th...@redhat.com wrote: On 2019-02-13 18:14, Peter Maydell wrote: On Wed, 13 Feb 2019 at 00:13, Alistair Francis wrote: I know the other RISC-V files don't do it, but this should go in the hw/gpio directory instead of hw/riscv. It might be nice to

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

It looks like this is fixed as of c7b951718815 ("RISC-V: Implement modular CSR helper interface"), which was merged on January 14th. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1815078 Title:

Re: [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write

On Fri, 08 Feb 2019 10:41:17 PST (-0800), alistai...@gmail.com wrote: On Thu, Feb 7, 2019 at 2:08 AM Fabien Chouteau wrote: Hello Alistair, On 07/02/2019 01:42, Alistair Francis wrote:> > Can you describe what this fixes? > I encountered this problem when I tried to write 0x

Re: [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing

On Fri, 08 Feb 2019 10:57:17 PST (-0800), alistai...@gmail.com wrote: On Wed, Jan 30, 2019 at 2:20 PM Luke Nelson wrote: pmpcfg_csr_{read,write} do not correctly handle accesses to PMP configurations 8 through 15 (CSR pmpcfg2) on RV64. The current code computes the pmpcfg index using:

[Qemu-devel] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn16.decode | 20 ++-- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvc.inc.c | 24 3 files

[Qemu-devel] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

From: Bastian Koppelmann manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson

[Qemu-devel] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvm.inc.c | 55 ++-- target/riscv/translate.c| 320 ++-- 2 files changed, 164 insertions(+), 211

[Qemu-devel] [PATCH v7 29/35] target/riscv: Remove gen_system()

From: Bastian Koppelmann with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 34 -- 1

[Qemu-devel] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn16.decode | 43 +++ target/riscv/insn_trans/trans_rvc.inc.c | 151 target/riscv/translate.c| 118

[Qemu-devel] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn16.decode | 31 target/riscv/insn_trans/trans_rvc.inc.c | 101 target/riscv/translate.c|

[Qemu-devel] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 8 + target/riscv/insn_trans/trans_rvd.inc.c | 76 +++ target/riscv/translate.c|

[Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode| 15 +++ .../riscv/insn_trans/trans_privileged.inc.c | 110 ++

[Qemu-devel] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++ target/riscv/insn_trans/trans_rvc.inc.c | 75

[Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 35 +++ target/riscv/insn_trans/trans_rvf.inc.c | 353

[Qemu-devel] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64

From: Bastian Koppelmann this finally removes the old decoder functions that we carried along with it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/Makefile.objs | 1 + target/riscv/insn16-32.decode | 24

[Qemu-devel] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 35 +++--

[Qemu-devel] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 28 ++ target/riscv/insn_trans/trans_rvd.inc.c | 335

[Qemu-devel] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 27 +

[Qemu-devel] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 93 + target/riscv/translate.c| 59 +--- 2 files changed, 81 insertions(+), 71

[Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr()

From: Bastian Koppelmann trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 28 +-

[Qemu-devel] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions

From: Bastian Koppelmann gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt ---

[Qemu-devel] [PATCH v7 04/35] target/riscv: Convert RV32I load/store insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvi.inc.c | 48 + 2 files changed, 58

[Qemu-devel] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions

From: Bastian Koppelmann These all expand simply to R format instructions. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/Makefile.objs | 10 +++--- target/riscv/insn16-64.decode | 24 ++ target/riscv/insn16.decode

[Qemu-devel] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch()

From: Bastian Koppelmann We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 46 +---

[Qemu-devel] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++--- target/riscv/translate.c| 4 ++-- 3 files changed, 18

[Qemu-devel] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree

From: Bastian Koppelmann we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt ---

[Qemu-devel] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree

From: Bastian Koppelmann this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by:

[Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G()

From: Bastian Koppelmann decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 21 + 1 file changed, 1 insertion(+), 20

[Qemu-devel] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 7 ++ target/riscv/insn32.decode | 10 +++ target/riscv/insn_trans/trans_rvm.inc.c |

[Qemu-devel] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators

From: Bastian Koppelmann only one translate functions of rvc needs to handle special cases. For the other rvc insns we can remove the extra layer of indirection. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn16.decode | 37

[Qemu-devel] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 13 +++ target/riscv/insn_trans/trans_rva.inc.c | 58 ++ target/riscv/translate.c

[Qemu-devel] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 17 +++ target/riscv/insn_trans/trans_rva.inc.c | 149

[Qemu-devel] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64

From: Bastian Koppelmann it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them reuse the code generator used for the non compressed insns. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn16-32.decode | 7 +

[Qemu-devel] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 58 - 2 files changed, 63

[Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext

From: Bastian Koppelmann CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis

[Qemu-devel] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvi.inc.c | 79 +

[Qemu-devel] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvi.inc.c | 19 +++ target/riscv/translate.c

[Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree

RVC by reusing as much as possible from the RVG decoder as suggested by Richard. [Patch 31-35] full tree available at https://github.com/palmer-dabbelt/qemu/tree/riscv-dt-v7 Cheers, Bastian v6 -> v7: - Rebased on top of riscv-for-master-4.0-sf1, which contains a refactor

[Qemu-devel] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 19 ++ target/riscv/insn_trans/trans_rvi.inc.c | 49

[Qemu-devel] [PATCH v7 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC

From: Bastian Koppelmann for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson Acked-by: Alistair Francis Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/Makefile.objs

[Qemu-devel] [PULL 08/11] RISC-V: Add misa runtime write support

by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h

[Qemu-devel] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer

Michael is no longer employed by SiFive and does not want to continue maintianing the RISC-V port. Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a2da141a928f..e170a4c73376 100644 --- a/MAINTAINERS +++ b

[Qemu-devel] [PULL 07/11] RISC-V: Add misa.MAFD checks to translate

Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 158 +++ 1 file changed, 158 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bb80387088e2..b7176cbf98e1 100644 --- a/target/riscv/translate.c +++ b/target/riscv

[Qemu-devel] [PULL 11/11] riscv: Ensure the kernel start address is correctly cast

. The reason is that the binary was loaded to a negative address. Signed-off-by: Alistair Francis Suggested-by: Alexander Graf Reported-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv

[Qemu-devel] [PULL 02/11] RISC-V: Mark mstatus.fs dirty

.FS so the bug in the first spin of this patch has been fixed in a prior commit. Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Co-authored-by: Richard Henderson Co-authored-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c |

[Qemu-devel] [PULL 04/11] RISC-V: Use riscv prefix consistently on cpu helpers

* rename riscv_set_mode to riscv_cpu_set_mode Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- linux-user/riscv/signal.c | 4 ++-- target/riscv/cpu.h| 21 ++--- target/riscv/cpu_helper.c | 10

[Qemu-devel] [PULL 03/11] RISC-V: Implement mstatus.TSR/TW/TVM

From: Michael Clark This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Co-authored-by: Matthew Suozzo Co-authored-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cs

[Qemu-devel] [PULL 10/11] target/riscv: fix counter-enable checks in ctr()

From: Xi Wang Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt

[Qemu-devel] [PULL 05/11] RISC-V: Add priv_ver to DisasContext

From: Alistair Francis The gen methods should access state from DisasContext. Add priv_ver field to the DisasContext struct. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 7 +-- 1 file changed, 5 insertions

[Qemu-devel] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1

) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf1 for you to fetch changes up to 40e46e516d90c2dfe8e8de3741c1c65f1b526502: riscv: Ensure the kernel start address is correctly cast (2019-02-11 15:56:22 -0800

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